mv_pci.c revision 294510
1/*- 2 * Copyright (c) 2008 MARVELL INTERNATIONAL LTD. 3 * Copyright (c) 2010 The FreeBSD Foundation 4 * Copyright (c) 2010-2015 Semihalf 5 * All rights reserved. 6 * 7 * Developed by Semihalf. 8 * 9 * Portions of this software were developed by Semihalf 10 * under sponsorship from the FreeBSD Foundation. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 3. Neither the name of MARVELL nor the names of contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 */ 36 37/* 38 * Marvell integrated PCI/PCI-Express controller driver. 39 */ 40 41#include <sys/cdefs.h> 42__FBSDID("$FreeBSD: head/sys/arm/mv/mv_pci.c 294510 2016-01-21 16:42:52Z andrew $"); 43 44#include <sys/param.h> 45#include <sys/systm.h> 46#include <sys/kernel.h> 47#include <sys/lock.h> 48#include <sys/malloc.h> 49#include <sys/module.h> 50#include <sys/mutex.h> 51#include <sys/queue.h> 52#include <sys/bus.h> 53#include <sys/rman.h> 54#include <sys/endian.h> 55 56#include <machine/fdt.h> 57#include <machine/intr.h> 58 59#include <vm/vm.h> 60#include <vm/pmap.h> 61 62#include <dev/fdt/fdt_common.h> 63#include <dev/ofw/ofw_bus.h> 64#include <dev/ofw/ofw_pci.h> 65#include <dev/ofw/ofw_bus_subr.h> 66#include <dev/pci/pcivar.h> 67#include <dev/pci/pcireg.h> 68#include <dev/pci/pcib_private.h> 69 70#include "ofw_bus_if.h" 71#include "pcib_if.h" 72 73#include <machine/devmap.h> 74#include <machine/resource.h> 75#include <machine/bus.h> 76 77#include <arm/mv/mvreg.h> 78#include <arm/mv/mvvar.h> 79#include <arm/mv/mvwin.h> 80 81#ifdef DEBUG 82#define debugf(fmt, args...) do { printf(fmt,##args); } while (0) 83#else 84#define debugf(fmt, args...) 85#endif 86 87/* 88 * Code and data related to fdt-based PCI configuration. 89 * 90 * This stuff used to be in dev/fdt/fdt_pci.c and fdt_common.h, but it was 91 * always Marvell-specific so that was deleted and the code now lives here. 92 */ 93 94struct mv_pci_range { 95 u_long base_pci; 96 u_long base_parent; 97 u_long len; 98}; 99 100#define FDT_RANGES_CELLS ((3 + 3 + 2) * 2) 101 102static void 103mv_pci_range_dump(struct mv_pci_range *range) 104{ 105#ifdef DEBUG 106 printf("\n"); 107 printf(" base_pci = 0x%08lx\n", range->base_pci); 108 printf(" base_par = 0x%08lx\n", range->base_parent); 109 printf(" len = 0x%08lx\n", range->len); 110#endif 111} 112 113static int 114mv_pci_ranges_decode(phandle_t node, struct mv_pci_range *io_space, 115 struct mv_pci_range *mem_space) 116{ 117 pcell_t ranges[FDT_RANGES_CELLS]; 118 struct mv_pci_range *pci_space; 119 pcell_t addr_cells, size_cells, par_addr_cells; 120 pcell_t *rangesptr; 121 pcell_t cell0, cell1, cell2; 122 int tuple_size, tuples, i, rv, offset_cells, len; 123 124 /* 125 * Retrieve 'ranges' property. 126 */ 127 if ((fdt_addrsize_cells(node, &addr_cells, &size_cells)) != 0) 128 return (EINVAL); 129 if (addr_cells != 3 || size_cells != 2) 130 return (ERANGE); 131 132 par_addr_cells = fdt_parent_addr_cells(node); 133 if (par_addr_cells > 3) 134 return (ERANGE); 135 136 len = OF_getproplen(node, "ranges"); 137 if (len > sizeof(ranges)) 138 return (ENOMEM); 139 140 if (OF_getprop(node, "ranges", ranges, sizeof(ranges)) <= 0) 141 return (EINVAL); 142 143 tuple_size = sizeof(pcell_t) * (addr_cells + par_addr_cells + 144 size_cells); 145 tuples = len / tuple_size; 146 147 /* 148 * Initialize the ranges so that we don't have to worry about 149 * having them all defined in the FDT. In particular, it is 150 * perfectly fine not to want I/O space on PCI busses. 151 */ 152 bzero(io_space, sizeof(*io_space)); 153 bzero(mem_space, sizeof(*mem_space)); 154 155 rangesptr = &ranges[0]; 156 offset_cells = 0; 157 for (i = 0; i < tuples; i++) { 158 cell0 = fdt_data_get((void *)rangesptr, 1); 159 rangesptr++; 160 cell1 = fdt_data_get((void *)rangesptr, 1); 161 rangesptr++; 162 cell2 = fdt_data_get((void *)rangesptr, 1); 163 rangesptr++; 164 165 if (cell0 & 0x02000000) { 166 pci_space = mem_space; 167 } else if (cell0 & 0x01000000) { 168 pci_space = io_space; 169 } else { 170 rv = ERANGE; 171 goto out; 172 } 173 174 if (par_addr_cells == 3) { 175 /* 176 * This is a PCI subnode 'ranges'. Skip cell0 and 177 * cell1 of this entry and only use cell2. 178 */ 179 offset_cells = 2; 180 rangesptr += offset_cells; 181 } 182 183 if ((par_addr_cells - offset_cells) > 2) { 184 rv = ERANGE; 185 goto out; 186 } 187 pci_space->base_parent = fdt_data_get((void *)rangesptr, 188 par_addr_cells - offset_cells); 189 rangesptr += par_addr_cells - offset_cells; 190 191 if (size_cells > 2) { 192 rv = ERANGE; 193 goto out; 194 } 195 pci_space->len = fdt_data_get((void *)rangesptr, size_cells); 196 rangesptr += size_cells; 197 198 pci_space->base_pci = cell2; 199 } 200 rv = 0; 201out: 202 return (rv); 203} 204 205static int 206mv_pci_ranges(phandle_t node, struct mv_pci_range *io_space, 207 struct mv_pci_range *mem_space) 208{ 209 int err; 210 211 debugf("Processing PCI node: %x\n", node); 212 if ((err = mv_pci_ranges_decode(node, io_space, mem_space)) != 0) { 213 debugf("could not decode parent PCI node 'ranges'\n"); 214 return (err); 215 } 216 217 debugf("Post fixup dump:\n"); 218 mv_pci_range_dump(io_space); 219 mv_pci_range_dump(mem_space); 220 return (0); 221} 222 223int 224mv_pci_devmap(phandle_t node, struct arm_devmap_entry *devmap, vm_offset_t io_va, 225 vm_offset_t mem_va) 226{ 227 struct mv_pci_range io_space, mem_space; 228 int error; 229 230 if ((error = mv_pci_ranges_decode(node, &io_space, &mem_space)) != 0) 231 return (error); 232 233 devmap->pd_va = (io_va ? io_va : io_space.base_parent); 234 devmap->pd_pa = io_space.base_parent; 235 devmap->pd_size = io_space.len; 236 devmap->pd_prot = VM_PROT_READ | VM_PROT_WRITE; 237 devmap->pd_cache = PTE_DEVICE; 238 devmap++; 239 240 devmap->pd_va = (mem_va ? mem_va : mem_space.base_parent); 241 devmap->pd_pa = mem_space.base_parent; 242 devmap->pd_size = mem_space.len; 243 devmap->pd_prot = VM_PROT_READ | VM_PROT_WRITE; 244 devmap->pd_cache = PTE_DEVICE; 245 return (0); 246} 247 248/* 249 * Code and data related to the Marvell pcib driver. 250 */ 251 252#define PCI_CFG_ENA (1U << 31) 253#define PCI_CFG_BUS(bus) (((bus) & 0xff) << 16) 254#define PCI_CFG_DEV(dev) (((dev) & 0x1f) << 11) 255#define PCI_CFG_FUN(fun) (((fun) & 0x7) << 8) 256#define PCI_CFG_PCIE_REG(reg) ((reg) & 0xfc) 257 258#define PCI_REG_CFG_ADDR 0x0C78 259#define PCI_REG_CFG_DATA 0x0C7C 260 261#define PCIE_REG_CFG_ADDR 0x18F8 262#define PCIE_REG_CFG_DATA 0x18FC 263#define PCIE_REG_CONTROL 0x1A00 264#define PCIE_CTRL_LINK1X 0x00000001 265#define PCIE_REG_STATUS 0x1A04 266#define PCIE_REG_IRQ_MASK 0x1910 267 268#define PCIE_CONTROL_ROOT_CMPLX (1 << 1) 269#define PCIE_CONTROL_HOT_RESET (1 << 24) 270 271#define PCIE_LINK_TIMEOUT 1000000 272 273#define PCIE_STATUS_LINK_DOWN 1 274#define PCIE_STATUS_DEV_OFFS 16 275 276/* Minimum PCI Memory and I/O allocations taken from PCI spec (in bytes) */ 277#define PCI_MIN_IO_ALLOC 4 278#define PCI_MIN_MEM_ALLOC 16 279 280#define BITS_PER_UINT32 (NBBY * sizeof(uint32_t)) 281 282struct mv_pcib_softc { 283 device_t sc_dev; 284 285 struct rman sc_mem_rman; 286 bus_addr_t sc_mem_base; 287 bus_addr_t sc_mem_size; 288 uint32_t sc_mem_map[MV_PCI_MEM_SLICE_SIZE / 289 (PCI_MIN_MEM_ALLOC * BITS_PER_UINT32)]; 290 int sc_win_target; 291 int sc_mem_win_attr; 292 293 struct rman sc_io_rman; 294 bus_addr_t sc_io_base; 295 bus_addr_t sc_io_size; 296 uint32_t sc_io_map[MV_PCI_IO_SLICE_SIZE / 297 (PCI_MIN_IO_ALLOC * BITS_PER_UINT32)]; 298 int sc_io_win_attr; 299 300 struct resource *sc_res; 301 bus_space_handle_t sc_bsh; 302 bus_space_tag_t sc_bst; 303 int sc_rid; 304 305 struct mtx sc_msi_mtx; 306 uint32_t sc_msi_bitmap; 307 308 int sc_busnr; /* Host bridge bus number */ 309 int sc_devnr; /* Host bridge device number */ 310 int sc_type; 311 int sc_mode; /* Endpoint / Root Complex */ 312 313 struct ofw_bus_iinfo sc_pci_iinfo; 314}; 315 316/* Local forward prototypes */ 317static int mv_pcib_decode_win(phandle_t, struct mv_pcib_softc *); 318static void mv_pcib_hw_cfginit(void); 319static uint32_t mv_pcib_hw_cfgread(struct mv_pcib_softc *, u_int, u_int, 320 u_int, u_int, int); 321static void mv_pcib_hw_cfgwrite(struct mv_pcib_softc *, u_int, u_int, 322 u_int, u_int, uint32_t, int); 323static int mv_pcib_init(struct mv_pcib_softc *, int, int); 324static int mv_pcib_init_all_bars(struct mv_pcib_softc *, int, int, int, int); 325static void mv_pcib_init_bridge(struct mv_pcib_softc *, int, int, int); 326static inline void pcib_write_irq_mask(struct mv_pcib_softc *, uint32_t); 327static void mv_pcib_enable(struct mv_pcib_softc *, uint32_t); 328static int mv_pcib_mem_init(struct mv_pcib_softc *); 329 330/* Forward prototypes */ 331static int mv_pcib_probe(device_t); 332static int mv_pcib_attach(device_t); 333 334static struct resource *mv_pcib_alloc_resource(device_t, device_t, int, int *, 335 u_long, u_long, u_long, u_int); 336static int mv_pcib_release_resource(device_t, device_t, int, int, 337 struct resource *); 338static int mv_pcib_read_ivar(device_t, device_t, int, uintptr_t *); 339static int mv_pcib_write_ivar(device_t, device_t, int, uintptr_t); 340 341static int mv_pcib_maxslots(device_t); 342static uint32_t mv_pcib_read_config(device_t, u_int, u_int, u_int, u_int, int); 343static void mv_pcib_write_config(device_t, u_int, u_int, u_int, u_int, 344 uint32_t, int); 345static int mv_pcib_route_interrupt(device_t, device_t, int); 346#if defined(SOC_MV_ARMADAXP) 347static int mv_pcib_alloc_msi(device_t, device_t, int, int, int *); 348static int mv_pcib_map_msi(device_t, device_t, int, uint64_t *, uint32_t *); 349static int mv_pcib_release_msi(device_t, device_t, int, int *); 350#endif 351 352/* 353 * Bus interface definitions. 354 */ 355static device_method_t mv_pcib_methods[] = { 356 /* Device interface */ 357 DEVMETHOD(device_probe, mv_pcib_probe), 358 DEVMETHOD(device_attach, mv_pcib_attach), 359 360 /* Bus interface */ 361 DEVMETHOD(bus_read_ivar, mv_pcib_read_ivar), 362 DEVMETHOD(bus_write_ivar, mv_pcib_write_ivar), 363 DEVMETHOD(bus_alloc_resource, mv_pcib_alloc_resource), 364 DEVMETHOD(bus_release_resource, mv_pcib_release_resource), 365 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 366 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 367 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 368 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 369 370 /* pcib interface */ 371 DEVMETHOD(pcib_maxslots, mv_pcib_maxslots), 372 DEVMETHOD(pcib_read_config, mv_pcib_read_config), 373 DEVMETHOD(pcib_write_config, mv_pcib_write_config), 374 DEVMETHOD(pcib_route_interrupt, mv_pcib_route_interrupt), 375 376#if defined(SOC_MV_ARMADAXP) 377 DEVMETHOD(pcib_alloc_msi, mv_pcib_alloc_msi), 378 DEVMETHOD(pcib_release_msi, mv_pcib_release_msi), 379 DEVMETHOD(pcib_map_msi, mv_pcib_map_msi), 380#endif 381 382 /* OFW bus interface */ 383 DEVMETHOD(ofw_bus_get_compat, ofw_bus_gen_get_compat), 384 DEVMETHOD(ofw_bus_get_model, ofw_bus_gen_get_model), 385 DEVMETHOD(ofw_bus_get_name, ofw_bus_gen_get_name), 386 DEVMETHOD(ofw_bus_get_node, ofw_bus_gen_get_node), 387 DEVMETHOD(ofw_bus_get_type, ofw_bus_gen_get_type), 388 389 DEVMETHOD_END 390}; 391 392static driver_t mv_pcib_driver = { 393 "pcib", 394 mv_pcib_methods, 395 sizeof(struct mv_pcib_softc), 396}; 397 398devclass_t pcib_devclass; 399 400DRIVER_MODULE(pcib, ofwbus, mv_pcib_driver, pcib_devclass, 0, 0); 401 402static struct mtx pcicfg_mtx; 403 404static int 405mv_pcib_probe(device_t self) 406{ 407 phandle_t node; 408 409 node = ofw_bus_get_node(self); 410 if (!fdt_is_type(node, "pci")) 411 return (ENXIO); 412 413 if (!(ofw_bus_is_compatible(self, "mrvl,pcie") || 414 ofw_bus_is_compatible(self, "mrvl,pci"))) 415 return (ENXIO); 416 417 device_set_desc(self, "Marvell Integrated PCI/PCI-E Controller"); 418 return (BUS_PROBE_DEFAULT); 419} 420 421static int 422mv_pcib_attach(device_t self) 423{ 424 struct mv_pcib_softc *sc; 425 phandle_t node, parnode; 426 uint32_t val, unit; 427 int err; 428 429 sc = device_get_softc(self); 430 sc->sc_dev = self; 431 unit = fdt_get_unit(self); 432 433 434 node = ofw_bus_get_node(self); 435 parnode = OF_parent(node); 436 if (fdt_is_compatible(node, "mrvl,pcie")) { 437 sc->sc_type = MV_TYPE_PCIE; 438 sc->sc_win_target = MV_WIN_PCIE_TARGET(unit); 439 sc->sc_mem_win_attr = MV_WIN_PCIE_MEM_ATTR(unit); 440 sc->sc_io_win_attr = MV_WIN_PCIE_IO_ATTR(unit); 441 } else if (fdt_is_compatible(node, "mrvl,pci")) { 442 sc->sc_type = MV_TYPE_PCI; 443 sc->sc_win_target = MV_WIN_PCI_TARGET; 444 sc->sc_mem_win_attr = MV_WIN_PCI_MEM_ATTR; 445 sc->sc_io_win_attr = MV_WIN_PCI_IO_ATTR; 446 } else 447 return (ENXIO); 448 449 /* 450 * Retrieve our mem-mapped registers range. 451 */ 452 sc->sc_rid = 0; 453 sc->sc_res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &sc->sc_rid, 454 RF_ACTIVE); 455 if (sc->sc_res == NULL) { 456 device_printf(self, "could not map memory\n"); 457 return (ENXIO); 458 } 459 sc->sc_bst = rman_get_bustag(sc->sc_res); 460 sc->sc_bsh = rman_get_bushandle(sc->sc_res); 461 462 val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, PCIE_REG_CONTROL); 463 sc->sc_mode = (val & PCIE_CONTROL_ROOT_CMPLX ? MV_MODE_ROOT : 464 MV_MODE_ENDPOINT); 465 466 /* 467 * Get PCI interrupt info. 468 */ 469 if (sc->sc_mode == MV_MODE_ROOT) 470 ofw_bus_setup_iinfo(node, &sc->sc_pci_iinfo, sizeof(pcell_t)); 471 472 /* 473 * Configure decode windows for PCI(E) access. 474 */ 475 if (mv_pcib_decode_win(node, sc) != 0) 476 return (ENXIO); 477 478 mv_pcib_hw_cfginit(); 479 480 /* 481 * Enable PCIE device. 482 */ 483 mv_pcib_enable(sc, unit); 484 485 /* 486 * Memory management. 487 */ 488 err = mv_pcib_mem_init(sc); 489 if (err) 490 return (err); 491 492 if (sc->sc_mode == MV_MODE_ROOT) { 493 err = mv_pcib_init(sc, sc->sc_busnr, 494 mv_pcib_maxslots(sc->sc_dev)); 495 if (err) 496 goto error; 497 498 device_add_child(self, "pci", -1); 499 } else { 500 sc->sc_devnr = 1; 501 bus_space_write_4(sc->sc_bst, sc->sc_bsh, 502 PCIE_REG_STATUS, 1 << PCIE_STATUS_DEV_OFFS); 503 device_add_child(self, "pci_ep", -1); 504 } 505 506 mtx_init(&sc->sc_msi_mtx, "msi_mtx", NULL, MTX_DEF); 507 return (bus_generic_attach(self)); 508 509error: 510 /* XXX SYS_RES_ should be released here */ 511 rman_fini(&sc->sc_mem_rman); 512 rman_fini(&sc->sc_io_rman); 513 514 return (err); 515} 516 517static void 518mv_pcib_enable(struct mv_pcib_softc *sc, uint32_t unit) 519{ 520 uint32_t val; 521#if !defined(SOC_MV_ARMADAXP) 522 int timeout; 523 524 /* 525 * Check if PCIE device is enabled. 526 */ 527 if (read_cpu_ctrl(CPU_CONTROL) & CPU_CONTROL_PCIE_DISABLE(unit)) { 528 write_cpu_ctrl(CPU_CONTROL, read_cpu_ctrl(CPU_CONTROL) & 529 ~(CPU_CONTROL_PCIE_DISABLE(unit))); 530 531 timeout = PCIE_LINK_TIMEOUT; 532 val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, 533 PCIE_REG_STATUS); 534 while (((val & PCIE_STATUS_LINK_DOWN) == 1) && (timeout > 0)) { 535 DELAY(1000); 536 timeout -= 1000; 537 val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, 538 PCIE_REG_STATUS); 539 } 540 } 541#endif 542 543 544 if (sc->sc_mode == MV_MODE_ROOT) { 545 /* 546 * Enable PCI bridge. 547 */ 548 val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, PCIR_COMMAND); 549 val |= PCIM_CMD_SERRESPEN | PCIM_CMD_BUSMASTEREN | 550 PCIM_CMD_MEMEN | PCIM_CMD_PORTEN; 551 bus_space_write_4(sc->sc_bst, sc->sc_bsh, PCIR_COMMAND, val); 552 } 553} 554 555static int 556mv_pcib_mem_init(struct mv_pcib_softc *sc) 557{ 558 int err; 559 560 /* 561 * Memory management. 562 */ 563 sc->sc_mem_rman.rm_type = RMAN_ARRAY; 564 err = rman_init(&sc->sc_mem_rman); 565 if (err) 566 return (err); 567 568 sc->sc_io_rman.rm_type = RMAN_ARRAY; 569 err = rman_init(&sc->sc_io_rman); 570 if (err) { 571 rman_fini(&sc->sc_mem_rman); 572 return (err); 573 } 574 575 err = rman_manage_region(&sc->sc_mem_rman, sc->sc_mem_base, 576 sc->sc_mem_base + sc->sc_mem_size - 1); 577 if (err) 578 goto error; 579 580 err = rman_manage_region(&sc->sc_io_rman, sc->sc_io_base, 581 sc->sc_io_base + sc->sc_io_size - 1); 582 if (err) 583 goto error; 584 585 return (0); 586 587error: 588 rman_fini(&sc->sc_mem_rman); 589 rman_fini(&sc->sc_io_rman); 590 591 return (err); 592} 593 594static inline uint32_t 595pcib_bit_get(uint32_t *map, uint32_t bit) 596{ 597 uint32_t n = bit / BITS_PER_UINT32; 598 599 bit = bit % BITS_PER_UINT32; 600 return (map[n] & (1 << bit)); 601} 602 603static inline void 604pcib_bit_set(uint32_t *map, uint32_t bit) 605{ 606 uint32_t n = bit / BITS_PER_UINT32; 607 608 bit = bit % BITS_PER_UINT32; 609 map[n] |= (1 << bit); 610} 611 612static inline uint32_t 613pcib_map_check(uint32_t *map, uint32_t start, uint32_t bits) 614{ 615 uint32_t i; 616 617 for (i = start; i < start + bits; i++) 618 if (pcib_bit_get(map, i)) 619 return (0); 620 621 return (1); 622} 623 624static inline void 625pcib_map_set(uint32_t *map, uint32_t start, uint32_t bits) 626{ 627 uint32_t i; 628 629 for (i = start; i < start + bits; i++) 630 pcib_bit_set(map, i); 631} 632 633/* 634 * The idea of this allocator is taken from ARM No-Cache memory 635 * management code (sys/arm/arm/vm_machdep.c). 636 */ 637static bus_addr_t 638pcib_alloc(struct mv_pcib_softc *sc, uint32_t smask) 639{ 640 uint32_t bits, bits_limit, i, *map, min_alloc, size; 641 bus_addr_t addr = 0; 642 bus_addr_t base; 643 644 if (smask & 1) { 645 base = sc->sc_io_base; 646 min_alloc = PCI_MIN_IO_ALLOC; 647 bits_limit = sc->sc_io_size / min_alloc; 648 map = sc->sc_io_map; 649 smask &= ~0x3; 650 } else { 651 base = sc->sc_mem_base; 652 min_alloc = PCI_MIN_MEM_ALLOC; 653 bits_limit = sc->sc_mem_size / min_alloc; 654 map = sc->sc_mem_map; 655 smask &= ~0xF; 656 } 657 658 size = ~smask + 1; 659 bits = size / min_alloc; 660 661 for (i = 0; i + bits <= bits_limit; i += bits) 662 if (pcib_map_check(map, i, bits)) { 663 pcib_map_set(map, i, bits); 664 addr = base + (i * min_alloc); 665 return (addr); 666 } 667 668 return (addr); 669} 670 671static int 672mv_pcib_init_bar(struct mv_pcib_softc *sc, int bus, int slot, int func, 673 int barno) 674{ 675 uint32_t addr, bar; 676 int reg, width; 677 678 reg = PCIR_BAR(barno); 679 680 /* 681 * Need to init the BAR register with 0xffffffff before correct 682 * value can be read. 683 */ 684 mv_pcib_write_config(sc->sc_dev, bus, slot, func, reg, ~0, 4); 685 bar = mv_pcib_read_config(sc->sc_dev, bus, slot, func, reg, 4); 686 if (bar == 0) 687 return (1); 688 689 /* Calculate BAR size: 64 or 32 bit (in 32-bit units) */ 690 width = ((bar & 7) == 4) ? 2 : 1; 691 692 addr = pcib_alloc(sc, bar); 693 if (!addr) 694 return (-1); 695 696 if (bootverbose) 697 printf("PCI %u:%u:%u: reg %x: smask=%08x: addr=%08x\n", 698 bus, slot, func, reg, bar, addr); 699 700 mv_pcib_write_config(sc->sc_dev, bus, slot, func, reg, addr, 4); 701 if (width == 2) 702 mv_pcib_write_config(sc->sc_dev, bus, slot, func, reg + 4, 703 0, 4); 704 705 return (width); 706} 707 708static void 709mv_pcib_init_bridge(struct mv_pcib_softc *sc, int bus, int slot, int func) 710{ 711 bus_addr_t io_base, mem_base; 712 uint32_t io_limit, mem_limit; 713 int secbus; 714 715 io_base = sc->sc_io_base; 716 io_limit = io_base + sc->sc_io_size - 1; 717 mem_base = sc->sc_mem_base; 718 mem_limit = mem_base + sc->sc_mem_size - 1; 719 720 /* Configure I/O decode registers */ 721 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_IOBASEL_1, 722 io_base >> 8, 1); 723 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_IOBASEH_1, 724 io_base >> 16, 2); 725 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_IOLIMITL_1, 726 io_limit >> 8, 1); 727 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_IOLIMITH_1, 728 io_limit >> 16, 2); 729 730 /* Configure memory decode registers */ 731 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_MEMBASE_1, 732 mem_base >> 16, 2); 733 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_MEMLIMIT_1, 734 mem_limit >> 16, 2); 735 736 /* Disable memory prefetch decode */ 737 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_PMBASEL_1, 738 0x10, 2); 739 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_PMBASEH_1, 740 0x0, 4); 741 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_PMLIMITL_1, 742 0xF, 2); 743 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_PMLIMITH_1, 744 0x0, 4); 745 746 secbus = mv_pcib_read_config(sc->sc_dev, bus, slot, func, 747 PCIR_SECBUS_1, 1); 748 749 /* Configure buses behind the bridge */ 750 mv_pcib_init(sc, secbus, PCI_SLOTMAX); 751} 752 753static int 754mv_pcib_init(struct mv_pcib_softc *sc, int bus, int maxslot) 755{ 756 int slot, func, maxfunc, error; 757 uint8_t hdrtype, command, class, subclass; 758 759 for (slot = 0; slot <= maxslot; slot++) { 760 maxfunc = 0; 761 for (func = 0; func <= maxfunc; func++) { 762 hdrtype = mv_pcib_read_config(sc->sc_dev, bus, slot, 763 func, PCIR_HDRTYPE, 1); 764 765 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE) 766 continue; 767 768 if (func == 0 && (hdrtype & PCIM_MFDEV)) 769 maxfunc = PCI_FUNCMAX; 770 771 command = mv_pcib_read_config(sc->sc_dev, bus, slot, 772 func, PCIR_COMMAND, 1); 773 command &= ~(PCIM_CMD_MEMEN | PCIM_CMD_PORTEN); 774 mv_pcib_write_config(sc->sc_dev, bus, slot, func, 775 PCIR_COMMAND, command, 1); 776 777 error = mv_pcib_init_all_bars(sc, bus, slot, func, 778 hdrtype); 779 780 if (error) 781 return (error); 782 783 command |= PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN | 784 PCIM_CMD_PORTEN; 785 mv_pcib_write_config(sc->sc_dev, bus, slot, func, 786 PCIR_COMMAND, command, 1); 787 788 /* Handle PCI-PCI bridges */ 789 class = mv_pcib_read_config(sc->sc_dev, bus, slot, 790 func, PCIR_CLASS, 1); 791 subclass = mv_pcib_read_config(sc->sc_dev, bus, slot, 792 func, PCIR_SUBCLASS, 1); 793 794 if (class != PCIC_BRIDGE || 795 subclass != PCIS_BRIDGE_PCI) 796 continue; 797 798 mv_pcib_init_bridge(sc, bus, slot, func); 799 } 800 } 801 802 /* Enable all ABCD interrupts */ 803 pcib_write_irq_mask(sc, (0xF << 24)); 804 805 return (0); 806} 807 808static int 809mv_pcib_init_all_bars(struct mv_pcib_softc *sc, int bus, int slot, 810 int func, int hdrtype) 811{ 812 int maxbar, bar, i; 813 814 maxbar = (hdrtype & PCIM_HDRTYPE) ? 0 : 6; 815 bar = 0; 816 817 /* Program the base address registers */ 818 while (bar < maxbar) { 819 i = mv_pcib_init_bar(sc, bus, slot, func, bar); 820 bar += i; 821 if (i < 0) { 822 device_printf(sc->sc_dev, 823 "PCI IO/Memory space exhausted\n"); 824 return (ENOMEM); 825 } 826 } 827 828 return (0); 829} 830 831static struct resource * 832mv_pcib_alloc_resource(device_t dev, device_t child, int type, int *rid, 833 u_long start, u_long end, u_long count, u_int flags) 834{ 835 struct mv_pcib_softc *sc = device_get_softc(dev); 836 struct rman *rm = NULL; 837 struct resource *res; 838 839 switch (type) { 840 case SYS_RES_IOPORT: 841 rm = &sc->sc_io_rman; 842 break; 843 case SYS_RES_MEMORY: 844 rm = &sc->sc_mem_rman; 845 break; 846 default: 847 return (BUS_ALLOC_RESOURCE(device_get_parent(dev), dev, 848 type, rid, start, end, count, flags)); 849 }; 850 851 if ((start == 0UL) && (end == ~0UL)) { 852 start = sc->sc_mem_base; 853 end = sc->sc_mem_base + sc->sc_mem_size - 1; 854 count = sc->sc_mem_size; 855 } 856 857 if ((start < sc->sc_mem_base) || (start + count - 1 != end) || 858 (end > sc->sc_mem_base + sc->sc_mem_size - 1)) 859 return (NULL); 860 861 res = rman_reserve_resource(rm, start, end, count, flags, child); 862 if (res == NULL) 863 return (NULL); 864 865 rman_set_rid(res, *rid); 866 rman_set_bustag(res, fdtbus_bs_tag); 867 rman_set_bushandle(res, start); 868 869 if (flags & RF_ACTIVE) 870 if (bus_activate_resource(child, type, *rid, res)) { 871 rman_release_resource(res); 872 return (NULL); 873 } 874 875 return (res); 876} 877 878static int 879mv_pcib_release_resource(device_t dev, device_t child, int type, int rid, 880 struct resource *res) 881{ 882 883 if (type != SYS_RES_IOPORT && type != SYS_RES_MEMORY) 884 return (BUS_RELEASE_RESOURCE(device_get_parent(dev), child, 885 type, rid, res)); 886 887 return (rman_release_resource(res)); 888} 889 890static int 891mv_pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 892{ 893 struct mv_pcib_softc *sc = device_get_softc(dev); 894 895 switch (which) { 896 case PCIB_IVAR_BUS: 897 *result = sc->sc_busnr; 898 return (0); 899 case PCIB_IVAR_DOMAIN: 900 *result = device_get_unit(dev); 901 return (0); 902 } 903 904 return (ENOENT); 905} 906 907static int 908mv_pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value) 909{ 910 struct mv_pcib_softc *sc = device_get_softc(dev); 911 912 switch (which) { 913 case PCIB_IVAR_BUS: 914 sc->sc_busnr = value; 915 return (0); 916 } 917 918 return (ENOENT); 919} 920 921static inline void 922pcib_write_irq_mask(struct mv_pcib_softc *sc, uint32_t mask) 923{ 924 925 if (sc->sc_type != MV_TYPE_PCI) 926 return; 927 928 bus_space_write_4(sc->sc_bst, sc->sc_bsh, PCIE_REG_IRQ_MASK, mask); 929} 930 931static void 932mv_pcib_hw_cfginit(void) 933{ 934 static int opened = 0; 935 936 if (opened) 937 return; 938 939 mtx_init(&pcicfg_mtx, "pcicfg", NULL, MTX_SPIN); 940 opened = 1; 941} 942 943static uint32_t 944mv_pcib_hw_cfgread(struct mv_pcib_softc *sc, u_int bus, u_int slot, 945 u_int func, u_int reg, int bytes) 946{ 947 uint32_t addr, data, ca, cd; 948 949 ca = (sc->sc_type != MV_TYPE_PCI) ? 950 PCIE_REG_CFG_ADDR : PCI_REG_CFG_ADDR; 951 cd = (sc->sc_type != MV_TYPE_PCI) ? 952 PCIE_REG_CFG_DATA : PCI_REG_CFG_DATA; 953 addr = PCI_CFG_ENA | PCI_CFG_BUS(bus) | PCI_CFG_DEV(slot) | 954 PCI_CFG_FUN(func) | PCI_CFG_PCIE_REG(reg); 955 956 mtx_lock_spin(&pcicfg_mtx); 957 bus_space_write_4(sc->sc_bst, sc->sc_bsh, ca, addr); 958 959 data = ~0; 960 switch (bytes) { 961 case 1: 962 data = bus_space_read_1(sc->sc_bst, sc->sc_bsh, 963 cd + (reg & 3)); 964 break; 965 case 2: 966 data = le16toh(bus_space_read_2(sc->sc_bst, sc->sc_bsh, 967 cd + (reg & 2))); 968 break; 969 case 4: 970 data = le32toh(bus_space_read_4(sc->sc_bst, sc->sc_bsh, 971 cd)); 972 break; 973 } 974 mtx_unlock_spin(&pcicfg_mtx); 975 return (data); 976} 977 978static void 979mv_pcib_hw_cfgwrite(struct mv_pcib_softc *sc, u_int bus, u_int slot, 980 u_int func, u_int reg, uint32_t data, int bytes) 981{ 982 uint32_t addr, ca, cd; 983 984 ca = (sc->sc_type != MV_TYPE_PCI) ? 985 PCIE_REG_CFG_ADDR : PCI_REG_CFG_ADDR; 986 cd = (sc->sc_type != MV_TYPE_PCI) ? 987 PCIE_REG_CFG_DATA : PCI_REG_CFG_DATA; 988 addr = PCI_CFG_ENA | PCI_CFG_BUS(bus) | PCI_CFG_DEV(slot) | 989 PCI_CFG_FUN(func) | PCI_CFG_PCIE_REG(reg); 990 991 mtx_lock_spin(&pcicfg_mtx); 992 bus_space_write_4(sc->sc_bst, sc->sc_bsh, ca, addr); 993 994 switch (bytes) { 995 case 1: 996 bus_space_write_1(sc->sc_bst, sc->sc_bsh, 997 cd + (reg & 3), data); 998 break; 999 case 2: 1000 bus_space_write_2(sc->sc_bst, sc->sc_bsh, 1001 cd + (reg & 2), htole16(data)); 1002 break; 1003 case 4: 1004 bus_space_write_4(sc->sc_bst, sc->sc_bsh, 1005 cd, htole32(data)); 1006 break; 1007 } 1008 mtx_unlock_spin(&pcicfg_mtx); 1009} 1010 1011static int 1012mv_pcib_maxslots(device_t dev) 1013{ 1014 struct mv_pcib_softc *sc = device_get_softc(dev); 1015 1016 return ((sc->sc_type != MV_TYPE_PCI) ? 1 : PCI_SLOTMAX); 1017} 1018 1019static int 1020mv_pcib_root_slot(device_t dev, u_int bus, u_int slot, u_int func) 1021{ 1022#if defined(SOC_MV_ARMADA38X) 1023 struct mv_pcib_softc *sc = device_get_softc(dev); 1024 uint32_t vendor, device; 1025 1026 vendor = mv_pcib_hw_cfgread(sc, bus, slot, func, PCIR_VENDOR, 1027 PCIR_VENDOR_LENGTH); 1028 device = mv_pcib_hw_cfgread(sc, bus, slot, func, PCIR_DEVICE, 1029 PCIR_DEVICE_LENGTH) & MV_DEV_FAMILY_MASK; 1030 1031 return (vendor == PCI_VENDORID_MRVL && device == MV_DEV_ARMADA38X); 1032#else 1033 /* On platforms other than Armada38x, root link is always at slot 0 */ 1034 return (slot == 0); 1035#endif 1036} 1037 1038static uint32_t 1039mv_pcib_read_config(device_t dev, u_int bus, u_int slot, u_int func, 1040 u_int reg, int bytes) 1041{ 1042 struct mv_pcib_softc *sc = device_get_softc(dev); 1043 1044 /* Return ~0 if link is inactive or trying to read from Root */ 1045 if ((bus_space_read_4(sc->sc_bst, sc->sc_bsh, PCIE_REG_STATUS) & 1046 PCIE_STATUS_LINK_DOWN) || mv_pcib_root_slot(dev, bus, slot, func)) 1047 return (~0U); 1048 1049 return (mv_pcib_hw_cfgread(sc, bus, slot, func, reg, bytes)); 1050} 1051 1052static void 1053mv_pcib_write_config(device_t dev, u_int bus, u_int slot, u_int func, 1054 u_int reg, uint32_t val, int bytes) 1055{ 1056 struct mv_pcib_softc *sc = device_get_softc(dev); 1057 1058 /* Return if link is inactive or trying to write to Root */ 1059 if ((bus_space_read_4(sc->sc_bst, sc->sc_bsh, PCIE_REG_STATUS) & 1060 PCIE_STATUS_LINK_DOWN) || mv_pcib_root_slot(dev, bus, slot, func)) 1061 return; 1062 1063 mv_pcib_hw_cfgwrite(sc, bus, slot, func, reg, val, bytes); 1064} 1065 1066static int 1067mv_pcib_route_interrupt(device_t bus, device_t dev, int pin) 1068{ 1069 struct mv_pcib_softc *sc; 1070 struct ofw_pci_register reg; 1071 uint32_t pintr, mintr[4]; 1072 int icells; 1073 phandle_t iparent; 1074 1075 sc = device_get_softc(bus); 1076 pintr = pin; 1077 1078 /* Fabricate imap information in case this isn't an OFW device */ 1079 bzero(®, sizeof(reg)); 1080 reg.phys_hi = (pci_get_bus(dev) << OFW_PCI_PHYS_HI_BUSSHIFT) | 1081 (pci_get_slot(dev) << OFW_PCI_PHYS_HI_DEVICESHIFT) | 1082 (pci_get_function(dev) << OFW_PCI_PHYS_HI_FUNCTIONSHIFT); 1083 1084 icells = ofw_bus_lookup_imap(ofw_bus_get_node(dev), &sc->sc_pci_iinfo, 1085 ®, sizeof(reg), &pintr, sizeof(pintr), mintr, sizeof(mintr), 1086 &iparent); 1087 if (icells > 0) 1088 return (ofw_bus_map_intr(dev, iparent, icells, mintr)); 1089 1090 /* Maybe it's a real interrupt, not an intpin */ 1091 if (pin > 4) 1092 return (pin); 1093 1094 device_printf(bus, "could not route pin %d for device %d.%d\n", 1095 pin, pci_get_slot(dev), pci_get_function(dev)); 1096 return (PCI_INVALID_IRQ); 1097} 1098 1099static int 1100mv_pcib_decode_win(phandle_t node, struct mv_pcib_softc *sc) 1101{ 1102 struct mv_pci_range io_space, mem_space; 1103 device_t dev; 1104 int error; 1105 1106 dev = sc->sc_dev; 1107 1108 if ((error = mv_pci_ranges(node, &io_space, &mem_space)) != 0) { 1109 device_printf(dev, "could not retrieve 'ranges' data\n"); 1110 return (error); 1111 } 1112 1113 /* Configure CPU decoding windows */ 1114 error = decode_win_cpu_set(sc->sc_win_target, 1115 sc->sc_io_win_attr, io_space.base_parent, io_space.len, ~0); 1116 if (error < 0) { 1117 device_printf(dev, "could not set up CPU decode " 1118 "window for PCI IO\n"); 1119 return (ENXIO); 1120 } 1121 error = decode_win_cpu_set(sc->sc_win_target, 1122 sc->sc_mem_win_attr, mem_space.base_parent, mem_space.len, 1123 mem_space.base_parent); 1124 if (error < 0) { 1125 device_printf(dev, "could not set up CPU decode " 1126 "windows for PCI MEM\n"); 1127 return (ENXIO); 1128 } 1129 1130 sc->sc_io_base = io_space.base_parent; 1131 sc->sc_io_size = io_space.len; 1132 1133 sc->sc_mem_base = mem_space.base_parent; 1134 sc->sc_mem_size = mem_space.len; 1135 1136 return (0); 1137} 1138 1139#if defined(SOC_MV_ARMADAXP) 1140static int 1141mv_pcib_map_msi(device_t dev, device_t child, int irq, uint64_t *addr, 1142 uint32_t *data) 1143{ 1144 struct mv_pcib_softc *sc; 1145 1146 sc = device_get_softc(dev); 1147 irq = irq - MSI_IRQ; 1148 1149 /* validate parameters */ 1150 if (isclr(&sc->sc_msi_bitmap, irq)) { 1151 device_printf(dev, "invalid MSI 0x%x\n", irq); 1152 return (EINVAL); 1153 } 1154 1155 mv_msi_data(irq, addr, data); 1156 1157 debugf("%s: irq: %d addr: %jx data: %x\n", 1158 __func__, irq, *addr, *data); 1159 1160 return (0); 1161} 1162 1163static int 1164mv_pcib_alloc_msi(device_t dev, device_t child, int count, 1165 int maxcount __unused, int *irqs) 1166{ 1167 struct mv_pcib_softc *sc; 1168 u_int start = 0, i; 1169 1170 if (powerof2(count) == 0 || count > MSI_IRQ_NUM) 1171 return (EINVAL); 1172 1173 sc = device_get_softc(dev); 1174 mtx_lock(&sc->sc_msi_mtx); 1175 1176 for (start = 0; (start + count) < MSI_IRQ_NUM; start++) { 1177 for (i = start; i < start + count; i++) { 1178 if (isset(&sc->sc_msi_bitmap, i)) 1179 break; 1180 } 1181 if (i == start + count) 1182 break; 1183 } 1184 1185 if ((start + count) == MSI_IRQ_NUM) { 1186 mtx_unlock(&sc->sc_msi_mtx); 1187 return (ENXIO); 1188 } 1189 1190 for (i = start; i < start + count; i++) { 1191 setbit(&sc->sc_msi_bitmap, i); 1192 *irqs++ = MSI_IRQ + i; 1193 } 1194 debugf("%s: start: %x count: %x\n", __func__, start, count); 1195 1196 mtx_unlock(&sc->sc_msi_mtx); 1197 return (0); 1198} 1199 1200static int 1201mv_pcib_release_msi(device_t dev, device_t child, int count, int *irqs) 1202{ 1203 struct mv_pcib_softc *sc; 1204 u_int i; 1205 1206 sc = device_get_softc(dev); 1207 mtx_lock(&sc->sc_msi_mtx); 1208 1209 for (i = 0; i < count; i++) 1210 clrbit(&sc->sc_msi_bitmap, irqs[i] - MSI_IRQ); 1211 1212 mtx_unlock(&sc->sc_msi_mtx); 1213 return (0); 1214} 1215#endif 1216 1217