mv_pci.c revision 259484
1/*- 2 * Copyright (c) 2008 MARVELL INTERNATIONAL LTD. 3 * Copyright (c) 2010 The FreeBSD Foundation 4 * Copyright (c) 2010-2012 Semihalf 5 * All rights reserved. 6 * 7 * Developed by Semihalf. 8 * 9 * Portions of this software were developed by Semihalf 10 * under sponsorship from the FreeBSD Foundation. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 3. Neither the name of MARVELL nor the names of contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 */ 36 37/* 38 * Marvell integrated PCI/PCI-Express controller driver. 39 */ 40 41#include <sys/cdefs.h> 42__FBSDID("$FreeBSD: head/sys/arm/mv/mv_pci.c 259484 2013-12-16 22:04:47Z nwhitehorn $"); 43 44#include <sys/param.h> 45#include <sys/systm.h> 46#include <sys/kernel.h> 47#include <sys/lock.h> 48#include <sys/malloc.h> 49#include <sys/module.h> 50#include <sys/mutex.h> 51#include <sys/queue.h> 52#include <sys/bus.h> 53#include <sys/rman.h> 54#include <sys/endian.h> 55 56#include <machine/intr.h> 57 58#include <vm/vm.h> 59#include <vm/pmap.h> 60 61#include <dev/fdt/fdt_common.h> 62#include <dev/ofw/ofw_bus.h> 63#include <dev/ofw/ofw_pci.h> 64#include <dev/ofw/ofw_bus_subr.h> 65#include <dev/pci/pcivar.h> 66#include <dev/pci/pcireg.h> 67#include <dev/pci/pcib_private.h> 68 69#include "ofw_bus_if.h" 70#include "pcib_if.h" 71 72#include <machine/resource.h> 73#include <machine/bus.h> 74 75#include <arm/mv/mvreg.h> 76#include <arm/mv/mvvar.h> 77#include <arm/mv/mvwin.h> 78 79#ifdef DEBUG 80#define debugf(fmt, args...) do { printf(fmt,##args); } while (0) 81#else 82#define debugf(fmt, args...) 83#endif 84 85#define PCI_CFG_ENA (1U << 31) 86#define PCI_CFG_BUS(bus) (((bus) & 0xff) << 16) 87#define PCI_CFG_DEV(dev) (((dev) & 0x1f) << 11) 88#define PCI_CFG_FUN(fun) (((fun) & 0x7) << 8) 89#define PCI_CFG_PCIE_REG(reg) ((reg) & 0xfc) 90 91#define PCI_REG_CFG_ADDR 0x0C78 92#define PCI_REG_CFG_DATA 0x0C7C 93 94#define PCIE_REG_CFG_ADDR 0x18F8 95#define PCIE_REG_CFG_DATA 0x18FC 96#define PCIE_REG_CONTROL 0x1A00 97#define PCIE_CTRL_LINK1X 0x00000001 98#define PCIE_REG_STATUS 0x1A04 99#define PCIE_REG_IRQ_MASK 0x1910 100 101#define PCIE_CONTROL_ROOT_CMPLX (1 << 1) 102#define PCIE_CONTROL_HOT_RESET (1 << 24) 103 104#define PCIE_LINK_TIMEOUT 1000000 105 106#define PCIE_STATUS_LINK_DOWN 1 107#define PCIE_STATUS_DEV_OFFS 16 108 109/* Minimum PCI Memory and I/O allocations taken from PCI spec (in bytes) */ 110#define PCI_MIN_IO_ALLOC 4 111#define PCI_MIN_MEM_ALLOC 16 112 113#define BITS_PER_UINT32 (NBBY * sizeof(uint32_t)) 114 115struct mv_pcib_softc { 116 device_t sc_dev; 117 118 struct rman sc_mem_rman; 119 bus_addr_t sc_mem_base; 120 bus_addr_t sc_mem_size; 121 uint32_t sc_mem_map[MV_PCI_MEM_SLICE_SIZE / 122 (PCI_MIN_MEM_ALLOC * BITS_PER_UINT32)]; 123 int sc_win_target; 124 int sc_mem_win_attr; 125 126 struct rman sc_io_rman; 127 bus_addr_t sc_io_base; 128 bus_addr_t sc_io_size; 129 uint32_t sc_io_map[MV_PCI_IO_SLICE_SIZE / 130 (PCI_MIN_IO_ALLOC * BITS_PER_UINT32)]; 131 int sc_io_win_attr; 132 133 struct resource *sc_res; 134 bus_space_handle_t sc_bsh; 135 bus_space_tag_t sc_bst; 136 int sc_rid; 137 138 struct mtx sc_msi_mtx; 139 uint32_t sc_msi_bitmap; 140 141 int sc_busnr; /* Host bridge bus number */ 142 int sc_devnr; /* Host bridge device number */ 143 int sc_type; 144 int sc_mode; /* Endpoint / Root Complex */ 145 146 struct ofw_bus_iinfo sc_pci_iinfo; 147}; 148 149/* Local forward prototypes */ 150static int mv_pcib_decode_win(phandle_t, struct mv_pcib_softc *); 151static void mv_pcib_hw_cfginit(void); 152static uint32_t mv_pcib_hw_cfgread(struct mv_pcib_softc *, u_int, u_int, 153 u_int, u_int, int); 154static void mv_pcib_hw_cfgwrite(struct mv_pcib_softc *, u_int, u_int, 155 u_int, u_int, uint32_t, int); 156static int mv_pcib_init(struct mv_pcib_softc *, int, int); 157static int mv_pcib_init_all_bars(struct mv_pcib_softc *, int, int, int, int); 158static void mv_pcib_init_bridge(struct mv_pcib_softc *, int, int, int); 159static inline void pcib_write_irq_mask(struct mv_pcib_softc *, uint32_t); 160static void mv_pcib_enable(struct mv_pcib_softc *, uint32_t); 161static int mv_pcib_mem_init(struct mv_pcib_softc *); 162 163/* Forward prototypes */ 164static int mv_pcib_probe(device_t); 165static int mv_pcib_attach(device_t); 166 167static struct resource *mv_pcib_alloc_resource(device_t, device_t, int, int *, 168 u_long, u_long, u_long, u_int); 169static int mv_pcib_release_resource(device_t, device_t, int, int, 170 struct resource *); 171static int mv_pcib_read_ivar(device_t, device_t, int, uintptr_t *); 172static int mv_pcib_write_ivar(device_t, device_t, int, uintptr_t); 173 174static int mv_pcib_maxslots(device_t); 175static uint32_t mv_pcib_read_config(device_t, u_int, u_int, u_int, u_int, int); 176static void mv_pcib_write_config(device_t, u_int, u_int, u_int, u_int, 177 uint32_t, int); 178static int mv_pcib_route_interrupt(device_t, device_t, int); 179#if defined(SOC_MV_ARMADAXP) 180static int mv_pcib_alloc_msi(device_t, device_t, int, int, int *); 181static int mv_pcib_map_msi(device_t, device_t, int, uint64_t *, uint32_t *); 182static int mv_pcib_release_msi(device_t, device_t, int, int *); 183#endif 184 185/* 186 * Bus interface definitions. 187 */ 188static device_method_t mv_pcib_methods[] = { 189 /* Device interface */ 190 DEVMETHOD(device_probe, mv_pcib_probe), 191 DEVMETHOD(device_attach, mv_pcib_attach), 192 193 /* Bus interface */ 194 DEVMETHOD(bus_read_ivar, mv_pcib_read_ivar), 195 DEVMETHOD(bus_write_ivar, mv_pcib_write_ivar), 196 DEVMETHOD(bus_alloc_resource, mv_pcib_alloc_resource), 197 DEVMETHOD(bus_release_resource, mv_pcib_release_resource), 198 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 199 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 200 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 201 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 202 203 /* pcib interface */ 204 DEVMETHOD(pcib_maxslots, mv_pcib_maxslots), 205 DEVMETHOD(pcib_read_config, mv_pcib_read_config), 206 DEVMETHOD(pcib_write_config, mv_pcib_write_config), 207 DEVMETHOD(pcib_route_interrupt, mv_pcib_route_interrupt), 208 209#if defined(SOC_MV_ARMADAXP) 210 DEVMETHOD(pcib_alloc_msi, mv_pcib_alloc_msi), 211 DEVMETHOD(pcib_release_msi, mv_pcib_release_msi), 212 DEVMETHOD(pcib_map_msi, mv_pcib_map_msi), 213#endif 214 215 /* OFW bus interface */ 216 DEVMETHOD(ofw_bus_get_compat, ofw_bus_gen_get_compat), 217 DEVMETHOD(ofw_bus_get_model, ofw_bus_gen_get_model), 218 DEVMETHOD(ofw_bus_get_name, ofw_bus_gen_get_name), 219 DEVMETHOD(ofw_bus_get_node, ofw_bus_gen_get_node), 220 DEVMETHOD(ofw_bus_get_type, ofw_bus_gen_get_type), 221 222 DEVMETHOD_END 223}; 224 225static driver_t mv_pcib_driver = { 226 "pcib", 227 mv_pcib_methods, 228 sizeof(struct mv_pcib_softc), 229}; 230 231devclass_t pcib_devclass; 232 233DRIVER_MODULE(pcib, nexus, mv_pcib_driver, pcib_devclass, 0, 0); 234 235static struct mtx pcicfg_mtx; 236 237static int 238mv_pcib_probe(device_t self) 239{ 240 phandle_t node; 241 242 node = ofw_bus_get_node(self); 243 if (!fdt_is_type(node, "pci")) 244 return (ENXIO); 245 246 if (!(ofw_bus_is_compatible(self, "mrvl,pcie") || 247 ofw_bus_is_compatible(self, "mrvl,pci"))) 248 return (ENXIO); 249 250 device_set_desc(self, "Marvell Integrated PCI/PCI-E Controller"); 251 return (BUS_PROBE_DEFAULT); 252} 253 254static int 255mv_pcib_attach(device_t self) 256{ 257 struct mv_pcib_softc *sc; 258 phandle_t node, parnode; 259 uint32_t val, unit; 260 int err; 261 262 sc = device_get_softc(self); 263 sc->sc_dev = self; 264 unit = fdt_get_unit(self); 265 266 267 node = ofw_bus_get_node(self); 268 parnode = OF_parent(node); 269 if (fdt_is_compatible(node, "mrvl,pcie")) { 270 sc->sc_type = MV_TYPE_PCIE; 271 sc->sc_win_target = MV_WIN_PCIE_TARGET(unit); 272 sc->sc_mem_win_attr = MV_WIN_PCIE_MEM_ATTR(unit); 273 sc->sc_io_win_attr = MV_WIN_PCIE_IO_ATTR(unit); 274 } else if (fdt_is_compatible(node, "mrvl,pci")) { 275 sc->sc_type = MV_TYPE_PCI; 276 sc->sc_win_target = MV_WIN_PCI_TARGET; 277 sc->sc_mem_win_attr = MV_WIN_PCI_MEM_ATTR; 278 sc->sc_io_win_attr = MV_WIN_PCI_IO_ATTR; 279 } else 280 return (ENXIO); 281 282 /* 283 * Retrieve our mem-mapped registers range. 284 */ 285 sc->sc_rid = 0; 286 sc->sc_res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &sc->sc_rid, 287 RF_ACTIVE); 288 if (sc->sc_res == NULL) { 289 device_printf(self, "could not map memory\n"); 290 return (ENXIO); 291 } 292 sc->sc_bst = rman_get_bustag(sc->sc_res); 293 sc->sc_bsh = rman_get_bushandle(sc->sc_res); 294 295 val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, PCIE_REG_CONTROL); 296 sc->sc_mode = (val & PCIE_CONTROL_ROOT_CMPLX ? MV_MODE_ROOT : 297 MV_MODE_ENDPOINT); 298 299 /* 300 * Get PCI interrupt info. 301 */ 302 if (sc->sc_mode == MV_MODE_ROOT) 303 ofw_bus_setup_iinfo(node, &sc->sc_pci_iinfo, sizeof(pcell_t)); 304 305 /* 306 * Configure decode windows for PCI(E) access. 307 */ 308 if (mv_pcib_decode_win(node, sc) != 0) 309 return (ENXIO); 310 311 mv_pcib_hw_cfginit(); 312 313 /* 314 * Enable PCIE device. 315 */ 316 mv_pcib_enable(sc, unit); 317 318 /* 319 * Memory management. 320 */ 321 err = mv_pcib_mem_init(sc); 322 if (err) 323 return (err); 324 325 if (sc->sc_mode == MV_MODE_ROOT) { 326 err = mv_pcib_init(sc, sc->sc_busnr, 327 mv_pcib_maxslots(sc->sc_dev)); 328 if (err) 329 goto error; 330 331 device_add_child(self, "pci", -1); 332 } else { 333 sc->sc_devnr = 1; 334 bus_space_write_4(sc->sc_bst, sc->sc_bsh, 335 PCIE_REG_STATUS, 1 << PCIE_STATUS_DEV_OFFS); 336 device_add_child(self, "pci_ep", -1); 337 } 338 339 mtx_init(&sc->sc_msi_mtx, "msi_mtx", NULL, MTX_DEF); 340 return (bus_generic_attach(self)); 341 342error: 343 /* XXX SYS_RES_ should be released here */ 344 rman_fini(&sc->sc_mem_rman); 345 rman_fini(&sc->sc_io_rman); 346 347 return (err); 348} 349 350static void 351mv_pcib_enable(struct mv_pcib_softc *sc, uint32_t unit) 352{ 353 uint32_t val; 354#if !defined(SOC_MV_ARMADAXP) 355 int timeout; 356 357 /* 358 * Check if PCIE device is enabled. 359 */ 360 if (read_cpu_ctrl(CPU_CONTROL) & CPU_CONTROL_PCIE_DISABLE(unit)) { 361 write_cpu_ctrl(CPU_CONTROL, read_cpu_ctrl(CPU_CONTROL) & 362 ~(CPU_CONTROL_PCIE_DISABLE(unit))); 363 364 timeout = PCIE_LINK_TIMEOUT; 365 val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, 366 PCIE_REG_STATUS); 367 while (((val & PCIE_STATUS_LINK_DOWN) == 1) && (timeout > 0)) { 368 DELAY(1000); 369 timeout -= 1000; 370 val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, 371 PCIE_REG_STATUS); 372 } 373 } 374#endif 375 376 377 if (sc->sc_mode == MV_MODE_ROOT) { 378 /* 379 * Enable PCI bridge. 380 */ 381 val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, PCIR_COMMAND); 382 val |= PCIM_CMD_SERRESPEN | PCIM_CMD_BUSMASTEREN | 383 PCIM_CMD_MEMEN | PCIM_CMD_PORTEN; 384 bus_space_write_4(sc->sc_bst, sc->sc_bsh, PCIR_COMMAND, val); 385 } 386} 387 388static int 389mv_pcib_mem_init(struct mv_pcib_softc *sc) 390{ 391 int err; 392 393 /* 394 * Memory management. 395 */ 396 sc->sc_mem_rman.rm_type = RMAN_ARRAY; 397 err = rman_init(&sc->sc_mem_rman); 398 if (err) 399 return (err); 400 401 sc->sc_io_rman.rm_type = RMAN_ARRAY; 402 err = rman_init(&sc->sc_io_rman); 403 if (err) { 404 rman_fini(&sc->sc_mem_rman); 405 return (err); 406 } 407 408 err = rman_manage_region(&sc->sc_mem_rman, sc->sc_mem_base, 409 sc->sc_mem_base + sc->sc_mem_size - 1); 410 if (err) 411 goto error; 412 413 err = rman_manage_region(&sc->sc_io_rman, sc->sc_io_base, 414 sc->sc_io_base + sc->sc_io_size - 1); 415 if (err) 416 goto error; 417 418 return (0); 419 420error: 421 rman_fini(&sc->sc_mem_rman); 422 rman_fini(&sc->sc_io_rman); 423 424 return (err); 425} 426 427static inline uint32_t 428pcib_bit_get(uint32_t *map, uint32_t bit) 429{ 430 uint32_t n = bit / BITS_PER_UINT32; 431 432 bit = bit % BITS_PER_UINT32; 433 return (map[n] & (1 << bit)); 434} 435 436static inline void 437pcib_bit_set(uint32_t *map, uint32_t bit) 438{ 439 uint32_t n = bit / BITS_PER_UINT32; 440 441 bit = bit % BITS_PER_UINT32; 442 map[n] |= (1 << bit); 443} 444 445static inline uint32_t 446pcib_map_check(uint32_t *map, uint32_t start, uint32_t bits) 447{ 448 uint32_t i; 449 450 for (i = start; i < start + bits; i++) 451 if (pcib_bit_get(map, i)) 452 return (0); 453 454 return (1); 455} 456 457static inline void 458pcib_map_set(uint32_t *map, uint32_t start, uint32_t bits) 459{ 460 uint32_t i; 461 462 for (i = start; i < start + bits; i++) 463 pcib_bit_set(map, i); 464} 465 466/* 467 * The idea of this allocator is taken from ARM No-Cache memory 468 * management code (sys/arm/arm/vm_machdep.c). 469 */ 470static bus_addr_t 471pcib_alloc(struct mv_pcib_softc *sc, uint32_t smask) 472{ 473 uint32_t bits, bits_limit, i, *map, min_alloc, size; 474 bus_addr_t addr = 0; 475 bus_addr_t base; 476 477 if (smask & 1) { 478 base = sc->sc_io_base; 479 min_alloc = PCI_MIN_IO_ALLOC; 480 bits_limit = sc->sc_io_size / min_alloc; 481 map = sc->sc_io_map; 482 smask &= ~0x3; 483 } else { 484 base = sc->sc_mem_base; 485 min_alloc = PCI_MIN_MEM_ALLOC; 486 bits_limit = sc->sc_mem_size / min_alloc; 487 map = sc->sc_mem_map; 488 smask &= ~0xF; 489 } 490 491 size = ~smask + 1; 492 bits = size / min_alloc; 493 494 for (i = 0; i + bits <= bits_limit; i += bits) 495 if (pcib_map_check(map, i, bits)) { 496 pcib_map_set(map, i, bits); 497 addr = base + (i * min_alloc); 498 return (addr); 499 } 500 501 return (addr); 502} 503 504static int 505mv_pcib_init_bar(struct mv_pcib_softc *sc, int bus, int slot, int func, 506 int barno) 507{ 508 uint32_t addr, bar; 509 int reg, width; 510 511 reg = PCIR_BAR(barno); 512 513 /* 514 * Need to init the BAR register with 0xffffffff before correct 515 * value can be read. 516 */ 517 mv_pcib_write_config(sc->sc_dev, bus, slot, func, reg, ~0, 4); 518 bar = mv_pcib_read_config(sc->sc_dev, bus, slot, func, reg, 4); 519 if (bar == 0) 520 return (1); 521 522 /* Calculate BAR size: 64 or 32 bit (in 32-bit units) */ 523 width = ((bar & 7) == 4) ? 2 : 1; 524 525 addr = pcib_alloc(sc, bar); 526 if (!addr) 527 return (-1); 528 529 if (bootverbose) 530 printf("PCI %u:%u:%u: reg %x: smask=%08x: addr=%08x\n", 531 bus, slot, func, reg, bar, addr); 532 533 mv_pcib_write_config(sc->sc_dev, bus, slot, func, reg, addr, 4); 534 if (width == 2) 535 mv_pcib_write_config(sc->sc_dev, bus, slot, func, reg + 4, 536 0, 4); 537 538 return (width); 539} 540 541static void 542mv_pcib_init_bridge(struct mv_pcib_softc *sc, int bus, int slot, int func) 543{ 544 bus_addr_t io_base, mem_base; 545 uint32_t io_limit, mem_limit; 546 int secbus; 547 548 io_base = sc->sc_io_base; 549 io_limit = io_base + sc->sc_io_size - 1; 550 mem_base = sc->sc_mem_base; 551 mem_limit = mem_base + sc->sc_mem_size - 1; 552 553 /* Configure I/O decode registers */ 554 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_IOBASEL_1, 555 io_base >> 8, 1); 556 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_IOBASEH_1, 557 io_base >> 16, 2); 558 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_IOLIMITL_1, 559 io_limit >> 8, 1); 560 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_IOLIMITH_1, 561 io_limit >> 16, 2); 562 563 /* Configure memory decode registers */ 564 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_MEMBASE_1, 565 mem_base >> 16, 2); 566 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_MEMLIMIT_1, 567 mem_limit >> 16, 2); 568 569 /* Disable memory prefetch decode */ 570 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_PMBASEL_1, 571 0x10, 2); 572 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_PMBASEH_1, 573 0x0, 4); 574 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_PMLIMITL_1, 575 0xF, 2); 576 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_PMLIMITH_1, 577 0x0, 4); 578 579 secbus = mv_pcib_read_config(sc->sc_dev, bus, slot, func, 580 PCIR_SECBUS_1, 1); 581 582 /* Configure buses behind the bridge */ 583 mv_pcib_init(sc, secbus, PCI_SLOTMAX); 584} 585 586static int 587mv_pcib_init(struct mv_pcib_softc *sc, int bus, int maxslot) 588{ 589 int slot, func, maxfunc, error; 590 uint8_t hdrtype, command, class, subclass; 591 592 for (slot = 0; slot <= maxslot; slot++) { 593 maxfunc = 0; 594 for (func = 0; func <= maxfunc; func++) { 595 hdrtype = mv_pcib_read_config(sc->sc_dev, bus, slot, 596 func, PCIR_HDRTYPE, 1); 597 598 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE) 599 continue; 600 601 if (func == 0 && (hdrtype & PCIM_MFDEV)) 602 maxfunc = PCI_FUNCMAX; 603 604 command = mv_pcib_read_config(sc->sc_dev, bus, slot, 605 func, PCIR_COMMAND, 1); 606 command &= ~(PCIM_CMD_MEMEN | PCIM_CMD_PORTEN); 607 mv_pcib_write_config(sc->sc_dev, bus, slot, func, 608 PCIR_COMMAND, command, 1); 609 610 error = mv_pcib_init_all_bars(sc, bus, slot, func, 611 hdrtype); 612 613 if (error) 614 return (error); 615 616 command |= PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN | 617 PCIM_CMD_PORTEN; 618 mv_pcib_write_config(sc->sc_dev, bus, slot, func, 619 PCIR_COMMAND, command, 1); 620 621 /* Handle PCI-PCI bridges */ 622 class = mv_pcib_read_config(sc->sc_dev, bus, slot, 623 func, PCIR_CLASS, 1); 624 subclass = mv_pcib_read_config(sc->sc_dev, bus, slot, 625 func, PCIR_SUBCLASS, 1); 626 627 if (class != PCIC_BRIDGE || 628 subclass != PCIS_BRIDGE_PCI) 629 continue; 630 631 mv_pcib_init_bridge(sc, bus, slot, func); 632 } 633 } 634 635 /* Enable all ABCD interrupts */ 636 pcib_write_irq_mask(sc, (0xF << 24)); 637 638 return (0); 639} 640 641static int 642mv_pcib_init_all_bars(struct mv_pcib_softc *sc, int bus, int slot, 643 int func, int hdrtype) 644{ 645 int maxbar, bar, i; 646 647 maxbar = (hdrtype & PCIM_HDRTYPE) ? 0 : 6; 648 bar = 0; 649 650 /* Program the base address registers */ 651 while (bar < maxbar) { 652 i = mv_pcib_init_bar(sc, bus, slot, func, bar); 653 bar += i; 654 if (i < 0) { 655 device_printf(sc->sc_dev, 656 "PCI IO/Memory space exhausted\n"); 657 return (ENOMEM); 658 } 659 } 660 661 return (0); 662} 663 664static struct resource * 665mv_pcib_alloc_resource(device_t dev, device_t child, int type, int *rid, 666 u_long start, u_long end, u_long count, u_int flags) 667{ 668 struct mv_pcib_softc *sc = device_get_softc(dev); 669 struct rman *rm = NULL; 670 struct resource *res; 671 672 switch (type) { 673 case SYS_RES_IOPORT: 674 rm = &sc->sc_io_rman; 675 break; 676 case SYS_RES_MEMORY: 677 rm = &sc->sc_mem_rman; 678 break; 679 default: 680 return (BUS_ALLOC_RESOURCE(device_get_parent(dev), dev, 681 type, rid, start, end, count, flags)); 682 }; 683 684 if ((start == 0UL) && (end == ~0UL)) { 685 start = sc->sc_mem_base; 686 end = sc->sc_mem_base + sc->sc_mem_size - 1; 687 count = sc->sc_mem_size; 688 } 689 690 if ((start < sc->sc_mem_base) || (start + count - 1 != end) || 691 (end > sc->sc_mem_base + sc->sc_mem_size - 1)) 692 return (NULL); 693 694 res = rman_reserve_resource(rm, start, end, count, flags, child); 695 if (res == NULL) 696 return (NULL); 697 698 rman_set_rid(res, *rid); 699 rman_set_bustag(res, fdtbus_bs_tag); 700 rman_set_bushandle(res, start); 701 702 if (flags & RF_ACTIVE) 703 if (bus_activate_resource(child, type, *rid, res)) { 704 rman_release_resource(res); 705 return (NULL); 706 } 707 708 return (res); 709} 710 711static int 712mv_pcib_release_resource(device_t dev, device_t child, int type, int rid, 713 struct resource *res) 714{ 715 716 if (type != SYS_RES_IOPORT && type != SYS_RES_MEMORY) 717 return (BUS_RELEASE_RESOURCE(device_get_parent(dev), child, 718 type, rid, res)); 719 720 return (rman_release_resource(res)); 721} 722 723static int 724mv_pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 725{ 726 struct mv_pcib_softc *sc = device_get_softc(dev); 727 728 switch (which) { 729 case PCIB_IVAR_BUS: 730 *result = sc->sc_busnr; 731 return (0); 732 case PCIB_IVAR_DOMAIN: 733 *result = device_get_unit(dev); 734 return (0); 735 } 736 737 return (ENOENT); 738} 739 740static int 741mv_pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value) 742{ 743 struct mv_pcib_softc *sc = device_get_softc(dev); 744 745 switch (which) { 746 case PCIB_IVAR_BUS: 747 sc->sc_busnr = value; 748 return (0); 749 } 750 751 return (ENOENT); 752} 753 754static inline void 755pcib_write_irq_mask(struct mv_pcib_softc *sc, uint32_t mask) 756{ 757 758 if (!sc->sc_type != MV_TYPE_PCI) 759 return; 760 761 bus_space_write_4(sc->sc_bst, sc->sc_bsh, PCIE_REG_IRQ_MASK, mask); 762} 763 764static void 765mv_pcib_hw_cfginit(void) 766{ 767 static int opened = 0; 768 769 if (opened) 770 return; 771 772 mtx_init(&pcicfg_mtx, "pcicfg", NULL, MTX_SPIN); 773 opened = 1; 774} 775 776static uint32_t 777mv_pcib_hw_cfgread(struct mv_pcib_softc *sc, u_int bus, u_int slot, 778 u_int func, u_int reg, int bytes) 779{ 780 uint32_t addr, data, ca, cd; 781 782 ca = (sc->sc_type != MV_TYPE_PCI) ? 783 PCIE_REG_CFG_ADDR : PCI_REG_CFG_ADDR; 784 cd = (sc->sc_type != MV_TYPE_PCI) ? 785 PCIE_REG_CFG_DATA : PCI_REG_CFG_DATA; 786 addr = PCI_CFG_ENA | PCI_CFG_BUS(bus) | PCI_CFG_DEV(slot) | 787 PCI_CFG_FUN(func) | PCI_CFG_PCIE_REG(reg); 788 789 mtx_lock_spin(&pcicfg_mtx); 790 bus_space_write_4(sc->sc_bst, sc->sc_bsh, ca, addr); 791 792 data = ~0; 793 switch (bytes) { 794 case 1: 795 data = bus_space_read_1(sc->sc_bst, sc->sc_bsh, 796 cd + (reg & 3)); 797 break; 798 case 2: 799 data = le16toh(bus_space_read_2(sc->sc_bst, sc->sc_bsh, 800 cd + (reg & 2))); 801 break; 802 case 4: 803 data = le32toh(bus_space_read_4(sc->sc_bst, sc->sc_bsh, 804 cd)); 805 break; 806 } 807 mtx_unlock_spin(&pcicfg_mtx); 808 return (data); 809} 810 811static void 812mv_pcib_hw_cfgwrite(struct mv_pcib_softc *sc, u_int bus, u_int slot, 813 u_int func, u_int reg, uint32_t data, int bytes) 814{ 815 uint32_t addr, ca, cd; 816 817 ca = (sc->sc_type != MV_TYPE_PCI) ? 818 PCIE_REG_CFG_ADDR : PCI_REG_CFG_ADDR; 819 cd = (sc->sc_type != MV_TYPE_PCI) ? 820 PCIE_REG_CFG_DATA : PCI_REG_CFG_DATA; 821 addr = PCI_CFG_ENA | PCI_CFG_BUS(bus) | PCI_CFG_DEV(slot) | 822 PCI_CFG_FUN(func) | PCI_CFG_PCIE_REG(reg); 823 824 mtx_lock_spin(&pcicfg_mtx); 825 bus_space_write_4(sc->sc_bst, sc->sc_bsh, ca, addr); 826 827 switch (bytes) { 828 case 1: 829 bus_space_write_1(sc->sc_bst, sc->sc_bsh, 830 cd + (reg & 3), data); 831 break; 832 case 2: 833 bus_space_write_2(sc->sc_bst, sc->sc_bsh, 834 cd + (reg & 2), htole16(data)); 835 break; 836 case 4: 837 bus_space_write_4(sc->sc_bst, sc->sc_bsh, 838 cd, htole32(data)); 839 break; 840 } 841 mtx_unlock_spin(&pcicfg_mtx); 842} 843 844static int 845mv_pcib_maxslots(device_t dev) 846{ 847 struct mv_pcib_softc *sc = device_get_softc(dev); 848 849 return ((sc->sc_type != MV_TYPE_PCI) ? 1 : PCI_SLOTMAX); 850} 851 852static uint32_t 853mv_pcib_read_config(device_t dev, u_int bus, u_int slot, u_int func, 854 u_int reg, int bytes) 855{ 856 struct mv_pcib_softc *sc = device_get_softc(dev); 857 858 /* Return ~0 if link is inactive or trying to read from Root */ 859 if ((bus_space_read_4(sc->sc_bst, sc->sc_bsh, PCIE_REG_STATUS) & 860 PCIE_STATUS_LINK_DOWN) || (slot == 0)) 861 return (~0U); 862 863 return (mv_pcib_hw_cfgread(sc, bus, slot, func, reg, bytes)); 864} 865 866static void 867mv_pcib_write_config(device_t dev, u_int bus, u_int slot, u_int func, 868 u_int reg, uint32_t val, int bytes) 869{ 870 struct mv_pcib_softc *sc = device_get_softc(dev); 871 872 /* Return if link is inactive or trying to write to Root */ 873 if ((bus_space_read_4(sc->sc_bst, sc->sc_bsh, PCIE_REG_STATUS) & 874 PCIE_STATUS_LINK_DOWN) || (slot == 0)) 875 return; 876 877 mv_pcib_hw_cfgwrite(sc, bus, slot, func, reg, val, bytes); 878} 879 880static int 881mv_pcib_route_interrupt(device_t bus, device_t dev, int pin) 882{ 883 struct mv_pcib_softc *sc; 884 struct ofw_pci_register reg; 885 uint32_t pintr, mintr; 886 phandle_t iparent; 887 uint8_t maskbuf[sizeof(reg) + sizeof(pintr)]; 888 889 sc = device_get_softc(bus); 890 pintr = pin; 891 892 /* Fabricate imap information in case this isn't an OFW device */ 893 bzero(®, sizeof(reg)); 894 reg.phys_hi = (pci_get_bus(dev) << OFW_PCI_PHYS_HI_BUSSHIFT) | 895 (pci_get_slot(dev) << OFW_PCI_PHYS_HI_DEVICESHIFT) | 896 (pci_get_function(dev) << OFW_PCI_PHYS_HI_FUNCTIONSHIFT); 897 898 if (ofw_bus_lookup_imap(ofw_bus_get_node(dev), &sc->sc_pci_iinfo, ®, 899 sizeof(reg), &pintr, sizeof(pintr), &mintr, sizeof(mintr), 900 &iparent, maskbuf)) 901 return (ofw_bus_map_intr(dev, iparent, mintr)); 902 903 /* Maybe it's a real interrupt, not an intpin */ 904 if (pin > 4) 905 return (pin); 906 907 device_printf(bus, "could not route pin %d for device %d.%d\n", 908 pin, pci_get_slot(dev), pci_get_function(dev)); 909 return (PCI_INVALID_IRQ); 910} 911 912static int 913mv_pcib_decode_win(phandle_t node, struct mv_pcib_softc *sc) 914{ 915 struct fdt_pci_range io_space, mem_space; 916 device_t dev; 917 int error; 918 919 dev = sc->sc_dev; 920 921 if ((error = fdt_pci_ranges(node, &io_space, &mem_space)) != 0) { 922 device_printf(dev, "could not retrieve 'ranges' data\n"); 923 return (error); 924 } 925 926 /* Configure CPU decoding windows */ 927 error = decode_win_cpu_set(sc->sc_win_target, 928 sc->sc_io_win_attr, io_space.base_parent, io_space.len, ~0); 929 if (error < 0) { 930 device_printf(dev, "could not set up CPU decode " 931 "window for PCI IO\n"); 932 return (ENXIO); 933 } 934 error = decode_win_cpu_set(sc->sc_win_target, 935 sc->sc_mem_win_attr, mem_space.base_parent, mem_space.len, 936 mem_space.base_parent); 937 if (error < 0) { 938 device_printf(dev, "could not set up CPU decode " 939 "windows for PCI MEM\n"); 940 return (ENXIO); 941 } 942 943 sc->sc_io_base = io_space.base_parent; 944 sc->sc_io_size = io_space.len; 945 946 sc->sc_mem_base = mem_space.base_parent; 947 sc->sc_mem_size = mem_space.len; 948 949 return (0); 950} 951 952#if defined(SOC_MV_ARMADAXP) 953static int 954mv_pcib_map_msi(device_t dev, device_t child, int irq, uint64_t *addr, 955 uint32_t *data) 956{ 957 struct mv_pcib_softc *sc; 958 959 sc = device_get_softc(dev); 960 irq = irq - MSI_IRQ; 961 962 /* validate parameters */ 963 if (isclr(&sc->sc_msi_bitmap, irq)) { 964 device_printf(dev, "invalid MSI 0x%x\n", irq); 965 return (EINVAL); 966 } 967 968 mv_msi_data(irq, addr, data); 969 970 debugf("%s: irq: %d addr: %jx data: %x\n", 971 __func__, irq, *addr, *data); 972 973 return (0); 974} 975 976static int 977mv_pcib_alloc_msi(device_t dev, device_t child, int count, 978 int maxcount __unused, int *irqs) 979{ 980 struct mv_pcib_softc *sc; 981 u_int start = 0, i; 982 983 if (powerof2(count) == 0 || count > MSI_IRQ_NUM) 984 return (EINVAL); 985 986 sc = device_get_softc(dev); 987 mtx_lock(&sc->sc_msi_mtx); 988 989 for (start = 0; (start + count) < MSI_IRQ_NUM; start++) { 990 for (i = start; i < start + count; i++) { 991 if (isset(&sc->sc_msi_bitmap, i)) 992 break; 993 } 994 if (i == start + count) 995 break; 996 } 997 998 if ((start + count) == MSI_IRQ_NUM) { 999 mtx_unlock(&sc->sc_msi_mtx); 1000 return (ENXIO); 1001 } 1002 1003 for (i = start; i < start + count; i++) { 1004 setbit(&sc->sc_msi_bitmap, i); 1005 irqs[i] = MSI_IRQ + i; 1006 } 1007 debugf("%s: start: %x count: %x\n", __func__, start, count); 1008 1009 mtx_unlock(&sc->sc_msi_mtx); 1010 return (0); 1011} 1012 1013static int 1014mv_pcib_release_msi(device_t dev, device_t child, int count, int *irqs) 1015{ 1016 struct mv_pcib_softc *sc; 1017 u_int i; 1018 1019 sc = device_get_softc(dev); 1020 mtx_lock(&sc->sc_msi_mtx); 1021 1022 for (i = 0; i < count; i++) 1023 clrbit(&sc->sc_msi_bitmap, irqs[i] - MSI_IRQ); 1024 1025 mtx_unlock(&sc->sc_msi_mtx); 1026 return (0); 1027} 1028#endif 1029