1185089Sraj/*- 2209131Sraj * Copyright (c) 2008 MARVELL INTERNATIONAL LTD. 3209131Sraj * Copyright (c) 2010 The FreeBSD Foundation 4294430Szbb * Copyright (c) 2010-2015 Semihalf 5185089Sraj * All rights reserved. 6185089Sraj * 7185089Sraj * Developed by Semihalf. 8185089Sraj * 9209131Sraj * Portions of this software were developed by Semihalf 10209131Sraj * under sponsorship from the FreeBSD Foundation. 11209131Sraj * 12185089Sraj * Redistribution and use in source and binary forms, with or without 13185089Sraj * modification, are permitted provided that the following conditions 14185089Sraj * are met: 15185089Sraj * 1. Redistributions of source code must retain the above copyright 16185089Sraj * notice, this list of conditions and the following disclaimer. 17185089Sraj * 2. Redistributions in binary form must reproduce the above copyright 18185089Sraj * notice, this list of conditions and the following disclaimer in the 19185089Sraj * documentation and/or other materials provided with the distribution. 20185089Sraj * 3. Neither the name of MARVELL nor the names of contributors 21185089Sraj * may be used to endorse or promote products derived from this software 22185089Sraj * without specific prior written permission. 23185089Sraj * 24185089Sraj * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 25185089Sraj * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26185089Sraj * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27185089Sraj * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 28185089Sraj * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29185089Sraj * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30185089Sraj * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31185089Sraj * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32185089Sraj * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33185089Sraj * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34185089Sraj * SUCH DAMAGE. 35185089Sraj */ 36185089Sraj 37185089Sraj/* 38185089Sraj * Marvell integrated PCI/PCI-Express controller driver. 39185089Sraj */ 40185089Sraj 41185089Sraj#include <sys/cdefs.h> 42185089Sraj__FBSDID("$FreeBSD$"); 43185089Sraj 44185089Sraj#include <sys/param.h> 45185089Sraj#include <sys/systm.h> 46185089Sraj#include <sys/kernel.h> 47185089Sraj#include <sys/lock.h> 48185089Sraj#include <sys/malloc.h> 49185089Sraj#include <sys/module.h> 50185089Sraj#include <sys/mutex.h> 51185089Sraj#include <sys/queue.h> 52185089Sraj#include <sys/bus.h> 53185089Sraj#include <sys/rman.h> 54185089Sraj#include <sys/endian.h> 55298627Sbr#include <sys/devmap.h> 56185089Sraj 57260327Snwhitehorn#include <machine/fdt.h> 58240493Sgber#include <machine/intr.h> 59240493Sgber 60185089Sraj#include <vm/vm.h> 61185089Sraj#include <vm/pmap.h> 62185089Sraj 63209131Sraj#include <dev/fdt/fdt_common.h> 64209131Sraj#include <dev/ofw/ofw_bus.h> 65295807Sandrew#include <dev/ofw/ofw_bus_subr.h> 66259484Snwhitehorn#include <dev/ofw/ofw_pci.h> 67185089Sraj#include <dev/pci/pcivar.h> 68185089Sraj#include <dev/pci/pcireg.h> 69185089Sraj#include <dev/pci/pcib_private.h> 70185089Sraj 71209131Sraj#include "ofw_bus_if.h" 72185089Sraj#include "pcib_if.h" 73185089Sraj 74185089Sraj#include <machine/resource.h> 75185089Sraj#include <machine/bus.h> 76185089Sraj 77185089Sraj#include <arm/mv/mvreg.h> 78185089Sraj#include <arm/mv/mvvar.h> 79209131Sraj#include <arm/mv/mvwin.h> 80185089Sraj 81240493Sgber#ifdef DEBUG 82240493Sgber#define debugf(fmt, args...) do { printf(fmt,##args); } while (0) 83240493Sgber#else 84240493Sgber#define debugf(fmt, args...) 85240493Sgber#endif 86240493Sgber 87260340Sian/* 88260340Sian * Code and data related to fdt-based PCI configuration. 89260340Sian * 90260340Sian * This stuff used to be in dev/fdt/fdt_pci.c and fdt_common.h, but it was 91260340Sian * always Marvell-specific so that was deleted and the code now lives here. 92260340Sian */ 93260340Sian 94260340Sianstruct mv_pci_range { 95260340Sian u_long base_pci; 96260340Sian u_long base_parent; 97260340Sian u_long len; 98260340Sian}; 99260340Sian 100260340Sian#define FDT_RANGES_CELLS ((3 + 3 + 2) * 2) 101260340Sian 102260340Sianstatic void 103260340Sianmv_pci_range_dump(struct mv_pci_range *range) 104260340Sian{ 105260340Sian#ifdef DEBUG 106260340Sian printf("\n"); 107260340Sian printf(" base_pci = 0x%08lx\n", range->base_pci); 108260340Sian printf(" base_par = 0x%08lx\n", range->base_parent); 109260340Sian printf(" len = 0x%08lx\n", range->len); 110260340Sian#endif 111260340Sian} 112260340Sian 113260340Sianstatic int 114260340Sianmv_pci_ranges_decode(phandle_t node, struct mv_pci_range *io_space, 115260340Sian struct mv_pci_range *mem_space) 116260340Sian{ 117260340Sian pcell_t ranges[FDT_RANGES_CELLS]; 118260340Sian struct mv_pci_range *pci_space; 119260340Sian pcell_t addr_cells, size_cells, par_addr_cells; 120260340Sian pcell_t *rangesptr; 121260340Sian pcell_t cell0, cell1, cell2; 122260340Sian int tuple_size, tuples, i, rv, offset_cells, len; 123260340Sian 124260340Sian /* 125260340Sian * Retrieve 'ranges' property. 126260340Sian */ 127260340Sian if ((fdt_addrsize_cells(node, &addr_cells, &size_cells)) != 0) 128260340Sian return (EINVAL); 129260340Sian if (addr_cells != 3 || size_cells != 2) 130260340Sian return (ERANGE); 131260340Sian 132260340Sian par_addr_cells = fdt_parent_addr_cells(node); 133260340Sian if (par_addr_cells > 3) 134260340Sian return (ERANGE); 135260340Sian 136260340Sian len = OF_getproplen(node, "ranges"); 137260340Sian if (len > sizeof(ranges)) 138260340Sian return (ENOMEM); 139260340Sian 140260340Sian if (OF_getprop(node, "ranges", ranges, sizeof(ranges)) <= 0) 141260340Sian return (EINVAL); 142260340Sian 143260340Sian tuple_size = sizeof(pcell_t) * (addr_cells + par_addr_cells + 144260340Sian size_cells); 145260340Sian tuples = len / tuple_size; 146260340Sian 147260340Sian /* 148260340Sian * Initialize the ranges so that we don't have to worry about 149260340Sian * having them all defined in the FDT. In particular, it is 150260340Sian * perfectly fine not to want I/O space on PCI busses. 151260340Sian */ 152260340Sian bzero(io_space, sizeof(*io_space)); 153260340Sian bzero(mem_space, sizeof(*mem_space)); 154260340Sian 155260340Sian rangesptr = &ranges[0]; 156260340Sian offset_cells = 0; 157260340Sian for (i = 0; i < tuples; i++) { 158260340Sian cell0 = fdt_data_get((void *)rangesptr, 1); 159260340Sian rangesptr++; 160260340Sian cell1 = fdt_data_get((void *)rangesptr, 1); 161260340Sian rangesptr++; 162260340Sian cell2 = fdt_data_get((void *)rangesptr, 1); 163260340Sian rangesptr++; 164260340Sian 165260340Sian if (cell0 & 0x02000000) { 166260340Sian pci_space = mem_space; 167260340Sian } else if (cell0 & 0x01000000) { 168260340Sian pci_space = io_space; 169260340Sian } else { 170260340Sian rv = ERANGE; 171260340Sian goto out; 172260340Sian } 173260340Sian 174260340Sian if (par_addr_cells == 3) { 175260340Sian /* 176260340Sian * This is a PCI subnode 'ranges'. Skip cell0 and 177260340Sian * cell1 of this entry and only use cell2. 178260340Sian */ 179260340Sian offset_cells = 2; 180260340Sian rangesptr += offset_cells; 181260340Sian } 182260340Sian 183275799Sbr if ((par_addr_cells - offset_cells) > 2) { 184260340Sian rv = ERANGE; 185260340Sian goto out; 186260340Sian } 187260340Sian pci_space->base_parent = fdt_data_get((void *)rangesptr, 188260340Sian par_addr_cells - offset_cells); 189260340Sian rangesptr += par_addr_cells - offset_cells; 190260340Sian 191275802Sbr if (size_cells > 2) { 192260340Sian rv = ERANGE; 193260340Sian goto out; 194260340Sian } 195260340Sian pci_space->len = fdt_data_get((void *)rangesptr, size_cells); 196260340Sian rangesptr += size_cells; 197260340Sian 198260340Sian pci_space->base_pci = cell2; 199260340Sian } 200260340Sian rv = 0; 201260340Sianout: 202260340Sian return (rv); 203260340Sian} 204260340Sian 205260340Sianstatic int 206260340Sianmv_pci_ranges(phandle_t node, struct mv_pci_range *io_space, 207260340Sian struct mv_pci_range *mem_space) 208260340Sian{ 209260340Sian int err; 210260340Sian 211260340Sian debugf("Processing PCI node: %x\n", node); 212260340Sian if ((err = mv_pci_ranges_decode(node, io_space, mem_space)) != 0) { 213260340Sian debugf("could not decode parent PCI node 'ranges'\n"); 214260340Sian return (err); 215260340Sian } 216260340Sian 217260340Sian debugf("Post fixup dump:\n"); 218260340Sian mv_pci_range_dump(io_space); 219260340Sian mv_pci_range_dump(mem_space); 220260340Sian return (0); 221260340Sian} 222260340Sian 223260340Sianint 224298627Sbrmv_pci_devmap(phandle_t node, struct devmap_entry *devmap, vm_offset_t io_va, 225260340Sian vm_offset_t mem_va) 226260340Sian{ 227260340Sian struct mv_pci_range io_space, mem_space; 228260340Sian int error; 229260340Sian 230260340Sian if ((error = mv_pci_ranges_decode(node, &io_space, &mem_space)) != 0) 231260340Sian return (error); 232260340Sian 233260340Sian devmap->pd_va = (io_va ? io_va : io_space.base_parent); 234260340Sian devmap->pd_pa = io_space.base_parent; 235260340Sian devmap->pd_size = io_space.len; 236260340Sian devmap++; 237260340Sian 238260340Sian devmap->pd_va = (mem_va ? mem_va : mem_space.base_parent); 239260340Sian devmap->pd_pa = mem_space.base_parent; 240260340Sian devmap->pd_size = mem_space.len; 241260340Sian return (0); 242260340Sian} 243260340Sian 244260340Sian/* 245260340Sian * Code and data related to the Marvell pcib driver. 246260340Sian */ 247260340Sian 248258780Seadler#define PCI_CFG_ENA (1U << 31) 249185089Sraj#define PCI_CFG_BUS(bus) (((bus) & 0xff) << 16) 250185089Sraj#define PCI_CFG_DEV(dev) (((dev) & 0x1f) << 11) 251185089Sraj#define PCI_CFG_FUN(fun) (((fun) & 0x7) << 8) 252185089Sraj#define PCI_CFG_PCIE_REG(reg) ((reg) & 0xfc) 253185089Sraj 254185089Sraj#define PCI_REG_CFG_ADDR 0x0C78 255185089Sraj#define PCI_REG_CFG_DATA 0x0C7C 256185089Sraj 257185089Sraj#define PCIE_REG_CFG_ADDR 0x18F8 258185089Sraj#define PCIE_REG_CFG_DATA 0x18FC 259185089Sraj#define PCIE_REG_CONTROL 0x1A00 260185089Sraj#define PCIE_CTRL_LINK1X 0x00000001 261185089Sraj#define PCIE_REG_STATUS 0x1A04 262185089Sraj#define PCIE_REG_IRQ_MASK 0x1910 263185089Sraj 264240489Sgber#define PCIE_CONTROL_ROOT_CMPLX (1 << 1) 265240489Sgber#define PCIE_CONTROL_HOT_RESET (1 << 24) 266185089Sraj 267240489Sgber#define PCIE_LINK_TIMEOUT 1000000 268185089Sraj 269240489Sgber#define PCIE_STATUS_LINK_DOWN 1 270240489Sgber#define PCIE_STATUS_DEV_OFFS 16 271185089Sraj 272240489Sgber/* Minimum PCI Memory and I/O allocations taken from PCI spec (in bytes) */ 273240489Sgber#define PCI_MIN_IO_ALLOC 4 274240489Sgber#define PCI_MIN_MEM_ALLOC 16 275240489Sgber 276240489Sgber#define BITS_PER_UINT32 (NBBY * sizeof(uint32_t)) 277240489Sgber 278209131Srajstruct mv_pcib_softc { 279185089Sraj device_t sc_dev; 280185089Sraj 281209131Sraj struct rman sc_mem_rman; 282209131Sraj bus_addr_t sc_mem_base; 283209131Sraj bus_addr_t sc_mem_size; 284240489Sgber uint32_t sc_mem_map[MV_PCI_MEM_SLICE_SIZE / 285240489Sgber (PCI_MIN_MEM_ALLOC * BITS_PER_UINT32)]; 286240489Sgber int sc_win_target; 287209131Sraj int sc_mem_win_attr; 288185089Sraj 289209131Sraj struct rman sc_io_rman; 290209131Sraj bus_addr_t sc_io_base; 291209131Sraj bus_addr_t sc_io_size; 292240489Sgber uint32_t sc_io_map[MV_PCI_IO_SLICE_SIZE / 293240489Sgber (PCI_MIN_IO_ALLOC * BITS_PER_UINT32)]; 294209131Sraj int sc_io_win_attr; 295185089Sraj 296185089Sraj struct resource *sc_res; 297185089Sraj bus_space_handle_t sc_bsh; 298185089Sraj bus_space_tag_t sc_bst; 299185089Sraj int sc_rid; 300185089Sraj 301240493Sgber struct mtx sc_msi_mtx; 302240493Sgber uint32_t sc_msi_bitmap; 303240493Sgber 304185089Sraj int sc_busnr; /* Host bridge bus number */ 305185089Sraj int sc_devnr; /* Host bridge device number */ 306209131Sraj int sc_type; 307240489Sgber int sc_mode; /* Endpoint / Root Complex */ 308185089Sraj 309259484Snwhitehorn struct ofw_bus_iinfo sc_pci_iinfo; 310185089Sraj}; 311185089Sraj 312209131Sraj/* Local forward prototypes */ 313209131Srajstatic int mv_pcib_decode_win(phandle_t, struct mv_pcib_softc *); 314209131Srajstatic void mv_pcib_hw_cfginit(void); 315209131Srajstatic uint32_t mv_pcib_hw_cfgread(struct mv_pcib_softc *, u_int, u_int, 316209131Sraj u_int, u_int, int); 317209131Srajstatic void mv_pcib_hw_cfgwrite(struct mv_pcib_softc *, u_int, u_int, 318209131Sraj u_int, u_int, uint32_t, int); 319209131Srajstatic int mv_pcib_init(struct mv_pcib_softc *, int, int); 320209131Srajstatic int mv_pcib_init_all_bars(struct mv_pcib_softc *, int, int, int, int); 321209131Srajstatic void mv_pcib_init_bridge(struct mv_pcib_softc *, int, int, int); 322209131Srajstatic inline void pcib_write_irq_mask(struct mv_pcib_softc *, uint32_t); 323240489Sgberstatic void mv_pcib_enable(struct mv_pcib_softc *, uint32_t); 324240489Sgberstatic int mv_pcib_mem_init(struct mv_pcib_softc *); 325185089Sraj 326209131Sraj/* Forward prototypes */ 327209131Srajstatic int mv_pcib_probe(device_t); 328209131Srajstatic int mv_pcib_attach(device_t); 329209131Sraj 330209131Srajstatic struct resource *mv_pcib_alloc_resource(device_t, device_t, int, int *, 331294883Sjhibbits rman_res_t, rman_res_t, rman_res_t, u_int); 332209131Srajstatic int mv_pcib_release_resource(device_t, device_t, int, int, 333185089Sraj struct resource *); 334209131Srajstatic int mv_pcib_read_ivar(device_t, device_t, int, uintptr_t *); 335209131Srajstatic int mv_pcib_write_ivar(device_t, device_t, int, uintptr_t); 336185089Sraj 337209131Srajstatic int mv_pcib_maxslots(device_t); 338209131Srajstatic uint32_t mv_pcib_read_config(device_t, u_int, u_int, u_int, u_int, int); 339209131Srajstatic void mv_pcib_write_config(device_t, u_int, u_int, u_int, u_int, 340185089Sraj uint32_t, int); 341209131Srajstatic int mv_pcib_route_interrupt(device_t, device_t, int); 342240493Sgber#if defined(SOC_MV_ARMADAXP) 343240493Sgberstatic int mv_pcib_alloc_msi(device_t, device_t, int, int, int *); 344240493Sgberstatic int mv_pcib_map_msi(device_t, device_t, int, uint64_t *, uint32_t *); 345240493Sgberstatic int mv_pcib_release_msi(device_t, device_t, int, int *); 346240493Sgber#endif 347185089Sraj 348185089Sraj/* 349185089Sraj * Bus interface definitions. 350185089Sraj */ 351209131Srajstatic device_method_t mv_pcib_methods[] = { 352185089Sraj /* Device interface */ 353209131Sraj DEVMETHOD(device_probe, mv_pcib_probe), 354209131Sraj DEVMETHOD(device_attach, mv_pcib_attach), 355185089Sraj 356185089Sraj /* Bus interface */ 357209131Sraj DEVMETHOD(bus_read_ivar, mv_pcib_read_ivar), 358209131Sraj DEVMETHOD(bus_write_ivar, mv_pcib_write_ivar), 359209131Sraj DEVMETHOD(bus_alloc_resource, mv_pcib_alloc_resource), 360209131Sraj DEVMETHOD(bus_release_resource, mv_pcib_release_resource), 361185089Sraj DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 362185089Sraj DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 363185089Sraj DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 364185089Sraj DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 365185089Sraj 366185089Sraj /* pcib interface */ 367209131Sraj DEVMETHOD(pcib_maxslots, mv_pcib_maxslots), 368209131Sraj DEVMETHOD(pcib_read_config, mv_pcib_read_config), 369209131Sraj DEVMETHOD(pcib_write_config, mv_pcib_write_config), 370209131Sraj DEVMETHOD(pcib_route_interrupt, mv_pcib_route_interrupt), 371240493Sgber 372240493Sgber#if defined(SOC_MV_ARMADAXP) 373240493Sgber DEVMETHOD(pcib_alloc_msi, mv_pcib_alloc_msi), 374240493Sgber DEVMETHOD(pcib_release_msi, mv_pcib_release_msi), 375240493Sgber DEVMETHOD(pcib_map_msi, mv_pcib_map_msi), 376240493Sgber#endif 377240493Sgber 378209131Sraj /* OFW bus interface */ 379209131Sraj DEVMETHOD(ofw_bus_get_compat, ofw_bus_gen_get_compat), 380209131Sraj DEVMETHOD(ofw_bus_get_model, ofw_bus_gen_get_model), 381209131Sraj DEVMETHOD(ofw_bus_get_name, ofw_bus_gen_get_name), 382209131Sraj DEVMETHOD(ofw_bus_get_node, ofw_bus_gen_get_node), 383209131Sraj DEVMETHOD(ofw_bus_get_type, ofw_bus_gen_get_type), 384209131Sraj 385227843Smarius DEVMETHOD_END 386185089Sraj}; 387185089Sraj 388209131Srajstatic driver_t mv_pcib_driver = { 389185089Sraj "pcib", 390209131Sraj mv_pcib_methods, 391209131Sraj sizeof(struct mv_pcib_softc), 392185089Sraj}; 393185089Sraj 394185089Srajdevclass_t pcib_devclass; 395185089Sraj 396261513SnwhitehornDRIVER_MODULE(pcib, ofwbus, mv_pcib_driver, pcib_devclass, 0, 0); 397185089Sraj 398185089Srajstatic struct mtx pcicfg_mtx; 399185089Sraj 400185089Srajstatic int 401209131Srajmv_pcib_probe(device_t self) 402185089Sraj{ 403218228Smarcel phandle_t node; 404185089Sraj 405218228Smarcel node = ofw_bus_get_node(self); 406218228Smarcel if (!fdt_is_type(node, "pci")) 407209131Sraj return (ENXIO); 408218228Smarcel 409259484Snwhitehorn if (!(ofw_bus_is_compatible(self, "mrvl,pcie") || 410259484Snwhitehorn ofw_bus_is_compatible(self, "mrvl,pci"))) 411209131Sraj return (ENXIO); 412185089Sraj 413209131Sraj device_set_desc(self, "Marvell Integrated PCI/PCI-E Controller"); 414209131Sraj return (BUS_PROBE_DEFAULT); 415185089Sraj} 416185089Sraj 417185089Srajstatic int 418209131Srajmv_pcib_attach(device_t self) 419185089Sraj{ 420209131Sraj struct mv_pcib_softc *sc; 421209131Sraj phandle_t node, parnode; 422240489Sgber uint32_t val, unit; 423209131Sraj int err; 424185089Sraj 425185089Sraj sc = device_get_softc(self); 426209131Sraj sc->sc_dev = self; 427240489Sgber unit = fdt_get_unit(self); 428185089Sraj 429240489Sgber 430218228Smarcel node = ofw_bus_get_node(self); 431218228Smarcel parnode = OF_parent(node); 432218228Smarcel if (fdt_is_compatible(node, "mrvl,pcie")) { 433209131Sraj sc->sc_type = MV_TYPE_PCIE; 434240489Sgber sc->sc_win_target = MV_WIN_PCIE_TARGET(unit); 435240489Sgber sc->sc_mem_win_attr = MV_WIN_PCIE_MEM_ATTR(unit); 436240489Sgber sc->sc_io_win_attr = MV_WIN_PCIE_IO_ATTR(unit); 437218228Smarcel } else if (fdt_is_compatible(node, "mrvl,pci")) { 438209131Sraj sc->sc_type = MV_TYPE_PCI; 439240489Sgber sc->sc_win_target = MV_WIN_PCI_TARGET; 440209131Sraj sc->sc_mem_win_attr = MV_WIN_PCI_MEM_ATTR; 441209131Sraj sc->sc_io_win_attr = MV_WIN_PCI_IO_ATTR; 442209131Sraj } else 443185089Sraj return (ENXIO); 444185089Sraj 445209131Sraj /* 446209131Sraj * Retrieve our mem-mapped registers range. 447209131Sraj */ 448185089Sraj sc->sc_rid = 0; 449185089Sraj sc->sc_res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &sc->sc_rid, 450185089Sraj RF_ACTIVE); 451185089Sraj if (sc->sc_res == NULL) { 452209131Sraj device_printf(self, "could not map memory\n"); 453185089Sraj return (ENXIO); 454185089Sraj } 455185089Sraj sc->sc_bst = rman_get_bustag(sc->sc_res); 456185089Sraj sc->sc_bsh = rman_get_bushandle(sc->sc_res); 457185089Sraj 458240489Sgber val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, PCIE_REG_CONTROL); 459240489Sgber sc->sc_mode = (val & PCIE_CONTROL_ROOT_CMPLX ? MV_MODE_ROOT : 460240489Sgber MV_MODE_ENDPOINT); 461240489Sgber 462209131Sraj /* 463240489Sgber * Get PCI interrupt info. 464240489Sgber */ 465259484Snwhitehorn if (sc->sc_mode == MV_MODE_ROOT) 466259484Snwhitehorn ofw_bus_setup_iinfo(node, &sc->sc_pci_iinfo, sizeof(pcell_t)); 467240489Sgber 468240489Sgber /* 469209131Sraj * Configure decode windows for PCI(E) access. 470209131Sraj */ 471209131Sraj if (mv_pcib_decode_win(node, sc) != 0) 472209131Sraj return (ENXIO); 473209131Sraj 474209131Sraj mv_pcib_hw_cfginit(); 475209131Sraj 476209131Sraj /* 477240489Sgber * Enable PCIE device. 478209131Sraj */ 479240489Sgber mv_pcib_enable(sc, unit); 480185089Sraj 481240489Sgber /* 482240489Sgber * Memory management. 483240489Sgber */ 484240489Sgber err = mv_pcib_mem_init(sc); 485240489Sgber if (err) 486240489Sgber return (err); 487185089Sraj 488240489Sgber if (sc->sc_mode == MV_MODE_ROOT) { 489240489Sgber err = mv_pcib_init(sc, sc->sc_busnr, 490240489Sgber mv_pcib_maxslots(sc->sc_dev)); 491240489Sgber if (err) 492240489Sgber goto error; 493240489Sgber 494240489Sgber device_add_child(self, "pci", -1); 495240489Sgber } else { 496240489Sgber sc->sc_devnr = 1; 497240489Sgber bus_space_write_4(sc->sc_bst, sc->sc_bsh, 498240489Sgber PCIE_REG_STATUS, 1 << PCIE_STATUS_DEV_OFFS); 499240489Sgber device_add_child(self, "pci_ep", -1); 500240489Sgber } 501240489Sgber 502240493Sgber mtx_init(&sc->sc_msi_mtx, "msi_mtx", NULL, MTX_DEF); 503240489Sgber return (bus_generic_attach(self)); 504240489Sgber 505240489Sgbererror: 506240489Sgber /* XXX SYS_RES_ should be released here */ 507240489Sgber rman_fini(&sc->sc_mem_rman); 508240489Sgber rman_fini(&sc->sc_io_rman); 509240489Sgber 510240489Sgber return (err); 511240489Sgber} 512240489Sgber 513240489Sgberstatic void 514240489Sgbermv_pcib_enable(struct mv_pcib_softc *sc, uint32_t unit) 515240489Sgber{ 516240489Sgber uint32_t val; 517240489Sgber#if !defined(SOC_MV_ARMADAXP) 518240489Sgber int timeout; 519240489Sgber 520240489Sgber /* 521240489Sgber * Check if PCIE device is enabled. 522240489Sgber */ 523240489Sgber if (read_cpu_ctrl(CPU_CONTROL) & CPU_CONTROL_PCIE_DISABLE(unit)) { 524240489Sgber write_cpu_ctrl(CPU_CONTROL, read_cpu_ctrl(CPU_CONTROL) & 525240489Sgber ~(CPU_CONTROL_PCIE_DISABLE(unit))); 526240489Sgber 527240489Sgber timeout = PCIE_LINK_TIMEOUT; 528240489Sgber val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, 529240489Sgber PCIE_REG_STATUS); 530240489Sgber while (((val & PCIE_STATUS_LINK_DOWN) == 1) && (timeout > 0)) { 531240489Sgber DELAY(1000); 532240489Sgber timeout -= 1000; 533240489Sgber val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, 534240489Sgber PCIE_REG_STATUS); 535240489Sgber } 536240489Sgber } 537240489Sgber#endif 538240489Sgber 539240489Sgber 540240489Sgber if (sc->sc_mode == MV_MODE_ROOT) { 541240489Sgber /* 542240489Sgber * Enable PCI bridge. 543240489Sgber */ 544240489Sgber val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, PCIR_COMMAND); 545240489Sgber val |= PCIM_CMD_SERRESPEN | PCIM_CMD_BUSMASTEREN | 546240489Sgber PCIM_CMD_MEMEN | PCIM_CMD_PORTEN; 547240489Sgber bus_space_write_4(sc->sc_bst, sc->sc_bsh, PCIR_COMMAND, val); 548240489Sgber } 549240489Sgber} 550240489Sgber 551240489Sgberstatic int 552240489Sgbermv_pcib_mem_init(struct mv_pcib_softc *sc) 553240489Sgber{ 554240489Sgber int err; 555240489Sgber 556240489Sgber /* 557240489Sgber * Memory management. 558240489Sgber */ 559209131Sraj sc->sc_mem_rman.rm_type = RMAN_ARRAY; 560209131Sraj err = rman_init(&sc->sc_mem_rman); 561186932Sraj if (err) 562186932Sraj return (err); 563186932Sraj 564209131Sraj sc->sc_io_rman.rm_type = RMAN_ARRAY; 565209131Sraj err = rman_init(&sc->sc_io_rman); 566186932Sraj if (err) { 567209131Sraj rman_fini(&sc->sc_mem_rman); 568186932Sraj return (err); 569186932Sraj } 570186932Sraj 571209131Sraj err = rman_manage_region(&sc->sc_mem_rman, sc->sc_mem_base, 572209131Sraj sc->sc_mem_base + sc->sc_mem_size - 1); 573186932Sraj if (err) 574186932Sraj goto error; 575186932Sraj 576209131Sraj err = rman_manage_region(&sc->sc_io_rman, sc->sc_io_base, 577209131Sraj sc->sc_io_base + sc->sc_io_size - 1); 578186932Sraj if (err) 579186932Sraj goto error; 580186932Sraj 581240489Sgber return (0); 582185089Sraj 583186932Srajerror: 584209131Sraj rman_fini(&sc->sc_mem_rman); 585209131Sraj rman_fini(&sc->sc_io_rman); 586240489Sgber 587186932Sraj return (err); 588185089Sraj} 589185089Sraj 590240489Sgberstatic inline uint32_t 591240489Sgberpcib_bit_get(uint32_t *map, uint32_t bit) 592240489Sgber{ 593240489Sgber uint32_t n = bit / BITS_PER_UINT32; 594240489Sgber 595240489Sgber bit = bit % BITS_PER_UINT32; 596240489Sgber return (map[n] & (1 << bit)); 597240489Sgber} 598240489Sgber 599240489Sgberstatic inline void 600240489Sgberpcib_bit_set(uint32_t *map, uint32_t bit) 601240489Sgber{ 602240489Sgber uint32_t n = bit / BITS_PER_UINT32; 603240489Sgber 604240489Sgber bit = bit % BITS_PER_UINT32; 605240489Sgber map[n] |= (1 << bit); 606240489Sgber} 607240489Sgber 608240489Sgberstatic inline uint32_t 609240489Sgberpcib_map_check(uint32_t *map, uint32_t start, uint32_t bits) 610240489Sgber{ 611240489Sgber uint32_t i; 612240489Sgber 613240489Sgber for (i = start; i < start + bits; i++) 614240489Sgber if (pcib_bit_get(map, i)) 615240489Sgber return (0); 616240489Sgber 617240489Sgber return (1); 618240489Sgber} 619240489Sgber 620240489Sgberstatic inline void 621240489Sgberpcib_map_set(uint32_t *map, uint32_t start, uint32_t bits) 622240489Sgber{ 623240489Sgber uint32_t i; 624240489Sgber 625240489Sgber for (i = start; i < start + bits; i++) 626240489Sgber pcib_bit_set(map, i); 627240489Sgber} 628240489Sgber 629240489Sgber/* 630240489Sgber * The idea of this allocator is taken from ARM No-Cache memory 631240489Sgber * management code (sys/arm/arm/vm_machdep.c). 632240489Sgber */ 633240489Sgberstatic bus_addr_t 634240489Sgberpcib_alloc(struct mv_pcib_softc *sc, uint32_t smask) 635240489Sgber{ 636240489Sgber uint32_t bits, bits_limit, i, *map, min_alloc, size; 637240489Sgber bus_addr_t addr = 0; 638240489Sgber bus_addr_t base; 639240489Sgber 640240489Sgber if (smask & 1) { 641240489Sgber base = sc->sc_io_base; 642240489Sgber min_alloc = PCI_MIN_IO_ALLOC; 643240489Sgber bits_limit = sc->sc_io_size / min_alloc; 644240489Sgber map = sc->sc_io_map; 645240489Sgber smask &= ~0x3; 646240489Sgber } else { 647240489Sgber base = sc->sc_mem_base; 648240489Sgber min_alloc = PCI_MIN_MEM_ALLOC; 649240489Sgber bits_limit = sc->sc_mem_size / min_alloc; 650240489Sgber map = sc->sc_mem_map; 651240489Sgber smask &= ~0xF; 652240489Sgber } 653240489Sgber 654240489Sgber size = ~smask + 1; 655240489Sgber bits = size / min_alloc; 656240489Sgber 657240489Sgber for (i = 0; i + bits <= bits_limit; i += bits) 658240489Sgber if (pcib_map_check(map, i, bits)) { 659240489Sgber pcib_map_set(map, i, bits); 660240489Sgber addr = base + (i * min_alloc); 661240489Sgber return (addr); 662240489Sgber } 663240489Sgber 664240489Sgber return (addr); 665240489Sgber} 666240489Sgber 667185089Srajstatic int 668209131Srajmv_pcib_init_bar(struct mv_pcib_softc *sc, int bus, int slot, int func, 669185089Sraj int barno) 670185089Sraj{ 671240489Sgber uint32_t addr, bar; 672185089Sraj int reg, width; 673185089Sraj 674185089Sraj reg = PCIR_BAR(barno); 675240489Sgber 676240489Sgber /* 677240489Sgber * Need to init the BAR register with 0xffffffff before correct 678240489Sgber * value can be read. 679240489Sgber */ 680240489Sgber mv_pcib_write_config(sc->sc_dev, bus, slot, func, reg, ~0, 4); 681209131Sraj bar = mv_pcib_read_config(sc->sc_dev, bus, slot, func, reg, 4); 682185089Sraj if (bar == 0) 683185089Sraj return (1); 684185089Sraj 685185089Sraj /* Calculate BAR size: 64 or 32 bit (in 32-bit units) */ 686185089Sraj width = ((bar & 7) == 4) ? 2 : 1; 687185089Sraj 688240489Sgber addr = pcib_alloc(sc, bar); 689240489Sgber if (!addr) 690185089Sraj return (-1); 691185089Sraj 692185089Sraj if (bootverbose) 693240489Sgber printf("PCI %u:%u:%u: reg %x: smask=%08x: addr=%08x\n", 694240489Sgber bus, slot, func, reg, bar, addr); 695185089Sraj 696209131Sraj mv_pcib_write_config(sc->sc_dev, bus, slot, func, reg, addr, 4); 697185089Sraj if (width == 2) 698209131Sraj mv_pcib_write_config(sc->sc_dev, bus, slot, func, reg + 4, 699185089Sraj 0, 4); 700185089Sraj 701185089Sraj return (width); 702185089Sraj} 703185089Sraj 704185089Srajstatic void 705209131Srajmv_pcib_init_bridge(struct mv_pcib_softc *sc, int bus, int slot, int func) 706185089Sraj{ 707185089Sraj bus_addr_t io_base, mem_base; 708185089Sraj uint32_t io_limit, mem_limit; 709185089Sraj int secbus; 710185089Sraj 711209131Sraj io_base = sc->sc_io_base; 712209131Sraj io_limit = io_base + sc->sc_io_size - 1; 713209131Sraj mem_base = sc->sc_mem_base; 714209131Sraj mem_limit = mem_base + sc->sc_mem_size - 1; 715185089Sraj 716185089Sraj /* Configure I/O decode registers */ 717209131Sraj mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_IOBASEL_1, 718185639Sraj io_base >> 8, 1); 719209131Sraj mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_IOBASEH_1, 720185639Sraj io_base >> 16, 2); 721209131Sraj mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_IOLIMITL_1, 722185089Sraj io_limit >> 8, 1); 723209131Sraj mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_IOLIMITH_1, 724185089Sraj io_limit >> 16, 2); 725185089Sraj 726185089Sraj /* Configure memory decode registers */ 727209131Sraj mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_MEMBASE_1, 728185089Sraj mem_base >> 16, 2); 729209131Sraj mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_MEMLIMIT_1, 730185089Sraj mem_limit >> 16, 2); 731185089Sraj 732185089Sraj /* Disable memory prefetch decode */ 733209131Sraj mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_PMBASEL_1, 734185089Sraj 0x10, 2); 735209131Sraj mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_PMBASEH_1, 736185089Sraj 0x0, 4); 737209131Sraj mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_PMLIMITL_1, 738185089Sraj 0xF, 2); 739209131Sraj mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_PMLIMITH_1, 740185089Sraj 0x0, 4); 741185089Sraj 742209131Sraj secbus = mv_pcib_read_config(sc->sc_dev, bus, slot, func, 743185089Sraj PCIR_SECBUS_1, 1); 744185089Sraj 745185089Sraj /* Configure buses behind the bridge */ 746209131Sraj mv_pcib_init(sc, secbus, PCI_SLOTMAX); 747185089Sraj} 748185089Sraj 749185089Srajstatic int 750209131Srajmv_pcib_init(struct mv_pcib_softc *sc, int bus, int maxslot) 751185089Sraj{ 752185089Sraj int slot, func, maxfunc, error; 753185089Sraj uint8_t hdrtype, command, class, subclass; 754185089Sraj 755185089Sraj for (slot = 0; slot <= maxslot; slot++) { 756185089Sraj maxfunc = 0; 757185089Sraj for (func = 0; func <= maxfunc; func++) { 758209131Sraj hdrtype = mv_pcib_read_config(sc->sc_dev, bus, slot, 759185089Sraj func, PCIR_HDRTYPE, 1); 760185089Sraj 761185089Sraj if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE) 762185089Sraj continue; 763185089Sraj 764185089Sraj if (func == 0 && (hdrtype & PCIM_MFDEV)) 765185089Sraj maxfunc = PCI_FUNCMAX; 766185089Sraj 767209131Sraj command = mv_pcib_read_config(sc->sc_dev, bus, slot, 768185089Sraj func, PCIR_COMMAND, 1); 769185089Sraj command &= ~(PCIM_CMD_MEMEN | PCIM_CMD_PORTEN); 770209131Sraj mv_pcib_write_config(sc->sc_dev, bus, slot, func, 771185089Sraj PCIR_COMMAND, command, 1); 772185089Sraj 773209131Sraj error = mv_pcib_init_all_bars(sc, bus, slot, func, 774185089Sraj hdrtype); 775185089Sraj 776185089Sraj if (error) 777185089Sraj return (error); 778185089Sraj 779185089Sraj command |= PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN | 780185089Sraj PCIM_CMD_PORTEN; 781209131Sraj mv_pcib_write_config(sc->sc_dev, bus, slot, func, 782185089Sraj PCIR_COMMAND, command, 1); 783185089Sraj 784185089Sraj /* Handle PCI-PCI bridges */ 785209131Sraj class = mv_pcib_read_config(sc->sc_dev, bus, slot, 786185089Sraj func, PCIR_CLASS, 1); 787209131Sraj subclass = mv_pcib_read_config(sc->sc_dev, bus, slot, 788185089Sraj func, PCIR_SUBCLASS, 1); 789185089Sraj 790185089Sraj if (class != PCIC_BRIDGE || 791185089Sraj subclass != PCIS_BRIDGE_PCI) 792185089Sraj continue; 793185089Sraj 794209131Sraj mv_pcib_init_bridge(sc, bus, slot, func); 795185089Sraj } 796185089Sraj } 797185089Sraj 798185089Sraj /* Enable all ABCD interrupts */ 799185089Sraj pcib_write_irq_mask(sc, (0xF << 24)); 800185089Sraj 801185089Sraj return (0); 802185089Sraj} 803185089Sraj 804209131Srajstatic int 805209131Srajmv_pcib_init_all_bars(struct mv_pcib_softc *sc, int bus, int slot, 806209131Sraj int func, int hdrtype) 807209131Sraj{ 808209131Sraj int maxbar, bar, i; 809209131Sraj 810209131Sraj maxbar = (hdrtype & PCIM_HDRTYPE) ? 0 : 6; 811209131Sraj bar = 0; 812209131Sraj 813209131Sraj /* Program the base address registers */ 814209131Sraj while (bar < maxbar) { 815209131Sraj i = mv_pcib_init_bar(sc, bus, slot, func, bar); 816209131Sraj bar += i; 817209131Sraj if (i < 0) { 818209131Sraj device_printf(sc->sc_dev, 819209131Sraj "PCI IO/Memory space exhausted\n"); 820209131Sraj return (ENOMEM); 821209131Sraj } 822209131Sraj } 823209131Sraj 824209131Sraj return (0); 825209131Sraj} 826209131Sraj 827185089Srajstatic struct resource * 828209131Srajmv_pcib_alloc_resource(device_t dev, device_t child, int type, int *rid, 829294883Sjhibbits rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 830185089Sraj{ 831209131Sraj struct mv_pcib_softc *sc = device_get_softc(dev); 832186932Sraj struct rman *rm = NULL; 833186932Sraj struct resource *res; 834185089Sraj 835186932Sraj switch (type) { 836186932Sraj case SYS_RES_IOPORT: 837209131Sraj rm = &sc->sc_io_rman; 838186932Sraj break; 839186932Sraj case SYS_RES_MEMORY: 840209131Sraj rm = &sc->sc_mem_rman; 841186932Sraj break; 842186932Sraj default: 843240489Sgber return (BUS_ALLOC_RESOURCE(device_get_parent(dev), dev, 844186932Sraj type, rid, start, end, count, flags)); 845297793Spfg } 846186932Sraj 847295832Sjhibbits if (RMAN_IS_DEFAULT_RANGE(start, end)) { 848240489Sgber start = sc->sc_mem_base; 849240489Sgber end = sc->sc_mem_base + sc->sc_mem_size - 1; 850240489Sgber count = sc->sc_mem_size; 851240489Sgber } 852240489Sgber 853240489Sgber if ((start < sc->sc_mem_base) || (start + count - 1 != end) || 854240489Sgber (end > sc->sc_mem_base + sc->sc_mem_size - 1)) 855240489Sgber return (NULL); 856240489Sgber 857186932Sraj res = rman_reserve_resource(rm, start, end, count, flags, child); 858186932Sraj if (res == NULL) 859186932Sraj return (NULL); 860186932Sraj 861186932Sraj rman_set_rid(res, *rid); 862209131Sraj rman_set_bustag(res, fdtbus_bs_tag); 863186932Sraj rman_set_bushandle(res, start); 864186932Sraj 865186932Sraj if (flags & RF_ACTIVE) 866186932Sraj if (bus_activate_resource(child, type, *rid, res)) { 867186932Sraj rman_release_resource(res); 868186932Sraj return (NULL); 869186932Sraj } 870186932Sraj 871186932Sraj return (res); 872185089Sraj} 873185089Sraj 874185089Srajstatic int 875209131Srajmv_pcib_release_resource(device_t dev, device_t child, int type, int rid, 876185089Sraj struct resource *res) 877185089Sraj{ 878185089Sraj 879186932Sraj if (type != SYS_RES_IOPORT && type != SYS_RES_MEMORY) 880186932Sraj return (BUS_RELEASE_RESOURCE(device_get_parent(dev), child, 881186932Sraj type, rid, res)); 882186932Sraj 883186932Sraj return (rman_release_resource(res)); 884185089Sraj} 885185089Sraj 886185089Srajstatic int 887209131Srajmv_pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 888185089Sraj{ 889209131Sraj struct mv_pcib_softc *sc = device_get_softc(dev); 890185089Sraj 891185089Sraj switch (which) { 892185089Sraj case PCIB_IVAR_BUS: 893185089Sraj *result = sc->sc_busnr; 894185089Sraj return (0); 895185089Sraj case PCIB_IVAR_DOMAIN: 896185089Sraj *result = device_get_unit(dev); 897185089Sraj return (0); 898185089Sraj } 899185089Sraj 900185089Sraj return (ENOENT); 901185089Sraj} 902185089Sraj 903185089Srajstatic int 904209131Srajmv_pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value) 905185089Sraj{ 906209131Sraj struct mv_pcib_softc *sc = device_get_softc(dev); 907185089Sraj 908185089Sraj switch (which) { 909185089Sraj case PCIB_IVAR_BUS: 910185089Sraj sc->sc_busnr = value; 911185089Sraj return (0); 912185089Sraj } 913185089Sraj 914185089Sraj return (ENOENT); 915185089Sraj} 916209131Sraj 917209131Srajstatic inline void 918209131Srajpcib_write_irq_mask(struct mv_pcib_softc *sc, uint32_t mask) 919209131Sraj{ 920209131Sraj 921294510Sandrew if (sc->sc_type != MV_TYPE_PCI) 922209131Sraj return; 923209131Sraj 924209131Sraj bus_space_write_4(sc->sc_bst, sc->sc_bsh, PCIE_REG_IRQ_MASK, mask); 925209131Sraj} 926209131Sraj 927209131Srajstatic void 928209131Srajmv_pcib_hw_cfginit(void) 929209131Sraj{ 930209131Sraj static int opened = 0; 931209131Sraj 932209131Sraj if (opened) 933209131Sraj return; 934209131Sraj 935209131Sraj mtx_init(&pcicfg_mtx, "pcicfg", NULL, MTX_SPIN); 936209131Sraj opened = 1; 937209131Sraj} 938209131Sraj 939209131Srajstatic uint32_t 940209131Srajmv_pcib_hw_cfgread(struct mv_pcib_softc *sc, u_int bus, u_int slot, 941209131Sraj u_int func, u_int reg, int bytes) 942209131Sraj{ 943209131Sraj uint32_t addr, data, ca, cd; 944209131Sraj 945209131Sraj ca = (sc->sc_type != MV_TYPE_PCI) ? 946209131Sraj PCIE_REG_CFG_ADDR : PCI_REG_CFG_ADDR; 947209131Sraj cd = (sc->sc_type != MV_TYPE_PCI) ? 948209131Sraj PCIE_REG_CFG_DATA : PCI_REG_CFG_DATA; 949209131Sraj addr = PCI_CFG_ENA | PCI_CFG_BUS(bus) | PCI_CFG_DEV(slot) | 950209131Sraj PCI_CFG_FUN(func) | PCI_CFG_PCIE_REG(reg); 951209131Sraj 952209131Sraj mtx_lock_spin(&pcicfg_mtx); 953209131Sraj bus_space_write_4(sc->sc_bst, sc->sc_bsh, ca, addr); 954209131Sraj 955209131Sraj data = ~0; 956209131Sraj switch (bytes) { 957209131Sraj case 1: 958209131Sraj data = bus_space_read_1(sc->sc_bst, sc->sc_bsh, 959209131Sraj cd + (reg & 3)); 960209131Sraj break; 961209131Sraj case 2: 962209131Sraj data = le16toh(bus_space_read_2(sc->sc_bst, sc->sc_bsh, 963209131Sraj cd + (reg & 2))); 964209131Sraj break; 965209131Sraj case 4: 966209131Sraj data = le32toh(bus_space_read_4(sc->sc_bst, sc->sc_bsh, 967209131Sraj cd)); 968209131Sraj break; 969209131Sraj } 970209131Sraj mtx_unlock_spin(&pcicfg_mtx); 971209131Sraj return (data); 972209131Sraj} 973209131Sraj 974209131Srajstatic void 975209131Srajmv_pcib_hw_cfgwrite(struct mv_pcib_softc *sc, u_int bus, u_int slot, 976209131Sraj u_int func, u_int reg, uint32_t data, int bytes) 977209131Sraj{ 978209131Sraj uint32_t addr, ca, cd; 979209131Sraj 980209131Sraj ca = (sc->sc_type != MV_TYPE_PCI) ? 981209131Sraj PCIE_REG_CFG_ADDR : PCI_REG_CFG_ADDR; 982209131Sraj cd = (sc->sc_type != MV_TYPE_PCI) ? 983209131Sraj PCIE_REG_CFG_DATA : PCI_REG_CFG_DATA; 984209131Sraj addr = PCI_CFG_ENA | PCI_CFG_BUS(bus) | PCI_CFG_DEV(slot) | 985209131Sraj PCI_CFG_FUN(func) | PCI_CFG_PCIE_REG(reg); 986209131Sraj 987209131Sraj mtx_lock_spin(&pcicfg_mtx); 988209131Sraj bus_space_write_4(sc->sc_bst, sc->sc_bsh, ca, addr); 989209131Sraj 990209131Sraj switch (bytes) { 991209131Sraj case 1: 992209131Sraj bus_space_write_1(sc->sc_bst, sc->sc_bsh, 993209131Sraj cd + (reg & 3), data); 994209131Sraj break; 995209131Sraj case 2: 996209131Sraj bus_space_write_2(sc->sc_bst, sc->sc_bsh, 997209131Sraj cd + (reg & 2), htole16(data)); 998209131Sraj break; 999209131Sraj case 4: 1000209131Sraj bus_space_write_4(sc->sc_bst, sc->sc_bsh, 1001209131Sraj cd, htole32(data)); 1002209131Sraj break; 1003209131Sraj } 1004209131Sraj mtx_unlock_spin(&pcicfg_mtx); 1005209131Sraj} 1006209131Sraj 1007209131Srajstatic int 1008209131Srajmv_pcib_maxslots(device_t dev) 1009209131Sraj{ 1010209131Sraj struct mv_pcib_softc *sc = device_get_softc(dev); 1011209131Sraj 1012209131Sraj return ((sc->sc_type != MV_TYPE_PCI) ? 1 : PCI_SLOTMAX); 1013209131Sraj} 1014209131Sraj 1015294430Szbbstatic int 1016294430Szbbmv_pcib_root_slot(device_t dev, u_int bus, u_int slot, u_int func) 1017294430Szbb{ 1018294430Szbb#if defined(SOC_MV_ARMADA38X) 1019294430Szbb struct mv_pcib_softc *sc = device_get_softc(dev); 1020294430Szbb uint32_t vendor, device; 1021294430Szbb 1022294430Szbb vendor = mv_pcib_hw_cfgread(sc, bus, slot, func, PCIR_VENDOR, 1023294430Szbb PCIR_VENDOR_LENGTH); 1024294430Szbb device = mv_pcib_hw_cfgread(sc, bus, slot, func, PCIR_DEVICE, 1025294430Szbb PCIR_DEVICE_LENGTH) & MV_DEV_FAMILY_MASK; 1026294430Szbb 1027294430Szbb return (vendor == PCI_VENDORID_MRVL && device == MV_DEV_ARMADA38X); 1028294430Szbb#else 1029294430Szbb /* On platforms other than Armada38x, root link is always at slot 0 */ 1030294430Szbb return (slot == 0); 1031294430Szbb#endif 1032294430Szbb} 1033294430Szbb 1034209131Srajstatic uint32_t 1035209131Srajmv_pcib_read_config(device_t dev, u_int bus, u_int slot, u_int func, 1036209131Sraj u_int reg, int bytes) 1037209131Sraj{ 1038209131Sraj struct mv_pcib_softc *sc = device_get_softc(dev); 1039209131Sraj 1040240489Sgber /* Return ~0 if link is inactive or trying to read from Root */ 1041240489Sgber if ((bus_space_read_4(sc->sc_bst, sc->sc_bsh, PCIE_REG_STATUS) & 1042294430Szbb PCIE_STATUS_LINK_DOWN) || mv_pcib_root_slot(dev, bus, slot, func)) 1043209131Sraj return (~0U); 1044209131Sraj 1045209131Sraj return (mv_pcib_hw_cfgread(sc, bus, slot, func, reg, bytes)); 1046209131Sraj} 1047209131Sraj 1048209131Srajstatic void 1049209131Srajmv_pcib_write_config(device_t dev, u_int bus, u_int slot, u_int func, 1050209131Sraj u_int reg, uint32_t val, int bytes) 1051209131Sraj{ 1052209131Sraj struct mv_pcib_softc *sc = device_get_softc(dev); 1053209131Sraj 1054240489Sgber /* Return if link is inactive or trying to write to Root */ 1055240489Sgber if ((bus_space_read_4(sc->sc_bst, sc->sc_bsh, PCIE_REG_STATUS) & 1056294430Szbb PCIE_STATUS_LINK_DOWN) || mv_pcib_root_slot(dev, bus, slot, func)) 1057209131Sraj return; 1058209131Sraj 1059209131Sraj mv_pcib_hw_cfgwrite(sc, bus, slot, func, reg, val, bytes); 1060209131Sraj} 1061209131Sraj 1062209131Srajstatic int 1063259484Snwhitehornmv_pcib_route_interrupt(device_t bus, device_t dev, int pin) 1064209131Sraj{ 1065209131Sraj struct mv_pcib_softc *sc; 1066259484Snwhitehorn struct ofw_pci_register reg; 1067261351Snwhitehorn uint32_t pintr, mintr[4]; 1068261351Snwhitehorn int icells; 1069259484Snwhitehorn phandle_t iparent; 1070209131Sraj 1071259484Snwhitehorn sc = device_get_softc(bus); 1072259484Snwhitehorn pintr = pin; 1073209131Sraj 1074259484Snwhitehorn /* Fabricate imap information in case this isn't an OFW device */ 1075259484Snwhitehorn bzero(®, sizeof(reg)); 1076259484Snwhitehorn reg.phys_hi = (pci_get_bus(dev) << OFW_PCI_PHYS_HI_BUSSHIFT) | 1077259484Snwhitehorn (pci_get_slot(dev) << OFW_PCI_PHYS_HI_DEVICESHIFT) | 1078259484Snwhitehorn (pci_get_function(dev) << OFW_PCI_PHYS_HI_FUNCTIONSHIFT); 1079209131Sraj 1080261351Snwhitehorn icells = ofw_bus_lookup_imap(ofw_bus_get_node(dev), &sc->sc_pci_iinfo, 1081261351Snwhitehorn ®, sizeof(reg), &pintr, sizeof(pintr), mintr, sizeof(mintr), 1082261351Snwhitehorn &iparent); 1083261351Snwhitehorn if (icells > 0) 1084261351Snwhitehorn return (ofw_bus_map_intr(dev, iparent, icells, mintr)); 1085259484Snwhitehorn 1086259484Snwhitehorn /* Maybe it's a real interrupt, not an intpin */ 1087259484Snwhitehorn if (pin > 4) 1088259484Snwhitehorn return (pin); 1089259484Snwhitehorn 1090259484Snwhitehorn device_printf(bus, "could not route pin %d for device %d.%d\n", 1091209131Sraj pin, pci_get_slot(dev), pci_get_function(dev)); 1092209131Sraj return (PCI_INVALID_IRQ); 1093209131Sraj} 1094209131Sraj 1095209131Srajstatic int 1096209131Srajmv_pcib_decode_win(phandle_t node, struct mv_pcib_softc *sc) 1097209131Sraj{ 1098260340Sian struct mv_pci_range io_space, mem_space; 1099209131Sraj device_t dev; 1100209131Sraj int error; 1101209131Sraj 1102209131Sraj dev = sc->sc_dev; 1103209131Sraj 1104260340Sian if ((error = mv_pci_ranges(node, &io_space, &mem_space)) != 0) { 1105209131Sraj device_printf(dev, "could not retrieve 'ranges' data\n"); 1106209131Sraj return (error); 1107209131Sraj } 1108209131Sraj 1109209131Sraj /* Configure CPU decoding windows */ 1110240489Sgber error = decode_win_cpu_set(sc->sc_win_target, 1111240489Sgber sc->sc_io_win_attr, io_space.base_parent, io_space.len, ~0); 1112209131Sraj if (error < 0) { 1113209131Sraj device_printf(dev, "could not set up CPU decode " 1114209131Sraj "window for PCI IO\n"); 1115209131Sraj return (ENXIO); 1116209131Sraj } 1117240489Sgber error = decode_win_cpu_set(sc->sc_win_target, 1118240489Sgber sc->sc_mem_win_attr, mem_space.base_parent, mem_space.len, 1119240489Sgber mem_space.base_parent); 1120209131Sraj if (error < 0) { 1121209131Sraj device_printf(dev, "could not set up CPU decode " 1122209131Sraj "windows for PCI MEM\n"); 1123209131Sraj return (ENXIO); 1124209131Sraj } 1125209131Sraj 1126209131Sraj sc->sc_io_base = io_space.base_parent; 1127209131Sraj sc->sc_io_size = io_space.len; 1128209131Sraj 1129209131Sraj sc->sc_mem_base = mem_space.base_parent; 1130209131Sraj sc->sc_mem_size = mem_space.len; 1131209131Sraj 1132209131Sraj return (0); 1133209131Sraj} 1134209131Sraj 1135240493Sgber#if defined(SOC_MV_ARMADAXP) 1136240493Sgberstatic int 1137240493Sgbermv_pcib_map_msi(device_t dev, device_t child, int irq, uint64_t *addr, 1138240493Sgber uint32_t *data) 1139240493Sgber{ 1140240493Sgber struct mv_pcib_softc *sc; 1141240493Sgber 1142240493Sgber sc = device_get_softc(dev); 1143240493Sgber irq = irq - MSI_IRQ; 1144240493Sgber 1145240493Sgber /* validate parameters */ 1146240493Sgber if (isclr(&sc->sc_msi_bitmap, irq)) { 1147240493Sgber device_printf(dev, "invalid MSI 0x%x\n", irq); 1148240493Sgber return (EINVAL); 1149240493Sgber } 1150240493Sgber 1151240493Sgber mv_msi_data(irq, addr, data); 1152240493Sgber 1153240493Sgber debugf("%s: irq: %d addr: %jx data: %x\n", 1154240493Sgber __func__, irq, *addr, *data); 1155240493Sgber 1156240493Sgber return (0); 1157240493Sgber} 1158240493Sgber 1159240493Sgberstatic int 1160240493Sgbermv_pcib_alloc_msi(device_t dev, device_t child, int count, 1161240493Sgber int maxcount __unused, int *irqs) 1162240493Sgber{ 1163240493Sgber struct mv_pcib_softc *sc; 1164240493Sgber u_int start = 0, i; 1165240493Sgber 1166240493Sgber if (powerof2(count) == 0 || count > MSI_IRQ_NUM) 1167240493Sgber return (EINVAL); 1168240493Sgber 1169240493Sgber sc = device_get_softc(dev); 1170240493Sgber mtx_lock(&sc->sc_msi_mtx); 1171240493Sgber 1172240493Sgber for (start = 0; (start + count) < MSI_IRQ_NUM; start++) { 1173240493Sgber for (i = start; i < start + count; i++) { 1174240493Sgber if (isset(&sc->sc_msi_bitmap, i)) 1175240493Sgber break; 1176240493Sgber } 1177240493Sgber if (i == start + count) 1178240493Sgber break; 1179240493Sgber } 1180240493Sgber 1181240493Sgber if ((start + count) == MSI_IRQ_NUM) { 1182240493Sgber mtx_unlock(&sc->sc_msi_mtx); 1183240493Sgber return (ENXIO); 1184240493Sgber } 1185240493Sgber 1186240493Sgber for (i = start; i < start + count; i++) { 1187240493Sgber setbit(&sc->sc_msi_bitmap, i); 1188275583Szbb *irqs++ = MSI_IRQ + i; 1189240493Sgber } 1190240493Sgber debugf("%s: start: %x count: %x\n", __func__, start, count); 1191240493Sgber 1192240493Sgber mtx_unlock(&sc->sc_msi_mtx); 1193240493Sgber return (0); 1194240493Sgber} 1195240493Sgber 1196240493Sgberstatic int 1197240493Sgbermv_pcib_release_msi(device_t dev, device_t child, int count, int *irqs) 1198240493Sgber{ 1199240493Sgber struct mv_pcib_softc *sc; 1200240493Sgber u_int i; 1201240493Sgber 1202240493Sgber sc = device_get_softc(dev); 1203240493Sgber mtx_lock(&sc->sc_msi_mtx); 1204240493Sgber 1205240493Sgber for (i = 0; i < count; i++) 1206240493Sgber clrbit(&sc->sc_msi_bitmap, irqs[i] - MSI_IRQ); 1207240493Sgber 1208240493Sgber mtx_unlock(&sc->sc_msi_mtx); 1209240493Sgber return (0); 1210240493Sgber} 1211240493Sgber#endif 1212260340Sian 1213