gpio.c revision 209131
1/*- 2 * Copyright (c) 2006 Benno Rice. 3 * Copyright (C) 2008 MARVELL INTERNATIONAL LTD. 4 * All rights reserved. 5 * 6 * Adapted and extended for Marvell SoCs by Semihalf. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * from: FreeBSD: //depot/projects/arm/src/sys/arm/xscale/pxa2x0/pxa2x0_gpio.c, rev 1 29 */ 30 31#include <sys/cdefs.h> 32__FBSDID("$FreeBSD: head/sys/arm/mv/gpio.c 209131 2010-06-13 13:28:53Z raj $"); 33 34#include <sys/param.h> 35#include <sys/systm.h> 36#include <sys/bus.h> 37#include <sys/kernel.h> 38#include <sys/lock.h> 39#include <sys/interrupt.h> 40#include <sys/module.h> 41#include <sys/malloc.h> 42#include <sys/mutex.h> 43#include <sys/rman.h> 44#include <sys/queue.h> 45#include <sys/timetc.h> 46#include <machine/bus.h> 47#include <machine/fdt.h> 48#include <machine/intr.h> 49 50#include <dev/fdt/fdt_common.h> 51#include <dev/ofw/ofw_bus.h> 52#include <dev/ofw/ofw_bus_subr.h> 53 54#include <arm/mv/mvvar.h> 55#include <arm/mv/mvreg.h> 56 57#define GPIO_MAX_INTR_COUNT 8 58#define GPIO_PINS_PER_REG 32 59 60struct mv_gpio_softc { 61 struct resource * res[GPIO_MAX_INTR_COUNT + 1]; 62 void *ih_cookie[GPIO_MAX_INTR_COUNT]; 63 bus_space_tag_t bst; 64 bus_space_handle_t bsh; 65 uint8_t pin_num; /* number of GPIO pins */ 66 uint8_t irq_num; /* number of real IRQs occupied by GPIO controller */ 67 uint8_t use_high; 68}; 69 70extern struct resource_spec mv_gpio_res[]; 71 72static struct mv_gpio_softc *mv_gpio_softc = NULL; 73static uint32_t gpio_setup[MV_GPIO_MAX_NPINS]; 74 75static int mv_gpio_probe(device_t); 76static int mv_gpio_attach(device_t); 77static void mv_gpio_intr(void *); 78 79static void mv_gpio_intr_handler(int pin); 80static uint32_t mv_gpio_reg_read(uint32_t reg); 81static void mv_gpio_reg_write(uint32_t reg, uint32_t val); 82static void mv_gpio_reg_set(uint32_t reg, uint32_t val); 83static void mv_gpio_reg_clear(uint32_t reg, uint32_t val); 84 85static void mv_gpio_blink(uint32_t pin, uint8_t enable); 86static void mv_gpio_polarity(uint32_t pin, uint8_t enable); 87static void mv_gpio_level(uint32_t pin, uint8_t enable); 88static void mv_gpio_edge(uint32_t pin, uint8_t enable); 89static void mv_gpio_out_en(uint32_t pin, uint8_t enable); 90static void mv_gpio_int_ack(uint32_t pin); 91static void mv_gpio_value_set(uint32_t pin, uint8_t val); 92static uint32_t mv_gpio_value_get(uint32_t pin); 93 94static device_method_t mv_gpio_methods[] = { 95 DEVMETHOD(device_probe, mv_gpio_probe), 96 DEVMETHOD(device_attach, mv_gpio_attach), 97 { 0, 0 } 98}; 99 100static driver_t mv_gpio_driver = { 101 "gpio", 102 mv_gpio_methods, 103 sizeof(struct mv_gpio_softc), 104}; 105 106static devclass_t mv_gpio_devclass; 107 108DRIVER_MODULE(gpio, simplebus, mv_gpio_driver, mv_gpio_devclass, 0, 0); 109 110typedef int (*gpios_phandler_t)(phandle_t, pcell_t *, int); 111 112struct gpio_ctrl_entry { 113 const char *compat; 114 gpios_phandler_t handler; 115}; 116 117int mv_handle_gpios_prop(phandle_t ctrl, pcell_t *gpios, int len); 118int gpio_get_config_from_dt(void); 119 120struct gpio_ctrl_entry gpio_controllers[] = { 121 { "mrvl,gpio", &mv_handle_gpios_prop }, 122 { NULL, NULL } 123}; 124 125static int 126mv_gpio_probe(device_t dev) 127{ 128 129 if (!ofw_bus_is_compatible(dev, "mrvl,gpio")) 130 return (ENXIO); 131 132 device_set_desc(dev, "Marvell Integrated GPIO Controller"); 133 return (0); 134} 135 136static int 137mv_gpio_attach(device_t dev) 138{ 139 int error, i; 140 struct mv_gpio_softc *sc; 141 uint32_t dev_id, rev_id; 142 143 sc = (struct mv_gpio_softc *)device_get_softc(dev); 144 145 if (sc == NULL) 146 return (ENXIO); 147 148 mv_gpio_softc = sc; 149 150 /* Get chip id and revision */ 151 soc_id(&dev_id, &rev_id); 152 153 if (dev_id == MV_DEV_88F5182 || 154 dev_id == MV_DEV_88F5281 || 155 dev_id == MV_DEV_MV78100 || 156 dev_id == MV_DEV_MV78100_Z0 ) { 157 sc->pin_num = 32; 158 sc->irq_num = 4; 159 sc->use_high = 0; 160 161 } else if (dev_id == MV_DEV_88F6281) { 162 sc->pin_num = 50; 163 sc->irq_num = 7; 164 sc->use_high = 1; 165 166 } else { 167 device_printf(dev, "unknown chip id=0x%x\n", dev_id); 168 return (ENXIO); 169 } 170 171 error = bus_alloc_resources(dev, mv_gpio_res, sc->res); 172 if (error) { 173 device_printf(dev, "could not allocate resources\n"); 174 return (ENXIO); 175 } 176 177 sc->bst = rman_get_bustag(sc->res[0]); 178 sc->bsh = rman_get_bushandle(sc->res[0]); 179 180 /* Disable and clear all interrupts */ 181 bus_space_write_4(sc->bst, sc->bsh, GPIO_INT_EDGE_MASK, 0); 182 bus_space_write_4(sc->bst, sc->bsh, GPIO_INT_LEV_MASK, 0); 183 bus_space_write_4(sc->bst, sc->bsh, GPIO_INT_CAUSE, 0); 184 185 if (sc->use_high) { 186 bus_space_write_4(sc->bst, sc->bsh, 187 GPIO_HI_INT_EDGE_MASK, 0); 188 bus_space_write_4(sc->bst, sc->bsh, 189 GPIO_HI_INT_LEV_MASK, 0); 190 bus_space_write_4(sc->bst, sc->bsh, 191 GPIO_HI_INT_CAUSE, 0); 192 } 193 194 for (i = 0; i < sc->irq_num; i++) { 195 if (bus_setup_intr(dev, sc->res[1 + i], 196 INTR_TYPE_MISC | INTR_FAST, 197 (driver_filter_t *)mv_gpio_intr, NULL, 198 sc, &sc->ih_cookie[i]) != 0) { 199 bus_release_resources(dev, mv_gpio_res, sc->res); 200 device_printf(dev, "could not set up intr %d\n", i); 201 return (ENXIO); 202 } 203 } 204 205 /* 206 * GPIO lines setup is already done at this stage (see mv_machdep.c). 207 */ 208 return (0); 209} 210 211static void 212mv_gpio_intr(void *arg) 213{ 214 uint32_t int_cause, gpio_val; 215 uint32_t int_cause_hi, gpio_val_hi = 0; 216 int i; 217 218 int_cause = mv_gpio_reg_read(GPIO_INT_CAUSE); 219 gpio_val = mv_gpio_reg_read(GPIO_DATA_IN); 220 gpio_val &= int_cause; 221 if (mv_gpio_softc->use_high) { 222 int_cause_hi = mv_gpio_reg_read(GPIO_HI_INT_CAUSE); 223 gpio_val_hi = mv_gpio_reg_read(GPIO_HI_DATA_IN); 224 gpio_val_hi &= int_cause_hi; 225 } 226 227 i = 0; 228 while (gpio_val != 0) { 229 if (gpio_val & 1) 230 mv_gpio_intr_handler(i); 231 gpio_val >>= 1; 232 i++; 233 } 234 235 if (mv_gpio_softc->use_high) { 236 i = 0; 237 while (gpio_val_hi != 0) { 238 if (gpio_val_hi & 1) 239 mv_gpio_intr_handler(i + GPIO_PINS_PER_REG); 240 gpio_val_hi >>= 1; 241 i++; 242 } 243 } 244} 245 246/* 247 * GPIO interrupt handling 248 */ 249 250static struct intr_event *gpio_events[MV_GPIO_MAX_NPINS]; 251 252int 253mv_gpio_setup_intrhandler(const char *name, driver_filter_t *filt, 254 void (*hand)(void *), void *arg, int pin, int flags, void **cookiep) 255{ 256 struct intr_event *event; 257 int error; 258 259 if (pin < 0 || pin >= mv_gpio_softc->pin_num) 260 return (ENXIO); 261 event = gpio_events[pin]; 262 if (event == NULL) { 263 error = intr_event_create(&event, (void *)pin, 0, pin, 264 (void (*)(void *))mv_gpio_intr_mask, 265 (void (*)(void *))mv_gpio_intr_unmask, 266 (void (*)(void *))mv_gpio_int_ack, 267 NULL, 268 "gpio%d:", pin); 269 if (error != 0) 270 return (error); 271 gpio_events[pin] = event; 272 } 273 274 intr_event_add_handler(event, name, filt, hand, arg, 275 intr_priority(flags), flags, cookiep); 276 return (0); 277} 278 279void 280mv_gpio_intr_mask(int pin) 281{ 282 283 if (pin >= mv_gpio_softc->pin_num) 284 return; 285 286 if (gpio_setup[pin] & MV_GPIO_IN_IRQ_EDGE) 287 mv_gpio_edge(pin, 0); 288 else 289 mv_gpio_level(pin, 0); 290} 291 292void 293mv_gpio_intr_unmask(int pin) 294{ 295 296 if (pin >= mv_gpio_softc->pin_num) 297 return; 298 299 if (gpio_setup[pin] & MV_GPIO_IN_IRQ_EDGE) 300 mv_gpio_edge(pin, 1); 301 else 302 mv_gpio_level(pin, 1); 303} 304 305static void 306mv_gpio_intr_handler(int pin) 307{ 308 struct intr_event *event; 309 310 event = gpio_events[pin]; 311 if (event == NULL || TAILQ_EMPTY(&event->ie_handlers)) 312 return; 313 314 intr_event_handle(event, NULL); 315} 316 317static int 318mv_gpio_configure(uint32_t pin, uint32_t flags) 319{ 320 321 if (pin >= mv_gpio_softc->pin_num) 322 return (EINVAL); 323 324 if (flags & MV_GPIO_OUT_BLINK) 325 mv_gpio_blink(pin, 1); 326 if (flags & MV_GPIO_IN_POL_LOW) 327 mv_gpio_polarity(pin, 1); 328 if (flags & MV_GPIO_IN_IRQ_EDGE) 329 mv_gpio_edge(pin, 1); 330 if (flags & MV_GPIO_IN_IRQ_LEVEL) 331 mv_gpio_level(pin, 1); 332 333 gpio_setup[pin] = flags; 334 335 return (0); 336} 337 338void 339mv_gpio_out(uint32_t pin, uint8_t val, uint8_t enable) 340{ 341 342 mv_gpio_value_set(pin, val); 343 mv_gpio_out_en(pin, enable); 344} 345 346uint8_t 347mv_gpio_in(uint32_t pin) 348{ 349 350 return (mv_gpio_value_get(pin)); 351} 352 353static uint32_t 354mv_gpio_reg_read(uint32_t reg) 355{ 356 357 return (bus_space_read_4(mv_gpio_softc->bst, 358 mv_gpio_softc->bsh, reg)); 359} 360 361static void 362mv_gpio_reg_write(uint32_t reg, uint32_t val) 363{ 364 365 bus_space_write_4(mv_gpio_softc->bst, 366 mv_gpio_softc->bsh, reg, val); 367} 368 369static void 370mv_gpio_reg_set(uint32_t reg, uint32_t pin) 371{ 372 uint32_t reg_val; 373 374 reg_val = mv_gpio_reg_read(reg); 375 reg_val |= GPIO(pin); 376 mv_gpio_reg_write(reg, reg_val); 377} 378 379static void 380mv_gpio_reg_clear(uint32_t reg, uint32_t pin) 381{ 382 uint32_t reg_val; 383 384 reg_val = mv_gpio_reg_read(reg); 385 reg_val &= ~(GPIO(pin)); 386 mv_gpio_reg_write(reg, reg_val); 387} 388 389static void 390mv_gpio_out_en(uint32_t pin, uint8_t enable) 391{ 392 uint32_t reg; 393 394 if (pin >= mv_gpio_softc->pin_num) 395 return; 396 397 if (pin >= GPIO_PINS_PER_REG) { 398 reg = GPIO_HI_DATA_OUT_EN_CTRL; 399 pin -= GPIO_PINS_PER_REG; 400 } else 401 reg = GPIO_DATA_OUT_EN_CTRL; 402 403 if (enable) 404 mv_gpio_reg_clear(reg, pin); 405 else 406 mv_gpio_reg_set(reg, pin); 407} 408 409static void 410mv_gpio_blink(uint32_t pin, uint8_t enable) 411{ 412 uint32_t reg; 413 414 if (pin >= mv_gpio_softc->pin_num) 415 return; 416 417 if (pin >= GPIO_PINS_PER_REG) { 418 reg = GPIO_HI_BLINK_EN; 419 pin -= GPIO_PINS_PER_REG; 420 } else 421 reg = GPIO_BLINK_EN; 422 423 if (enable) 424 mv_gpio_reg_set(reg, pin); 425 else 426 mv_gpio_reg_clear(reg, pin); 427} 428 429static void 430mv_gpio_polarity(uint32_t pin, uint8_t enable) 431{ 432 uint32_t reg; 433 434 if (pin >= mv_gpio_softc->pin_num) 435 return; 436 437 if (pin >= GPIO_PINS_PER_REG) { 438 reg = GPIO_HI_DATA_IN_POLAR; 439 pin -= GPIO_PINS_PER_REG; 440 } else 441 reg = GPIO_DATA_IN_POLAR; 442 443 if (enable) 444 mv_gpio_reg_set(reg, pin); 445 else 446 mv_gpio_reg_clear(reg, pin); 447} 448 449static void 450mv_gpio_level(uint32_t pin, uint8_t enable) 451{ 452 uint32_t reg; 453 454 if (pin >= mv_gpio_softc->pin_num) 455 return; 456 457 if (pin >= GPIO_PINS_PER_REG) { 458 reg = GPIO_HI_INT_LEV_MASK; 459 pin -= GPIO_PINS_PER_REG; 460 } else 461 reg = GPIO_INT_LEV_MASK; 462 463 if (enable) 464 mv_gpio_reg_set(reg, pin); 465 else 466 mv_gpio_reg_clear(reg, pin); 467} 468 469static void 470mv_gpio_edge(uint32_t pin, uint8_t enable) 471{ 472 uint32_t reg; 473 474 if (pin >= mv_gpio_softc->pin_num) 475 return; 476 477 if (pin >= GPIO_PINS_PER_REG) { 478 reg = GPIO_HI_INT_EDGE_MASK; 479 pin -= GPIO_PINS_PER_REG; 480 } else 481 reg = GPIO_INT_EDGE_MASK; 482 483 if (enable) 484 mv_gpio_reg_set(reg, pin); 485 else 486 mv_gpio_reg_clear(reg, pin); 487} 488 489static void 490mv_gpio_int_ack(uint32_t pin) 491{ 492 uint32_t reg; 493 494 if (pin >= mv_gpio_softc->pin_num) 495 return; 496 497 if (pin >= GPIO_PINS_PER_REG) { 498 reg = GPIO_HI_INT_CAUSE; 499 pin -= GPIO_PINS_PER_REG; 500 } else 501 reg = GPIO_INT_CAUSE; 502 503 mv_gpio_reg_clear(reg, pin); 504} 505 506static uint32_t 507mv_gpio_value_get(uint32_t pin) 508{ 509 uint32_t reg, reg_val; 510 511 if (pin >= mv_gpio_softc->pin_num) 512 return (0); 513 514 if (pin >= GPIO_PINS_PER_REG) { 515 reg = GPIO_HI_DATA_IN; 516 pin -= GPIO_PINS_PER_REG; 517 } else 518 reg = GPIO_DATA_IN; 519 520 reg_val = mv_gpio_reg_read(reg); 521 522 return (reg_val & GPIO(pin)); 523} 524 525static void 526mv_gpio_value_set(uint32_t pin, uint8_t val) 527{ 528 uint32_t reg; 529 530 if (pin >= mv_gpio_softc->pin_num) 531 return; 532 533 if (pin >= GPIO_PINS_PER_REG) { 534 reg = GPIO_HI_DATA_OUT; 535 pin -= GPIO_PINS_PER_REG; 536 } else 537 reg = GPIO_DATA_OUT; 538 539 if (val) 540 mv_gpio_reg_set(reg, pin); 541 else 542 mv_gpio_reg_clear(reg, pin); 543} 544 545int 546mv_handle_gpios_prop(phandle_t ctrl, pcell_t *gpios, int len) 547{ 548 pcell_t gpio_cells, pincnt; 549 int inc, t, tuples, tuple_size; 550 int dir, flags, pin; 551 u_long gpio_ctrl, size; 552 struct mv_gpio_softc sc; 553 554 pincnt = 0; 555 if (OF_getproplen(ctrl, "gpio-controller") <= 0) 556 /* Node is not a GPIO controller. */ 557 return (ENXIO); 558 559 if (OF_getprop(ctrl, "#gpio-cells", &gpio_cells, sizeof(pcell_t)) < 0) 560 return (ENXIO); 561 562 gpio_cells = fdt32_to_cpu(gpio_cells); 563 if (gpio_cells != 3) 564 return (ENXIO); 565 566 tuple_size = gpio_cells * sizeof(pcell_t) + sizeof(phandle_t); 567 tuples = len / tuple_size; 568 569 if (fdt_regsize(ctrl, &gpio_ctrl, &size)) 570 return (ENXIO); 571 /* 572 * Since to set up GPIO we use the same functions as GPIO driver, and 573 * mv_gpio_softc is NULL at this early stage, we need to create a fake 574 * softc and set mv_gpio_softc pointer to that newly created object. 575 * After successful GPIO setup, the [shared] pointer will be set back 576 * to NULL. 577 */ 578 mv_gpio_softc = ≻ 579 580 sc.bst = fdtbus_bs_tag; 581 gpio_ctrl += fdt_immr_va; 582 583 if (bus_space_map(sc.bst, gpio_ctrl, size, 0, &sc.bsh) != 0) 584 return (ENXIO); 585 586 if (OF_getprop(ctrl, "pin-count", &pincnt, sizeof(pcell_t)) < 0) 587 return (ENXIO); 588 sc.pin_num = fdt32_to_cpu(pincnt); 589 590 /* 591 * Skip controller reference, since controller's phandle is given 592 * explicitly (in a function argument). 593 */ 594 inc = sizeof(ihandle_t) / sizeof(pcell_t); 595 gpios += inc; 596 597 for (t = 0; t < tuples; t++) { 598 pin = fdt32_to_cpu(gpios[0]); 599 dir = fdt32_to_cpu(gpios[1]); 600 flags = fdt32_to_cpu(gpios[2]); 601 602 mv_gpio_configure(pin, flags); 603 604 if (dir == 1) 605 /* Input. */ 606 mv_gpio_out_en(pin, 0); 607 else { 608 /* Output. */ 609 if (flags & MV_GPIO_OUT_OPEN_DRAIN) 610 mv_gpio_out(pin, 0, 1); 611 612 if (flags & MV_GPIO_OUT_OPEN_SRC) 613 mv_gpio_out(pin, 1, 1); 614 } 615 gpios += gpio_cells + inc; 616 } 617 618 /* Reset pointer. */ 619 mv_gpio_softc = NULL; 620 return (0); 621} 622 623#define MAX_PINS_PER_NODE 5 624#define GPIOS_PROP_CELLS 4 625int 626platform_gpio_init(void) 627{ 628 phandle_t child, parent, root, ctrl; 629 ihandle_t ctrl_ihandle; 630 pcell_t gpios[MAX_PINS_PER_NODE * GPIOS_PROP_CELLS]; 631 struct gpio_ctrl_entry *e; 632 int len, rv; 633 634 root = OF_finddevice("/"); 635 len = 0; 636 parent = root; 637 638 /* Traverse through entire tree to find nodes with 'gpios' prop */ 639 for (child = OF_child(parent); child != 0; child = OF_peer(child)) { 640 641 /* Find a 'leaf'. Start the search from this node. */ 642 while (OF_child(child)) { 643 parent = child; 644 child = OF_child(child); 645 } 646 if ((len = OF_getproplen(child, "gpios")) > 0) { 647 648 if (len > sizeof(gpios)) 649 return (ENXIO); 650 651 /* Get 'gpios' property. */ 652 OF_getprop(child, "gpios", &gpios, len); 653 654 e = (struct gpio_ctrl_entry *)&gpio_controllers; 655 656 /* Find and call a handler. */ 657 for (; e->compat; e++) { 658 /* 659 * First cell of 'gpios' property should 660 * contain a ref. to a node defining GPIO 661 * controller. 662 */ 663 ctrl_ihandle = (ihandle_t)gpios[0]; 664 ctrl_ihandle = fdt32_to_cpu(ctrl_ihandle); 665 ctrl = OF_instance_to_package(ctrl_ihandle); 666 667 if (fdt_is_compatible(ctrl, e->compat)) 668 /* Call a handler. */ 669 if ((rv = e->handler(ctrl, 670 (pcell_t *)&gpios, len))) 671 return (rv); 672 } 673 } 674 675 if (OF_peer(child) == 0) { 676 /* No more siblings. */ 677 child = parent; 678 parent = OF_parent(child); 679 } 680 } 681 return (0); 682} 683