discovery.c revision 194072
1/*- 2 * Copyright (C) 2008 MARVELL INTERNATIONAL LTD. 3 * All rights reserved. 4 * 5 * Developed by Semihalf. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. Neither the name of MARVELL nor the names of contributors 16 * may be used to endorse or promote products derived from this software 17 * without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 */ 31 32#include <sys/cdefs.h> 33__FBSDID("$FreeBSD: head/sys/arm/mv/discovery/discovery.c 194072 2009-06-12 20:00:38Z marcel $"); 34 35#include <sys/param.h> 36#include <sys/systm.h> 37#include <sys/bus.h> 38 39#include <machine/bus.h> 40 41#include <arm/mv/mvreg.h> 42#include <arm/mv/mvvar.h> 43#include <arm/mv/mvwin.h> 44 45#define _MV_PCIE_MAX_PORT 8 46 47#define _MV_PCIE_IO_SIZE (MV_PCIE_IO_SIZE / _MV_PCIE_MAX_PORT) 48#define _MV_PCIE_MEM_SIZE (MV_PCIE_MEM_SIZE / _MV_PCIE_MAX_PORT) 49 50#define _MV_PCIE_IO(n) (MV_PCIE_IO_BASE + ((n) * _MV_PCIE_IO_SIZE)) 51#define _MV_PCIE_MEM(n) (MV_PCIE_MEM_BASE + ((n) * _MV_PCIE_MEM_SIZE)) 52 53#define _MV_PCIE_IO_PHYS(n) (MV_PCIE_IO_PHYS_BASE + ((n) * _MV_PCIE_IO_SIZE)) 54#define _MV_PCIE_MEM_PHYS(n) (MV_PCIE_MEM_PHYS_BASE + ((n) * _MV_PCIE_MEM_SIZE)) 55 56/* 57 * Note the 'pcib' devices are not declared in the obio_devices[]: due to the 58 * much more complex configuration schemes allowed, specifically of the 59 * PCI-Express (multiple lanes width per port configured dynamically etc.) it 60 * is better and flexible to instantiate the number of PCI bridge devices 61 * (known in run-time) in the pcib_mbus_identify() method. 62 */ 63struct obio_device obio_devices[] = { 64 { "ic", MV_IC_BASE, MV_IC_SIZE, 65 { -1 }, 66 { -1 }, 67 CPU_PM_CTRL_NONE 68 }, 69 { "timer", MV_TIMERS_BASE, MV_TIMERS_SIZE, 70 { MV_INT_TIMER0, -1 }, 71 { -1 }, 72 CPU_PM_CTRL_NONE 73 }, 74 { "gpio", MV_GPIO_BASE, MV_GPIO_SIZE, 75 { MV_INT_GPIO7_0, MV_INT_GPIO15_8, 76 MV_INT_GPIO23_16, MV_INT_GPIO31_24, -1 }, 77 { -1 }, 78 CPU_PM_CTRL_NONE 79 }, 80 { "uart", MV_UART0_BASE, MV_UART_SIZE, 81 { MV_INT_UART0, -1 }, 82 { -1 }, 83 CPU_PM_CTRL_NONE 84 }, 85 { "uart", MV_UART1_BASE, MV_UART_SIZE, 86 { MV_INT_UART1, -1 }, 87 { -1 }, 88 CPU_PM_CTRL_NONE 89 }, 90 { "idma", MV_IDMA_BASE, MV_IDMA_SIZE, 91 { MV_INT_IDMA_ERR, MV_INT_IDMA0, MV_INT_IDMA1, 92 MV_INT_IDMA2, MV_INT_IDMA3, -1 }, 93 { -1 }, 94 CPU_PM_CTRL_IDMA 95 }, 96 { "xor", MV_XOR_BASE, MV_XOR_SIZE, 97 { MV_INT_XOR0, MV_INT_XOR1, 98 MV_INT_XOR_ERR, -1 }, 99 { -1 }, 100 CPU_PM_CTRL_XOR 101 }, 102 { "ehci", MV_USB0_BASE, MV_USB_SIZE, 103 { MV_INT_USB_ERR, MV_INT_USB0, -1 }, 104 { -1 }, 105 CPU_PM_CTRL_USB0 | CPU_PM_CTRL_USB1 | CPU_PM_CTRL_USB2 106 }, 107 { "ehci", MV_USB1_BASE, MV_USB_SIZE, 108 { MV_INT_USB_ERR, MV_INT_USB1, -1 }, 109 { -1 }, 110 CPU_PM_CTRL_USB0 | CPU_PM_CTRL_USB1 | CPU_PM_CTRL_USB2 111 }, 112 { "ehci", MV_USB2_BASE, MV_USB_SIZE, 113 { MV_INT_USB_ERR, MV_INT_USB2, -1 }, 114 { -1 }, 115 CPU_PM_CTRL_USB0 | CPU_PM_CTRL_USB1 | CPU_PM_CTRL_USB2 116 }, 117 { "mge", MV_ETH0_BASE, MV_ETH_SIZE, 118 { MV_INT_GBERX, MV_INT_GBETX, MV_INT_GBEMISC, 119 MV_INT_GBESUM, MV_INT_GBE_ERR, -1 }, 120 { -1 }, 121 CPU_PM_CTRL_GE0 122 }, 123 { "mge", MV_ETH1_BASE, MV_ETH_SIZE, 124 { MV_INT_GBE1RX, MV_INT_GBE1TX, MV_INT_GBE1MISC, 125 MV_INT_GBE1SUM, MV_INT_GBE_ERR, -1 }, 126 { -1 }, 127 CPU_PM_CTRL_GE1 128 }, 129 { "twsi", MV_TWSI_BASE, MV_TWSI_SIZE, 130 { -1 }, { -1 }, 131 CPU_PM_CTRL_NONE 132 }, 133 { NULL, 0, 0, { 0 }, { 0 }, 0 } 134}; 135 136const struct obio_pci mv_pci_info[] = { 137 { MV_TYPE_PCIE, 138 MV_PCIE00_BASE, MV_PCIE_SIZE, 139 _MV_PCIE_IO(0), _MV_PCIE_IO_SIZE, 4, 0xE0, 140 _MV_PCIE_MEM(0), _MV_PCIE_MEM_SIZE, 4, 0xE8, 141 NULL, MV_INT_PEX00 }, 142 143 { MV_TYPE_PCIE_AGGR_LANE, 144 MV_PCIE01_BASE, MV_PCIE_SIZE, 145 _MV_PCIE_IO(1), _MV_PCIE_IO_SIZE, 4, 0xD0, 146 _MV_PCIE_MEM(1), _MV_PCIE_MEM_SIZE, 4, 0xD8, 147 NULL, MV_INT_PEX01 }, 148#if 0 149 /* 150 * XXX Access to devices on this interface (PCIE 0.2) crashes the 151 * system. Could be a silicon defect as Marvell U-Boot has a 'Do not 152 * touch' precaution comment... 153 */ 154 { MV_TYPE_PCIE_AGGR_LANE, 155 MV_PCIE02_BASE, MV_PCIE_SIZE, 156 _MV_PCIE_IO(2), _MV_PCIE_IO_SIZE(2), 4, 0xB0, 157 _MV_PCIE_MEM(2), _MV_PCIE_MEM_SIZE(2), 4, 0xB8, 158 NULL, MV_INT_PEX02 }, 159#endif 160 { MV_TYPE_PCIE_AGGR_LANE, 161 MV_PCIE03_BASE, MV_PCIE_SIZE, 162 _MV_PCIE_IO(3), _MV_PCIE_IO_SIZE, 4, 0x70, 163 _MV_PCIE_MEM(3), _MV_PCIE_MEM_SIZE, 4, 0x78, 164 NULL, MV_INT_PEX03 }, 165 166 { MV_TYPE_PCIE, 167 MV_PCIE10_BASE, MV_PCIE_SIZE, 168 _MV_PCIE_IO(4), _MV_PCIE_IO_SIZE, 8, 0xE0, 169 _MV_PCIE_MEM(4), _MV_PCIE_MEM_SIZE, 8, 0xE8, 170 NULL, MV_INT_PEX10 }, 171 172 { MV_TYPE_PCIE_AGGR_LANE, 173 MV_PCIE11_BASE, MV_PCIE_SIZE, 174 _MV_PCIE_IO(5), _MV_PCIE_IO_SIZE, 8, 0xD0, 175 _MV_PCIE_MEM(5), _MV_PCIE_MEM_SIZE, 8, 0xD8, 176 NULL, MV_INT_PEX11 }, 177 { MV_TYPE_PCIE_AGGR_LANE, 178 MV_PCIE12_BASE, MV_PCIE_SIZE, 179 _MV_PCIE_IO(6), _MV_PCIE_IO_SIZE, 8, 0xB0, 180 _MV_PCIE_MEM(6), _MV_PCIE_MEM_SIZE, 8, 0xB8, 181 NULL, MV_INT_PEX12 }, 182 { MV_TYPE_PCIE_AGGR_LANE, 183 MV_PCIE13_BASE, MV_PCIE_SIZE, 184 _MV_PCIE_IO(7), _MV_PCIE_IO_SIZE, 8, 0x70, 185 _MV_PCIE_MEM(7), _MV_PCIE_MEM_SIZE, 8, 0x78, 186 NULL, MV_INT_PEX13 }, 187 188 { 0, 0, 0 } 189}; 190 191struct resource_spec mv_gpio_res[] = { 192 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 193 { SYS_RES_IRQ, 0, RF_ACTIVE }, 194 { SYS_RES_IRQ, 1, RF_ACTIVE }, 195 { SYS_RES_IRQ, 2, RF_ACTIVE }, 196 { SYS_RES_IRQ, 3, RF_ACTIVE }, 197 { -1, 0 } 198}; 199 200struct resource_spec mv_xor_res[] = { 201 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 202 { SYS_RES_IRQ, 0, RF_ACTIVE }, 203 { SYS_RES_IRQ, 1, RF_ACTIVE }, 204 { SYS_RES_IRQ, 2, RF_ACTIVE }, 205 { -1, 0 } 206}; 207 208const struct decode_win cpu_win_tbl[] = { 209 /* Device bus BOOT */ 210 { 1, 0x2f, MV_DEV_BOOT_PHYS_BASE, MV_DEV_BOOT_SIZE, -1 }, 211 212 /* Device bus CS0 */ 213 { 1, 0x3e, MV_DEV_CS0_PHYS_BASE, MV_DEV_CS0_SIZE, -1 }, 214 215 /* Device bus CS1 */ 216 { 1, 0x3d, MV_DEV_CS1_PHYS_BASE, MV_DEV_CS1_SIZE, -1 }, 217 218 /* Device bus CS2 */ 219 { 1, 0x3b, MV_DEV_CS2_PHYS_BASE, MV_DEV_CS2_SIZE, -1 }, 220 221 /* CESA */ 222 { 9, 0x01, MV_CESA_SRAM_PHYS_BASE, MV_CESA_SRAM_SIZE, -1 }, 223}; 224const struct decode_win *cpu_wins = cpu_win_tbl; 225int cpu_wins_no = sizeof(cpu_win_tbl) / sizeof(struct decode_win); 226 227/* 228 * Note: the decode windows table for IDMA does not explicitly have DRAM 229 * entries, which are not statically defined: active DDR banks (== windows) 230 * are established in run time from actual DDR windows settings. All active 231 * DDR banks are mapped into IDMA decode windows, so at least one IDMA decode 232 * window is occupied by the DDR bank; in case when all (MV_WIN_DDR_MAX) 233 * DDR banks are active, the remaining available IDMA decode windows for other 234 * targets is only MV_WIN_IDMA_MAX - MV_WIN_DDR_MAX. 235 */ 236const struct decode_win idma_win_tbl[] = { 237 /* PCIE MEM */ 238 { 4, 0xE8, _MV_PCIE_MEM_PHYS(0), _MV_PCIE_MEM_SIZE, -1 }, 239 { 4, 0xD8, _MV_PCIE_MEM_PHYS(1), _MV_PCIE_MEM_SIZE, -1 }, 240}; 241const struct decode_win *idma_wins = idma_win_tbl; 242int idma_wins_no = sizeof(idma_win_tbl) / sizeof(struct decode_win); 243 244const struct decode_win xor_win_tbl[] = { 245 /* PCIE MEM */ 246 { 4, 0xE8, _MV_PCIE_MEM_PHYS(0), _MV_PCIE_MEM_SIZE, -1}, 247 { 4, 0xD8, _MV_PCIE_MEM_PHYS(1), _MV_PCIE_MEM_SIZE, -1}, 248}; 249const struct decode_win *xor_wins = xor_win_tbl; 250int xor_wins_no = sizeof(xor_win_tbl) / sizeof(struct decode_win); 251 252uint32_t 253get_tclk(void) 254{ 255 uint32_t sar; 256 257 /* 258 * On Discovery TCLK is can be configured to 166 MHz or 200 MHz. 259 * Current setting is read from Sample At Reset register. 260 */ 261 sar = bus_space_read_4(obio_tag, MV_MPP_BASE, SAMPLE_AT_RESET_HI); 262 sar = (sar & TCLK_MASK) >> TCLK_SHIFT; 263 264 switch (sar) { 265 case 0: 266 return (TCLK_166MHZ); 267 case 1: 268 return (TCLK_200MHZ); 269 default: 270 panic("Unknown TCLK settings!"); 271 } 272} 273