discovery.c revision 185089
1/*- 2 * Copyright (C) 2008 MARVELL INTERNATIONAL LTD. 3 * All rights reserved. 4 * 5 * Developed by Semihalf. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. Neither the name of MARVELL nor the names of contributors 16 * may be used to endorse or promote products derived from this software 17 * without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 */ 31 32#include <sys/cdefs.h> 33__FBSDID("$FreeBSD: head/sys/arm/mv/discovery/discovery.c 185089 2008-11-19 11:30:44Z raj $"); 34 35#include <sys/param.h> 36#include <sys/systm.h> 37#include <sys/bus.h> 38 39#include <machine/bus.h> 40 41#include <arm/mv/mvreg.h> 42#include <arm/mv/mvvar.h> 43 44#define _MV_PCIE_MAX_PORT 8 45 46#define _MV_PCIE_IO_SIZE (MV_PCIE_IO_SIZE / _MV_PCIE_MAX_PORT) 47#define _MV_PCIE_MEM_SIZE (MV_PCIE_MEM_SIZE / _MV_PCIE_MAX_PORT) 48 49#define _MV_PCIE_IO(n) (MV_PCIE_IO_BASE + ((n) * _MV_PCIE_IO_SIZE)) 50#define _MV_PCIE_MEM(n) (MV_PCIE_MEM_BASE + ((n) * _MV_PCIE_MEM_SIZE)) 51 52#define _MV_PCIE_IO_PHYS(n) (MV_PCIE_IO_PHYS_BASE + ((n) * _MV_PCIE_IO_SIZE)) 53#define _MV_PCIE_MEM_PHYS(n) (MV_PCIE_MEM_PHYS_BASE + ((n) * _MV_PCIE_MEM_SIZE)) 54 55/* 56 * Note the 'pcib' devices are not declared in the obio_devices[]: due to the 57 * much more complex configuration schemes allowed, specifically of the 58 * PCI-Express (multiple lanes width per port configured dynamically etc.) it 59 * is better and flexible to instantiate the number of PCI bridge devices 60 * (known in run-time) in the pcib_mbus_identify() method. 61 */ 62struct obio_device obio_devices[] = { 63 { "ic", MV_IC_BASE, MV_IC_SIZE, 64 { -1 }, 65 { -1 }, 66 CPU_PM_CTRL_NONE 67 }, 68 { "timer", MV_TIMERS_BASE, MV_TIMERS_SIZE, 69 { MV_INT_TIMER0, -1 }, 70 { -1 }, 71 CPU_PM_CTRL_NONE 72 }, 73 { "gpio", MV_GPIO_BASE, MV_GPIO_SIZE, 74 { MV_INT_GPIO7_0, MV_INT_GPIO15_8, 75 MV_INT_GPIO23_16, MV_INT_GPIO31_24, -1 }, 76 { -1 }, 77 CPU_PM_CTRL_NONE 78 }, 79 { "uart", MV_UART0_BASE, MV_UART_SIZE, 80 { MV_INT_UART0, -1 }, 81 { -1 }, 82 CPU_PM_CTRL_NONE 83 }, 84 { "uart", MV_UART1_BASE, MV_UART_SIZE, 85 { MV_INT_UART1, -1 }, 86 { -1 }, 87 CPU_PM_CTRL_NONE 88 }, 89 { "idma", MV_IDMA_BASE, MV_IDMA_SIZE, 90 { MV_INT_IDMA_ERR, MV_INT_IDMA0, MV_INT_IDMA1, 91 MV_INT_IDMA2, MV_INT_IDMA3, -1 }, 92 { -1 }, 93 CPU_PM_CTRL_IDMA 94 }, 95 { "xor", MV_XOR_BASE, MV_XOR_SIZE, 96 { MV_INT_XOR0, MV_INT_XOR1, 97 MV_INT_XOR_ERR, -1 }, 98 { -1 }, 99 CPU_PM_CTRL_XOR 100 }, 101 { "ehci", MV_USB0_BASE, MV_USB_SIZE, 102 { MV_INT_USB_ERR, MV_INT_USB0, -1 }, 103 { -1 }, 104 CPU_PM_CTRL_USB0 | CPU_PM_CTRL_USB1 | CPU_PM_CTRL_USB2 105 }, 106 { "mge", MV_ETH0_BASE, MV_ETH_SIZE, 107 { MV_INT_GBERX, MV_INT_GBETX, MV_INT_GBEMISC, 108 MV_INT_GBESUM, MV_INT_GBE_ERR, -1 }, 109 { -1 }, 110 CPU_PM_CTRL_GE0 111 }, 112 { "mge", MV_ETH1_BASE, MV_ETH_SIZE, 113 { MV_INT_GBE1RX, MV_INT_GBE1TX, MV_INT_GBE1MISC, 114 MV_INT_GBE1SUM, MV_INT_GBE_ERR, -1 }, 115 { -1 }, 116 CPU_PM_CTRL_GE1 117 }, 118 { "twsi", MV_TWSI_BASE, MV_TWSI_SIZE, 119 { -1 }, { -1 }, 120 CPU_PM_CTRL_NONE 121 }, 122 { NULL, 0, 0, { 0 }, { 0 }, 0 } 123}; 124 125const struct obio_pci mv_pci_info[] = { 126 { MV_TYPE_PCIE, 127 MV_PCIE00_BASE, MV_PCIE_SIZE, 128 _MV_PCIE_IO(0), _MV_PCIE_IO_SIZE, 4, 0xE0, 129 _MV_PCIE_MEM(0), _MV_PCIE_MEM_SIZE, 4, 0xE8, 130 NULL, MV_INT_PEX00 }, 131 132 { MV_TYPE_PCIE_AGGR_LANE, 133 MV_PCIE01_BASE, MV_PCIE_SIZE, 134 _MV_PCIE_IO(1), _MV_PCIE_IO_SIZE, 4, 0xD0, 135 _MV_PCIE_MEM(1), _MV_PCIE_MEM_SIZE, 4, 0xD8, 136 NULL, MV_INT_PEX01 }, 137#if 0 138 /* 139 * XXX Access to devices on this interface (PCIE 0.2) crashes the 140 * system. Could be a silicon defect as Marvell U-Boot has a 'Do not 141 * touch' precaution comment... 142 */ 143 { MV_TYPE_PCIE_AGGR_LANE, 144 MV_PCIE02_BASE, MV_PCIE_SIZE, 145 _MV_PCIE_IO(2), _MV_PCIE_IO_SIZE(2), 4, 0xB0, 146 _MV_PCIE_MEM(2), _MV_PCIE_MEM_SIZE(2), 4, 0xB8, 147 NULL, MV_INT_PEX02 }, 148#endif 149 { MV_TYPE_PCIE_AGGR_LANE, 150 MV_PCIE03_BASE, MV_PCIE_SIZE, 151 _MV_PCIE_IO(3), _MV_PCIE_IO_SIZE, 4, 0x70, 152 _MV_PCIE_MEM(3), _MV_PCIE_MEM_SIZE, 4, 0x78, 153 NULL, MV_INT_PEX03 }, 154 155 { MV_TYPE_PCIE, 156 MV_PCIE10_BASE, MV_PCIE_SIZE, 157 _MV_PCIE_IO(4), _MV_PCIE_IO_SIZE, 8, 0xE0, 158 _MV_PCIE_MEM(4), _MV_PCIE_MEM_SIZE, 8, 0xE8, 159 NULL, MV_INT_PEX10 }, 160 161 { MV_TYPE_PCIE_AGGR_LANE, 162 MV_PCIE11_BASE, MV_PCIE_SIZE, 163 _MV_PCIE_IO(5), _MV_PCIE_IO_SIZE, 8, 0xD0, 164 _MV_PCIE_MEM(5), _MV_PCIE_MEM_SIZE, 8, 0xD8, 165 NULL, MV_INT_PEX11 }, 166 { MV_TYPE_PCIE_AGGR_LANE, 167 MV_PCIE12_BASE, MV_PCIE_SIZE, 168 _MV_PCIE_IO(6), _MV_PCIE_IO_SIZE, 8, 0xB0, 169 _MV_PCIE_MEM(6), _MV_PCIE_MEM_SIZE, 8, 0xB8, 170 NULL, MV_INT_PEX12 }, 171 { MV_TYPE_PCIE_AGGR_LANE, 172 MV_PCIE13_BASE, MV_PCIE_SIZE, 173 _MV_PCIE_IO(7), _MV_PCIE_IO_SIZE, 8, 0x70, 174 _MV_PCIE_MEM(7), _MV_PCIE_MEM_SIZE, 8, 0x78, 175 NULL, MV_INT_PEX13 }, 176 177 { 0, 0, 0 } 178}; 179 180struct resource_spec mv_gpio_spec[] = { 181 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 182 { SYS_RES_IRQ, 0, RF_ACTIVE }, 183 { SYS_RES_IRQ, 1, RF_ACTIVE }, 184 { SYS_RES_IRQ, 2, RF_ACTIVE }, 185 { SYS_RES_IRQ, 3, RF_ACTIVE }, 186 { -1, 0 } 187}; 188 189struct resource_spec mv_xor_spec[] = { 190 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 191 { SYS_RES_IRQ, 0, RF_ACTIVE }, 192 { SYS_RES_IRQ, 1, RF_ACTIVE }, 193 { SYS_RES_IRQ, 2, RF_ACTIVE }, 194 { -1, 0 } 195}; 196 197const struct decode_win cpu_win_tbl[] = { 198 /* Device bus BOOT */ 199 { 1, 0x2f, MV_DEV_BOOT_PHYS_BASE, MV_DEV_BOOT_SIZE, -1 }, 200 201 /* Device bus CS0 */ 202 { 1, 0x3e, MV_DEV_CS0_PHYS_BASE, MV_DEV_CS0_SIZE, -1 }, 203 204 /* Device bus CS1 */ 205 { 1, 0x3d, MV_DEV_CS1_PHYS_BASE, MV_DEV_CS1_SIZE, -1 }, 206 207 /* Device bus CS2 */ 208 { 1, 0x3b, MV_DEV_CS2_PHYS_BASE, MV_DEV_CS2_SIZE, -1 }, 209}; 210const struct decode_win *cpu_wins = cpu_win_tbl; 211int cpu_wins_no = sizeof(cpu_win_tbl) / sizeof(struct decode_win); 212 213/* 214 * Note: the decode windows table for IDMA does not explicitly have DRAM 215 * entries, which are not statically defined: active DDR banks (== windows) 216 * are established in run time from actual DDR windows settings. All active 217 * DDR banks are mapped into IDMA decode windows, so at least one IDMA decode 218 * window is occupied by the DDR bank; in case when all (MV_WIN_DDR_MAX) 219 * DDR banks are active, the remaining available IDMA decode windows for other 220 * targets is only MV_WIN_IDMA_MAX - MV_WIN_DDR_MAX. 221 */ 222const struct decode_win idma_win_tbl[] = { 223 /* PCIE MEM */ 224 { 4, 0xE8, _MV_PCIE_MEM_PHYS(0), _MV_PCIE_MEM_SIZE, -1 }, 225 { 4, 0xD8, _MV_PCIE_MEM_PHYS(1), _MV_PCIE_MEM_SIZE, -1 }, 226}; 227const struct decode_win *idma_wins = idma_win_tbl; 228int idma_wins_no = sizeof(idma_win_tbl) / sizeof(struct decode_win); 229