discovery.c revision 186909
1183840Sraj/*- 2183840Sraj * Copyright (C) 2008 MARVELL INTERNATIONAL LTD. 3183840Sraj * All rights reserved. 4183840Sraj * 5183840Sraj * Developed by Semihalf. 6183840Sraj * 7183840Sraj * Redistribution and use in source and binary forms, with or without 8183840Sraj * modification, are permitted provided that the following conditions 9183840Sraj * are met: 10183840Sraj * 1. Redistributions of source code must retain the above copyright 11183840Sraj * notice, this list of conditions and the following disclaimer. 12183840Sraj * 2. Redistributions in binary form must reproduce the above copyright 13183840Sraj * notice, this list of conditions and the following disclaimer in the 14183840Sraj * documentation and/or other materials provided with the distribution. 15183840Sraj * 3. Neither the name of MARVELL nor the names of contributors 16183840Sraj * may be used to endorse or promote products derived from this software 17183840Sraj * without specific prior written permission. 18183840Sraj * 19183840Sraj * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20183840Sraj * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21183840Sraj * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22183840Sraj * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 23183840Sraj * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24183840Sraj * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25183840Sraj * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26183840Sraj * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27183840Sraj * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28183840Sraj * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29183840Sraj * SUCH DAMAGE. 30183840Sraj */ 31183840Sraj 32183840Sraj#include <sys/cdefs.h> 33183840Sraj__FBSDID("$FreeBSD: head/sys/arm/mv/discovery/discovery.c 186909 2009-01-08 18:31:43Z raj $"); 34183840Sraj 35183840Sraj#include <sys/param.h> 36183840Sraj#include <sys/systm.h> 37183840Sraj#include <sys/bus.h> 38183840Sraj 39183840Sraj#include <machine/bus.h> 40183840Sraj 41183840Sraj#include <arm/mv/mvreg.h> 42183840Sraj#include <arm/mv/mvvar.h> 43183840Sraj 44185089Sraj#define _MV_PCIE_MAX_PORT 8 45185089Sraj 46185089Sraj#define _MV_PCIE_IO_SIZE (MV_PCIE_IO_SIZE / _MV_PCIE_MAX_PORT) 47185089Sraj#define _MV_PCIE_MEM_SIZE (MV_PCIE_MEM_SIZE / _MV_PCIE_MAX_PORT) 48185089Sraj 49185089Sraj#define _MV_PCIE_IO(n) (MV_PCIE_IO_BASE + ((n) * _MV_PCIE_IO_SIZE)) 50185089Sraj#define _MV_PCIE_MEM(n) (MV_PCIE_MEM_BASE + ((n) * _MV_PCIE_MEM_SIZE)) 51185089Sraj 52185089Sraj#define _MV_PCIE_IO_PHYS(n) (MV_PCIE_IO_PHYS_BASE + ((n) * _MV_PCIE_IO_SIZE)) 53185089Sraj#define _MV_PCIE_MEM_PHYS(n) (MV_PCIE_MEM_PHYS_BASE + ((n) * _MV_PCIE_MEM_SIZE)) 54185089Sraj 55185089Sraj/* 56185089Sraj * Note the 'pcib' devices are not declared in the obio_devices[]: due to the 57185089Sraj * much more complex configuration schemes allowed, specifically of the 58185089Sraj * PCI-Express (multiple lanes width per port configured dynamically etc.) it 59185089Sraj * is better and flexible to instantiate the number of PCI bridge devices 60185089Sraj * (known in run-time) in the pcib_mbus_identify() method. 61185089Sraj */ 62183840Srajstruct obio_device obio_devices[] = { 63183840Sraj { "ic", MV_IC_BASE, MV_IC_SIZE, 64183840Sraj { -1 }, 65183840Sraj { -1 }, 66183840Sraj CPU_PM_CTRL_NONE 67183840Sraj }, 68183840Sraj { "timer", MV_TIMERS_BASE, MV_TIMERS_SIZE, 69183840Sraj { MV_INT_TIMER0, -1 }, 70183840Sraj { -1 }, 71183840Sraj CPU_PM_CTRL_NONE 72183840Sraj }, 73183840Sraj { "gpio", MV_GPIO_BASE, MV_GPIO_SIZE, 74183840Sraj { MV_INT_GPIO7_0, MV_INT_GPIO15_8, 75183840Sraj MV_INT_GPIO23_16, MV_INT_GPIO31_24, -1 }, 76183840Sraj { -1 }, 77183840Sraj CPU_PM_CTRL_NONE 78183840Sraj }, 79183840Sraj { "uart", MV_UART0_BASE, MV_UART_SIZE, 80183840Sraj { MV_INT_UART0, -1 }, 81183840Sraj { -1 }, 82183840Sraj CPU_PM_CTRL_NONE 83183840Sraj }, 84183840Sraj { "uart", MV_UART1_BASE, MV_UART_SIZE, 85183840Sraj { MV_INT_UART1, -1 }, 86183840Sraj { -1 }, 87183840Sraj CPU_PM_CTRL_NONE 88183840Sraj }, 89183840Sraj { "idma", MV_IDMA_BASE, MV_IDMA_SIZE, 90183840Sraj { MV_INT_IDMA_ERR, MV_INT_IDMA0, MV_INT_IDMA1, 91183840Sraj MV_INT_IDMA2, MV_INT_IDMA3, -1 }, 92183840Sraj { -1 }, 93183840Sraj CPU_PM_CTRL_IDMA 94183840Sraj }, 95183840Sraj { "xor", MV_XOR_BASE, MV_XOR_SIZE, 96183840Sraj { MV_INT_XOR0, MV_INT_XOR1, 97183840Sraj MV_INT_XOR_ERR, -1 }, 98183840Sraj { -1 }, 99183840Sraj CPU_PM_CTRL_XOR 100183840Sraj }, 101183840Sraj { "ehci", MV_USB0_BASE, MV_USB_SIZE, 102183840Sraj { MV_INT_USB_ERR, MV_INT_USB0, -1 }, 103183840Sraj { -1 }, 104183840Sraj CPU_PM_CTRL_USB0 | CPU_PM_CTRL_USB1 | CPU_PM_CTRL_USB2 105183840Sraj }, 106186909Sraj { "ehci", MV_USB1_BASE, MV_USB_SIZE, 107186909Sraj { MV_INT_USB_ERR, MV_INT_USB1, -1 }, 108186909Sraj { -1 }, 109186909Sraj CPU_PM_CTRL_USB0 | CPU_PM_CTRL_USB1 | CPU_PM_CTRL_USB2 110186909Sraj }, 111186909Sraj { "ehci", MV_USB2_BASE, MV_USB_SIZE, 112186909Sraj { MV_INT_USB_ERR, MV_INT_USB2, -1 }, 113186909Sraj { -1 }, 114186909Sraj CPU_PM_CTRL_USB0 | CPU_PM_CTRL_USB1 | CPU_PM_CTRL_USB2 115186909Sraj }, 116183840Sraj { "mge", MV_ETH0_BASE, MV_ETH_SIZE, 117183840Sraj { MV_INT_GBERX, MV_INT_GBETX, MV_INT_GBEMISC, 118183840Sraj MV_INT_GBESUM, MV_INT_GBE_ERR, -1 }, 119183840Sraj { -1 }, 120183840Sraj CPU_PM_CTRL_GE0 121183840Sraj }, 122183840Sraj { "mge", MV_ETH1_BASE, MV_ETH_SIZE, 123183840Sraj { MV_INT_GBE1RX, MV_INT_GBE1TX, MV_INT_GBE1MISC, 124183840Sraj MV_INT_GBE1SUM, MV_INT_GBE_ERR, -1 }, 125183840Sraj { -1 }, 126183840Sraj CPU_PM_CTRL_GE1 127183840Sraj }, 128183840Sraj { "twsi", MV_TWSI_BASE, MV_TWSI_SIZE, 129183840Sraj { -1 }, { -1 }, 130183840Sraj CPU_PM_CTRL_NONE 131183840Sraj }, 132183840Sraj { NULL, 0, 0, { 0 }, { 0 }, 0 } 133183840Sraj}; 134183840Sraj 135185089Srajconst struct obio_pci mv_pci_info[] = { 136185089Sraj { MV_TYPE_PCIE, 137185089Sraj MV_PCIE00_BASE, MV_PCIE_SIZE, 138185089Sraj _MV_PCIE_IO(0), _MV_PCIE_IO_SIZE, 4, 0xE0, 139185089Sraj _MV_PCIE_MEM(0), _MV_PCIE_MEM_SIZE, 4, 0xE8, 140185089Sraj NULL, MV_INT_PEX00 }, 141185089Sraj 142185089Sraj { MV_TYPE_PCIE_AGGR_LANE, 143185089Sraj MV_PCIE01_BASE, MV_PCIE_SIZE, 144185089Sraj _MV_PCIE_IO(1), _MV_PCIE_IO_SIZE, 4, 0xD0, 145185089Sraj _MV_PCIE_MEM(1), _MV_PCIE_MEM_SIZE, 4, 0xD8, 146185089Sraj NULL, MV_INT_PEX01 }, 147185089Sraj#if 0 148185089Sraj /* 149185089Sraj * XXX Access to devices on this interface (PCIE 0.2) crashes the 150185089Sraj * system. Could be a silicon defect as Marvell U-Boot has a 'Do not 151185089Sraj * touch' precaution comment... 152185089Sraj */ 153185089Sraj { MV_TYPE_PCIE_AGGR_LANE, 154185089Sraj MV_PCIE02_BASE, MV_PCIE_SIZE, 155185089Sraj _MV_PCIE_IO(2), _MV_PCIE_IO_SIZE(2), 4, 0xB0, 156185089Sraj _MV_PCIE_MEM(2), _MV_PCIE_MEM_SIZE(2), 4, 0xB8, 157185089Sraj NULL, MV_INT_PEX02 }, 158185089Sraj#endif 159185089Sraj { MV_TYPE_PCIE_AGGR_LANE, 160185089Sraj MV_PCIE03_BASE, MV_PCIE_SIZE, 161185089Sraj _MV_PCIE_IO(3), _MV_PCIE_IO_SIZE, 4, 0x70, 162185089Sraj _MV_PCIE_MEM(3), _MV_PCIE_MEM_SIZE, 4, 0x78, 163185089Sraj NULL, MV_INT_PEX03 }, 164185089Sraj 165185089Sraj { MV_TYPE_PCIE, 166185089Sraj MV_PCIE10_BASE, MV_PCIE_SIZE, 167185089Sraj _MV_PCIE_IO(4), _MV_PCIE_IO_SIZE, 8, 0xE0, 168185089Sraj _MV_PCIE_MEM(4), _MV_PCIE_MEM_SIZE, 8, 0xE8, 169185089Sraj NULL, MV_INT_PEX10 }, 170185089Sraj 171185089Sraj { MV_TYPE_PCIE_AGGR_LANE, 172185089Sraj MV_PCIE11_BASE, MV_PCIE_SIZE, 173185089Sraj _MV_PCIE_IO(5), _MV_PCIE_IO_SIZE, 8, 0xD0, 174185089Sraj _MV_PCIE_MEM(5), _MV_PCIE_MEM_SIZE, 8, 0xD8, 175185089Sraj NULL, MV_INT_PEX11 }, 176185089Sraj { MV_TYPE_PCIE_AGGR_LANE, 177185089Sraj MV_PCIE12_BASE, MV_PCIE_SIZE, 178185089Sraj _MV_PCIE_IO(6), _MV_PCIE_IO_SIZE, 8, 0xB0, 179185089Sraj _MV_PCIE_MEM(6), _MV_PCIE_MEM_SIZE, 8, 0xB8, 180185089Sraj NULL, MV_INT_PEX12 }, 181185089Sraj { MV_TYPE_PCIE_AGGR_LANE, 182185089Sraj MV_PCIE13_BASE, MV_PCIE_SIZE, 183185089Sraj _MV_PCIE_IO(7), _MV_PCIE_IO_SIZE, 8, 0x70, 184185089Sraj _MV_PCIE_MEM(7), _MV_PCIE_MEM_SIZE, 8, 0x78, 185185089Sraj NULL, MV_INT_PEX13 }, 186185089Sraj 187185089Sraj { 0, 0, 0 } 188185089Sraj}; 189185089Sraj 190186909Srajstruct resource_spec mv_gpio_res[] = { 191183840Sraj { SYS_RES_MEMORY, 0, RF_ACTIVE }, 192183840Sraj { SYS_RES_IRQ, 0, RF_ACTIVE }, 193183840Sraj { SYS_RES_IRQ, 1, RF_ACTIVE }, 194183840Sraj { SYS_RES_IRQ, 2, RF_ACTIVE }, 195183840Sraj { SYS_RES_IRQ, 3, RF_ACTIVE }, 196183840Sraj { -1, 0 } 197183840Sraj}; 198183840Sraj 199186909Srajstruct resource_spec mv_xor_res[] = { 200183840Sraj { SYS_RES_MEMORY, 0, RF_ACTIVE }, 201183840Sraj { SYS_RES_IRQ, 0, RF_ACTIVE }, 202183840Sraj { SYS_RES_IRQ, 1, RF_ACTIVE }, 203183840Sraj { SYS_RES_IRQ, 2, RF_ACTIVE }, 204183840Sraj { -1, 0 } 205183840Sraj}; 206183840Sraj 207183840Srajconst struct decode_win cpu_win_tbl[] = { 208183840Sraj /* Device bus BOOT */ 209183840Sraj { 1, 0x2f, MV_DEV_BOOT_PHYS_BASE, MV_DEV_BOOT_SIZE, -1 }, 210183840Sraj 211183840Sraj /* Device bus CS0 */ 212183840Sraj { 1, 0x3e, MV_DEV_CS0_PHYS_BASE, MV_DEV_CS0_SIZE, -1 }, 213183840Sraj 214183840Sraj /* Device bus CS1 */ 215183840Sraj { 1, 0x3d, MV_DEV_CS1_PHYS_BASE, MV_DEV_CS1_SIZE, -1 }, 216183840Sraj 217183840Sraj /* Device bus CS2 */ 218183840Sraj { 1, 0x3b, MV_DEV_CS2_PHYS_BASE, MV_DEV_CS2_SIZE, -1 }, 219186909Sraj 220186909Sraj /* CESA */ 221186909Sraj { 9, 0x01, MV_CESA_SRAM_PHYS_BASE, MV_CESA_SRAM_SIZE, -1 }, 222183840Sraj}; 223183840Srajconst struct decode_win *cpu_wins = cpu_win_tbl; 224183840Srajint cpu_wins_no = sizeof(cpu_win_tbl) / sizeof(struct decode_win); 225183840Sraj 226183840Sraj/* 227183840Sraj * Note: the decode windows table for IDMA does not explicitly have DRAM 228183840Sraj * entries, which are not statically defined: active DDR banks (== windows) 229183840Sraj * are established in run time from actual DDR windows settings. All active 230183840Sraj * DDR banks are mapped into IDMA decode windows, so at least one IDMA decode 231183840Sraj * window is occupied by the DDR bank; in case when all (MV_WIN_DDR_MAX) 232183840Sraj * DDR banks are active, the remaining available IDMA decode windows for other 233183840Sraj * targets is only MV_WIN_IDMA_MAX - MV_WIN_DDR_MAX. 234183840Sraj */ 235183840Srajconst struct decode_win idma_win_tbl[] = { 236183840Sraj /* PCIE MEM */ 237185089Sraj { 4, 0xE8, _MV_PCIE_MEM_PHYS(0), _MV_PCIE_MEM_SIZE, -1 }, 238185089Sraj { 4, 0xD8, _MV_PCIE_MEM_PHYS(1), _MV_PCIE_MEM_SIZE, -1 }, 239183840Sraj}; 240183840Srajconst struct decode_win *idma_wins = idma_win_tbl; 241183840Srajint idma_wins_no = sizeof(idma_win_tbl) / sizeof(struct decode_win); 242186899Sraj 243186909Srajconst struct decode_win xor_win_tbl[] = { 244186909Sraj /* PCIE MEM */ 245186909Sraj { 4, 0xE8, _MV_PCIE_MEM_PHYS(0), _MV_PCIE_MEM_SIZE, -1}, 246186909Sraj { 4, 0xD8, _MV_PCIE_MEM_PHYS(1), _MV_PCIE_MEM_SIZE, -1}, 247186909Sraj}; 248186909Srajconst struct decode_win *xor_wins = xor_win_tbl; 249186909Srajint xor_wins_no = sizeof(xor_win_tbl) / sizeof(struct decode_win); 250186909Sraj 251186899Srajuint32_t 252186899Srajget_tclk(void) 253186899Sraj{ 254186899Sraj uint32_t sar; 255186899Sraj 256186899Sraj /* 257186899Sraj * On Discovery TCLK is can be configured to 166 MHz or 200 MHz. 258186899Sraj * Current setting is read from Sample At Reset register. 259186899Sraj */ 260186899Sraj sar = bus_space_read_4(obio_tag, MV_MPP_BASE, SAMPLE_AT_RESET_HI); 261186899Sraj sar = (sar & TCLK_MASK) >> TCLK_SHIFT; 262186899Sraj 263186899Sraj switch (sar) { 264186899Sraj case 0: 265186899Sraj return (TCLK_166MHZ); 266186899Sraj case 1: 267186899Sraj return (TCLK_200MHZ); 268186899Sraj default: 269186899Sraj panic("Unknown TCLK settings!"); 270186899Sraj } 271186899Sraj} 272