discovery.c revision 186899
1183840Sraj/*- 2183840Sraj * Copyright (C) 2008 MARVELL INTERNATIONAL LTD. 3183840Sraj * All rights reserved. 4183840Sraj * 5183840Sraj * Developed by Semihalf. 6183840Sraj * 7183840Sraj * Redistribution and use in source and binary forms, with or without 8183840Sraj * modification, are permitted provided that the following conditions 9183840Sraj * are met: 10183840Sraj * 1. Redistributions of source code must retain the above copyright 11183840Sraj * notice, this list of conditions and the following disclaimer. 12183840Sraj * 2. Redistributions in binary form must reproduce the above copyright 13183840Sraj * notice, this list of conditions and the following disclaimer in the 14183840Sraj * documentation and/or other materials provided with the distribution. 15183840Sraj * 3. Neither the name of MARVELL nor the names of contributors 16183840Sraj * may be used to endorse or promote products derived from this software 17183840Sraj * without specific prior written permission. 18183840Sraj * 19183840Sraj * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20183840Sraj * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21183840Sraj * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22183840Sraj * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 23183840Sraj * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24183840Sraj * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25183840Sraj * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26183840Sraj * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27183840Sraj * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28183840Sraj * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29183840Sraj * SUCH DAMAGE. 30183840Sraj */ 31183840Sraj 32183840Sraj#include <sys/cdefs.h> 33183840Sraj__FBSDID("$FreeBSD: head/sys/arm/mv/discovery/discovery.c 186899 2009-01-08 13:20:28Z raj $"); 34183840Sraj 35183840Sraj#include <sys/param.h> 36183840Sraj#include <sys/systm.h> 37183840Sraj#include <sys/bus.h> 38183840Sraj 39183840Sraj#include <machine/bus.h> 40183840Sraj 41183840Sraj#include <arm/mv/mvreg.h> 42183840Sraj#include <arm/mv/mvvar.h> 43183840Sraj 44185089Sraj#define _MV_PCIE_MAX_PORT 8 45185089Sraj 46185089Sraj#define _MV_PCIE_IO_SIZE (MV_PCIE_IO_SIZE / _MV_PCIE_MAX_PORT) 47185089Sraj#define _MV_PCIE_MEM_SIZE (MV_PCIE_MEM_SIZE / _MV_PCIE_MAX_PORT) 48185089Sraj 49185089Sraj#define _MV_PCIE_IO(n) (MV_PCIE_IO_BASE + ((n) * _MV_PCIE_IO_SIZE)) 50185089Sraj#define _MV_PCIE_MEM(n) (MV_PCIE_MEM_BASE + ((n) * _MV_PCIE_MEM_SIZE)) 51185089Sraj 52185089Sraj#define _MV_PCIE_IO_PHYS(n) (MV_PCIE_IO_PHYS_BASE + ((n) * _MV_PCIE_IO_SIZE)) 53185089Sraj#define _MV_PCIE_MEM_PHYS(n) (MV_PCIE_MEM_PHYS_BASE + ((n) * _MV_PCIE_MEM_SIZE)) 54185089Sraj 55185089Sraj/* 56185089Sraj * Note the 'pcib' devices are not declared in the obio_devices[]: due to the 57185089Sraj * much more complex configuration schemes allowed, specifically of the 58185089Sraj * PCI-Express (multiple lanes width per port configured dynamically etc.) it 59185089Sraj * is better and flexible to instantiate the number of PCI bridge devices 60185089Sraj * (known in run-time) in the pcib_mbus_identify() method. 61185089Sraj */ 62183840Srajstruct obio_device obio_devices[] = { 63183840Sraj { "ic", MV_IC_BASE, MV_IC_SIZE, 64183840Sraj { -1 }, 65183840Sraj { -1 }, 66183840Sraj CPU_PM_CTRL_NONE 67183840Sraj }, 68183840Sraj { "timer", MV_TIMERS_BASE, MV_TIMERS_SIZE, 69183840Sraj { MV_INT_TIMER0, -1 }, 70183840Sraj { -1 }, 71183840Sraj CPU_PM_CTRL_NONE 72183840Sraj }, 73183840Sraj { "gpio", MV_GPIO_BASE, MV_GPIO_SIZE, 74183840Sraj { MV_INT_GPIO7_0, MV_INT_GPIO15_8, 75183840Sraj MV_INT_GPIO23_16, MV_INT_GPIO31_24, -1 }, 76183840Sraj { -1 }, 77183840Sraj CPU_PM_CTRL_NONE 78183840Sraj }, 79183840Sraj { "uart", MV_UART0_BASE, MV_UART_SIZE, 80183840Sraj { MV_INT_UART0, -1 }, 81183840Sraj { -1 }, 82183840Sraj CPU_PM_CTRL_NONE 83183840Sraj }, 84183840Sraj { "uart", MV_UART1_BASE, MV_UART_SIZE, 85183840Sraj { MV_INT_UART1, -1 }, 86183840Sraj { -1 }, 87183840Sraj CPU_PM_CTRL_NONE 88183840Sraj }, 89183840Sraj { "idma", MV_IDMA_BASE, MV_IDMA_SIZE, 90183840Sraj { MV_INT_IDMA_ERR, MV_INT_IDMA0, MV_INT_IDMA1, 91183840Sraj MV_INT_IDMA2, MV_INT_IDMA3, -1 }, 92183840Sraj { -1 }, 93183840Sraj CPU_PM_CTRL_IDMA 94183840Sraj }, 95183840Sraj { "xor", MV_XOR_BASE, MV_XOR_SIZE, 96183840Sraj { MV_INT_XOR0, MV_INT_XOR1, 97183840Sraj MV_INT_XOR_ERR, -1 }, 98183840Sraj { -1 }, 99183840Sraj CPU_PM_CTRL_XOR 100183840Sraj }, 101183840Sraj { "ehci", MV_USB0_BASE, MV_USB_SIZE, 102183840Sraj { MV_INT_USB_ERR, MV_INT_USB0, -1 }, 103183840Sraj { -1 }, 104183840Sraj CPU_PM_CTRL_USB0 | CPU_PM_CTRL_USB1 | CPU_PM_CTRL_USB2 105183840Sraj }, 106183840Sraj { "mge", MV_ETH0_BASE, MV_ETH_SIZE, 107183840Sraj { MV_INT_GBERX, MV_INT_GBETX, MV_INT_GBEMISC, 108183840Sraj MV_INT_GBESUM, MV_INT_GBE_ERR, -1 }, 109183840Sraj { -1 }, 110183840Sraj CPU_PM_CTRL_GE0 111183840Sraj }, 112183840Sraj { "mge", MV_ETH1_BASE, MV_ETH_SIZE, 113183840Sraj { MV_INT_GBE1RX, MV_INT_GBE1TX, MV_INT_GBE1MISC, 114183840Sraj MV_INT_GBE1SUM, MV_INT_GBE_ERR, -1 }, 115183840Sraj { -1 }, 116183840Sraj CPU_PM_CTRL_GE1 117183840Sraj }, 118183840Sraj { "twsi", MV_TWSI_BASE, MV_TWSI_SIZE, 119183840Sraj { -1 }, { -1 }, 120183840Sraj CPU_PM_CTRL_NONE 121183840Sraj }, 122183840Sraj { NULL, 0, 0, { 0 }, { 0 }, 0 } 123183840Sraj}; 124183840Sraj 125185089Srajconst struct obio_pci mv_pci_info[] = { 126185089Sraj { MV_TYPE_PCIE, 127185089Sraj MV_PCIE00_BASE, MV_PCIE_SIZE, 128185089Sraj _MV_PCIE_IO(0), _MV_PCIE_IO_SIZE, 4, 0xE0, 129185089Sraj _MV_PCIE_MEM(0), _MV_PCIE_MEM_SIZE, 4, 0xE8, 130185089Sraj NULL, MV_INT_PEX00 }, 131185089Sraj 132185089Sraj { MV_TYPE_PCIE_AGGR_LANE, 133185089Sraj MV_PCIE01_BASE, MV_PCIE_SIZE, 134185089Sraj _MV_PCIE_IO(1), _MV_PCIE_IO_SIZE, 4, 0xD0, 135185089Sraj _MV_PCIE_MEM(1), _MV_PCIE_MEM_SIZE, 4, 0xD8, 136185089Sraj NULL, MV_INT_PEX01 }, 137185089Sraj#if 0 138185089Sraj /* 139185089Sraj * XXX Access to devices on this interface (PCIE 0.2) crashes the 140185089Sraj * system. Could be a silicon defect as Marvell U-Boot has a 'Do not 141185089Sraj * touch' precaution comment... 142185089Sraj */ 143185089Sraj { MV_TYPE_PCIE_AGGR_LANE, 144185089Sraj MV_PCIE02_BASE, MV_PCIE_SIZE, 145185089Sraj _MV_PCIE_IO(2), _MV_PCIE_IO_SIZE(2), 4, 0xB0, 146185089Sraj _MV_PCIE_MEM(2), _MV_PCIE_MEM_SIZE(2), 4, 0xB8, 147185089Sraj NULL, MV_INT_PEX02 }, 148185089Sraj#endif 149185089Sraj { MV_TYPE_PCIE_AGGR_LANE, 150185089Sraj MV_PCIE03_BASE, MV_PCIE_SIZE, 151185089Sraj _MV_PCIE_IO(3), _MV_PCIE_IO_SIZE, 4, 0x70, 152185089Sraj _MV_PCIE_MEM(3), _MV_PCIE_MEM_SIZE, 4, 0x78, 153185089Sraj NULL, MV_INT_PEX03 }, 154185089Sraj 155185089Sraj { MV_TYPE_PCIE, 156185089Sraj MV_PCIE10_BASE, MV_PCIE_SIZE, 157185089Sraj _MV_PCIE_IO(4), _MV_PCIE_IO_SIZE, 8, 0xE0, 158185089Sraj _MV_PCIE_MEM(4), _MV_PCIE_MEM_SIZE, 8, 0xE8, 159185089Sraj NULL, MV_INT_PEX10 }, 160185089Sraj 161185089Sraj { MV_TYPE_PCIE_AGGR_LANE, 162185089Sraj MV_PCIE11_BASE, MV_PCIE_SIZE, 163185089Sraj _MV_PCIE_IO(5), _MV_PCIE_IO_SIZE, 8, 0xD0, 164185089Sraj _MV_PCIE_MEM(5), _MV_PCIE_MEM_SIZE, 8, 0xD8, 165185089Sraj NULL, MV_INT_PEX11 }, 166185089Sraj { MV_TYPE_PCIE_AGGR_LANE, 167185089Sraj MV_PCIE12_BASE, MV_PCIE_SIZE, 168185089Sraj _MV_PCIE_IO(6), _MV_PCIE_IO_SIZE, 8, 0xB0, 169185089Sraj _MV_PCIE_MEM(6), _MV_PCIE_MEM_SIZE, 8, 0xB8, 170185089Sraj NULL, MV_INT_PEX12 }, 171185089Sraj { MV_TYPE_PCIE_AGGR_LANE, 172185089Sraj MV_PCIE13_BASE, MV_PCIE_SIZE, 173185089Sraj _MV_PCIE_IO(7), _MV_PCIE_IO_SIZE, 8, 0x70, 174185089Sraj _MV_PCIE_MEM(7), _MV_PCIE_MEM_SIZE, 8, 0x78, 175185089Sraj NULL, MV_INT_PEX13 }, 176185089Sraj 177185089Sraj { 0, 0, 0 } 178185089Sraj}; 179185089Sraj 180183840Srajstruct resource_spec mv_gpio_spec[] = { 181183840Sraj { SYS_RES_MEMORY, 0, RF_ACTIVE }, 182183840Sraj { SYS_RES_IRQ, 0, RF_ACTIVE }, 183183840Sraj { SYS_RES_IRQ, 1, RF_ACTIVE }, 184183840Sraj { SYS_RES_IRQ, 2, RF_ACTIVE }, 185183840Sraj { SYS_RES_IRQ, 3, RF_ACTIVE }, 186183840Sraj { -1, 0 } 187183840Sraj}; 188183840Sraj 189183840Srajstruct resource_spec mv_xor_spec[] = { 190183840Sraj { SYS_RES_MEMORY, 0, RF_ACTIVE }, 191183840Sraj { SYS_RES_IRQ, 0, RF_ACTIVE }, 192183840Sraj { SYS_RES_IRQ, 1, RF_ACTIVE }, 193183840Sraj { SYS_RES_IRQ, 2, RF_ACTIVE }, 194183840Sraj { -1, 0 } 195183840Sraj}; 196183840Sraj 197183840Srajconst struct decode_win cpu_win_tbl[] = { 198183840Sraj /* Device bus BOOT */ 199183840Sraj { 1, 0x2f, MV_DEV_BOOT_PHYS_BASE, MV_DEV_BOOT_SIZE, -1 }, 200183840Sraj 201183840Sraj /* Device bus CS0 */ 202183840Sraj { 1, 0x3e, MV_DEV_CS0_PHYS_BASE, MV_DEV_CS0_SIZE, -1 }, 203183840Sraj 204183840Sraj /* Device bus CS1 */ 205183840Sraj { 1, 0x3d, MV_DEV_CS1_PHYS_BASE, MV_DEV_CS1_SIZE, -1 }, 206183840Sraj 207183840Sraj /* Device bus CS2 */ 208183840Sraj { 1, 0x3b, MV_DEV_CS2_PHYS_BASE, MV_DEV_CS2_SIZE, -1 }, 209183840Sraj}; 210183840Srajconst struct decode_win *cpu_wins = cpu_win_tbl; 211183840Srajint cpu_wins_no = sizeof(cpu_win_tbl) / sizeof(struct decode_win); 212183840Sraj 213183840Sraj/* 214183840Sraj * Note: the decode windows table for IDMA does not explicitly have DRAM 215183840Sraj * entries, which are not statically defined: active DDR banks (== windows) 216183840Sraj * are established in run time from actual DDR windows settings. All active 217183840Sraj * DDR banks are mapped into IDMA decode windows, so at least one IDMA decode 218183840Sraj * window is occupied by the DDR bank; in case when all (MV_WIN_DDR_MAX) 219183840Sraj * DDR banks are active, the remaining available IDMA decode windows for other 220183840Sraj * targets is only MV_WIN_IDMA_MAX - MV_WIN_DDR_MAX. 221183840Sraj */ 222183840Srajconst struct decode_win idma_win_tbl[] = { 223183840Sraj /* PCIE MEM */ 224185089Sraj { 4, 0xE8, _MV_PCIE_MEM_PHYS(0), _MV_PCIE_MEM_SIZE, -1 }, 225185089Sraj { 4, 0xD8, _MV_PCIE_MEM_PHYS(1), _MV_PCIE_MEM_SIZE, -1 }, 226183840Sraj}; 227183840Srajconst struct decode_win *idma_wins = idma_win_tbl; 228183840Srajint idma_wins_no = sizeof(idma_win_tbl) / sizeof(struct decode_win); 229186899Sraj 230186899Srajuint32_t 231186899Srajget_tclk(void) 232186899Sraj{ 233186899Sraj uint32_t sar; 234186899Sraj 235186899Sraj /* 236186899Sraj * On Discovery TCLK is can be configured to 166 MHz or 200 MHz. 237186899Sraj * Current setting is read from Sample At Reset register. 238186899Sraj */ 239186899Sraj sar = bus_space_read_4(obio_tag, MV_MPP_BASE, SAMPLE_AT_RESET_HI); 240186899Sraj sar = (sar & TCLK_MASK) >> TCLK_SHIFT; 241186899Sraj 242186899Sraj switch (sar) { 243186899Sraj case 0: 244186899Sraj return (TCLK_166MHZ); 245186899Sraj case 1: 246186899Sraj return (TCLK_200MHZ); 247186899Sraj default: 248186899Sraj panic("Unknown TCLK settings!"); 249186899Sraj } 250186899Sraj} 251