discovery.c revision 183840 
1/*-
2 * Copyright (C) 2008 MARVELL INTERNATIONAL LTD.
3 * All rights reserved.
4 *
5 * Developed by Semihalf.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 *    notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 *    notice, this list of conditions and the following disclaimer in the
14 *    documentation and/or other materials provided with the distribution.
15 * 3. Neither the name of MARVELL nor the names of contributors
16 *    may be used to endorse or promote products derived from this software
17 *    without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * SUCH DAMAGE.
30 */
31
32#include <sys/cdefs.h>
33__FBSDID("$FreeBSD: head/sys/arm/mv/discovery/discovery.c 183840 2008-10-13 20:07:13Z raj $");
34
35#include <sys/param.h>
36#include <sys/systm.h>
37#include <sys/bus.h>
38
39#include <machine/bus.h>
40
41#include <arm/mv/mvreg.h>
42#include <arm/mv/mvvar.h>
43
44struct obio_device obio_devices[] = {
45	{ "ic", MV_IC_BASE, MV_IC_SIZE,
46		{ -1 },
47		{ -1 },
48		CPU_PM_CTRL_NONE
49	},
50	{ "timer", MV_TIMERS_BASE, MV_TIMERS_SIZE,
51		{ MV_INT_TIMER0, -1 },
52		{ -1 },
53		CPU_PM_CTRL_NONE
54	},
55	{ "gpio", MV_GPIO_BASE, MV_GPIO_SIZE,
56		{ MV_INT_GPIO7_0, MV_INT_GPIO15_8,
57		  MV_INT_GPIO23_16, MV_INT_GPIO31_24, -1 },
58		{ -1 },
59		CPU_PM_CTRL_NONE
60	},
61	{ "uart", MV_UART0_BASE, MV_UART_SIZE,
62		{ MV_INT_UART0, -1 },
63		{ -1 },
64		CPU_PM_CTRL_NONE
65	},
66	{ "uart", MV_UART1_BASE, MV_UART_SIZE,
67		{ MV_INT_UART1, -1 },
68		{ -1 },
69		CPU_PM_CTRL_NONE
70	},
71	{ "idma", MV_IDMA_BASE, MV_IDMA_SIZE,
72		{ MV_INT_IDMA_ERR, MV_INT_IDMA0, MV_INT_IDMA1,
73		  MV_INT_IDMA2, MV_INT_IDMA3, -1 },
74		{ -1 },
75		CPU_PM_CTRL_IDMA
76	},
77	{ "xor", MV_XOR_BASE, MV_XOR_SIZE,
78		{ MV_INT_XOR0, MV_INT_XOR1,
79		  MV_INT_XOR_ERR, -1 },
80		{ -1 },
81		CPU_PM_CTRL_XOR
82	},
83	{ "ehci", MV_USB0_BASE, MV_USB_SIZE,
84		{ MV_INT_USB_ERR, MV_INT_USB0, -1 },
85		{ -1 },
86		CPU_PM_CTRL_USB0 | CPU_PM_CTRL_USB1 | CPU_PM_CTRL_USB2
87	},
88	{ "mge", MV_ETH0_BASE, MV_ETH_SIZE,
89		{ MV_INT_GBERX, MV_INT_GBETX, MV_INT_GBEMISC,
90		  MV_INT_GBESUM, MV_INT_GBE_ERR, -1 },
91		{ -1 },
92		CPU_PM_CTRL_GE0
93	},
94	{ "mge", MV_ETH1_BASE, MV_ETH_SIZE,
95		{ MV_INT_GBE1RX, MV_INT_GBE1TX, MV_INT_GBE1MISC,
96		  MV_INT_GBE1SUM, MV_INT_GBE_ERR, -1 },
97		{ -1 },
98		CPU_PM_CTRL_GE1
99	},
100	{ "twsi", MV_TWSI_BASE, MV_TWSI_SIZE,
101		{ -1 }, { -1 },
102		CPU_PM_CTRL_NONE
103	},
104	{ NULL, 0, 0, { 0 }, { 0 }, 0 }
105};
106
107struct resource_spec mv_gpio_spec[] = {
108	{ SYS_RES_MEMORY,	0,	RF_ACTIVE },
109	{ SYS_RES_IRQ,		0,	RF_ACTIVE },
110	{ SYS_RES_IRQ,		1,	RF_ACTIVE },
111	{ SYS_RES_IRQ,		2,	RF_ACTIVE },
112	{ SYS_RES_IRQ,		3,	RF_ACTIVE },
113	{ -1, 0 }
114};
115
116struct resource_spec mv_xor_spec[] = {
117	{ SYS_RES_MEMORY,	0,	RF_ACTIVE },
118	{ SYS_RES_IRQ,		0,	RF_ACTIVE },
119	{ SYS_RES_IRQ,		1,	RF_ACTIVE },
120	{ SYS_RES_IRQ,		2,	RF_ACTIVE },
121	{ -1, 0 }
122};
123
124const struct decode_win cpu_win_tbl[] = {
125	/* PCIE IO */
126	{ 4, 0x51, MV_PCIE_IO_PHYS_BASE, MV_PCIE_IO_SIZE, -1 },
127
128	/* PCIE MEM */
129	{ 4, 0x59, MV_PCIE_MEM_PHYS_BASE, MV_PCIE_MEM_SIZE, -1 },
130
131	/* Device bus BOOT */
132	{ 1, 0x2f, MV_DEV_BOOT_PHYS_BASE, MV_DEV_BOOT_SIZE, -1 },
133
134	/* Device bus CS0 */
135	{ 1, 0x3e, MV_DEV_CS0_PHYS_BASE, MV_DEV_CS0_SIZE, -1 },
136
137	/* Device bus CS1 */
138	{ 1, 0x3d, MV_DEV_CS1_PHYS_BASE, MV_DEV_CS1_SIZE, -1 },
139
140	/* Device bus CS2 */
141	{ 1, 0x3b, MV_DEV_CS2_PHYS_BASE, MV_DEV_CS2_SIZE, -1 },
142};
143const struct decode_win *cpu_wins = cpu_win_tbl;
144int cpu_wins_no = sizeof(cpu_win_tbl) / sizeof(struct decode_win);
145
146/*
147 * Note: the decode windows table for IDMA does not explicitly have DRAM
148 * entries, which are not statically defined: active DDR banks (== windows)
149 * are established in run time from actual DDR windows settings. All active
150 * DDR banks are mapped into IDMA decode windows, so at least one IDMA decode
151 * window is occupied by the DDR bank; in case when all (MV_WIN_DDR_MAX)
152 * DDR banks are active, the remaining available IDMA decode windows for other
153 * targets is only MV_WIN_IDMA_MAX - MV_WIN_DDR_MAX.
154 */
155const struct decode_win idma_win_tbl[] = {
156	/* PCIE MEM */
157	{ 4, 0x59, MV_PCIE_MEM_PHYS_BASE, MV_PCIE_MEM_SIZE, -1 },
158};
159const struct decode_win *idma_wins = idma_win_tbl;
160int idma_wins_no = sizeof(idma_win_tbl) / sizeof(struct decode_win);
161