1294439Szbb/*- 2294439Szbb * Copyright (c) 2015 Semihalf. 3294439Szbb * Copyright (c) 2015 Stormshield. 4294439Szbb * All rights reserved. 5294439Szbb * 6294439Szbb * Redistribution and use in source and binary forms, with or without 7294439Szbb * modification, are permitted provided that the following conditions 8294439Szbb * are met: 9294439Szbb * 1. Redistributions of source code must retain the above copyright 10294439Szbb * notice, this list of conditions and the following disclaimer. 11294439Szbb * 2. Redistributions in binary form must reproduce the above copyright 12294439Szbb * notice, this list of conditions and the following disclaimer in the 13294439Szbb * documentation and/or other materials provided with the distribution. 14294439Szbb * 15294439Szbb * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16294439Szbb * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17294439Szbb * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18294439Szbb * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19294439Szbb * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20294439Szbb * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21294439Szbb * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22294439Szbb * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23294439Szbb * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24294439Szbb * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25294439Szbb * SUCH DAMAGE. 26294439Szbb */ 27294439Szbb#include <sys/cdefs.h> 28294439Szbb__FBSDID("$FreeBSD$"); 29294439Szbb 30294439Szbb#include <sys/param.h> 31294439Szbb#include <sys/systm.h> 32294439Szbb#include <sys/bus.h> 33294439Szbb#include <sys/smp.h> 34294439Szbb 35294439Szbb#include <machine/smp.h> 36294439Szbb#include <machine/fdt.h> 37294439Szbb#include <machine/intr.h> 38294439Szbb 39294439Szbb#include <dev/ofw/ofw_bus.h> 40294439Szbb#include <dev/ofw/ofw_bus_subr.h> 41294439Szbb 42294439Szbb#include <arm/mv/mvreg.h> 43294439Szbb 44294441Szbb#include "pmsu.h" 45294441Szbb 46294439Szbbint cpu_reset_deassert(void); 47294439Szbb 48294439Szbbint 49294439Szbbcpu_reset_deassert(void) 50294439Szbb{ 51294439Szbb bus_space_handle_t vaddr; 52294439Szbb uint32_t reg; 53294439Szbb int rv; 54294439Szbb 55294439Szbb rv = bus_space_map(fdtbus_bs_tag, (bus_addr_t)MV_CPU_RESET_BASE, 56294439Szbb MV_CPU_RESET_REGS_LEN, 0, &vaddr); 57294439Szbb if (rv != 0) 58294439Szbb return (rv); 59294439Szbb 60294439Szbb /* CPU1 is held at reset by default - clear assert bit to release it */ 61294439Szbb reg = bus_space_read_4(fdtbus_bs_tag, vaddr, CPU_RESET_OFFSET(1)); 62294439Szbb reg &= ~CPU_RESET_ASSERT; 63294439Szbb 64294439Szbb bus_space_write_4(fdtbus_bs_tag, vaddr, CPU_RESET_OFFSET(1), reg); 65294439Szbb 66294439Szbb bus_space_unmap(fdtbus_bs_tag, vaddr, MV_CPU_RESET_REGS_LEN); 67294439Szbb 68294439Szbb return (0); 69294439Szbb} 70294439Szbb 71294439Szbbstatic int 72294439Szbbplatform_cnt_cpus(void) 73294439Szbb{ 74294439Szbb bus_space_handle_t vaddr_scu; 75294439Szbb phandle_t cpus_node, child; 76294439Szbb char device_type[16]; 77294439Szbb int fdt_cpu_count = 0; 78294439Szbb int reg_cpu_count = 0; 79294439Szbb uint32_t val; 80294439Szbb int rv; 81294439Szbb 82294439Szbb cpus_node = OF_finddevice("/cpus"); 83294439Szbb if (cpus_node == -1) { 84294439Szbb /* Default is one core */ 85294439Szbb mp_ncpus = 1; 86294439Szbb return (0); 87294439Szbb } 88294439Szbb 89294439Szbb /* Get number of 'cpu' nodes from FDT */ 90294439Szbb for (child = OF_child(cpus_node); child != 0; child = OF_peer(child)) { 91294439Szbb /* Check if child is a CPU */ 92294439Szbb memset(device_type, 0, sizeof(device_type)); 93294439Szbb rv = OF_getprop(child, "device_type", device_type, 94294439Szbb sizeof(device_type) - 1); 95294439Szbb if (rv < 0) 96294439Szbb continue; 97294439Szbb if (strcmp(device_type, "cpu") != 0) 98294439Szbb continue; 99294439Szbb 100294439Szbb fdt_cpu_count++; 101294439Szbb } 102294439Szbb 103294439Szbb /* Get number of CPU cores from SCU register to cross-check with FDT */ 104294439Szbb rv = bus_space_map(fdtbus_bs_tag, (bus_addr_t)MV_SCU_BASE, 105294439Szbb MV_SCU_REGS_LEN, 0, &vaddr_scu); 106294439Szbb if (rv != 0) { 107294439Szbb /* Default is one core */ 108294439Szbb mp_ncpus = 1; 109294439Szbb return (0); 110294439Szbb } 111294439Szbb 112294439Szbb val = bus_space_read_4(fdtbus_bs_tag, vaddr_scu, MV_SCU_REG_CONFIG); 113294439Szbb bus_space_unmap(fdtbus_bs_tag, vaddr_scu, MV_SCU_REGS_LEN); 114294439Szbb reg_cpu_count = (val & SCU_CFG_REG_NCPU_MASK) + 1; 115294439Szbb 116294439Szbb /* Set mp_ncpus to number of cpus in FDT unless SOC contains only one */ 117294439Szbb mp_ncpus = min(reg_cpu_count, fdt_cpu_count); 118294439Szbb /* mp_ncpus must be at least 1 */ 119294439Szbb mp_ncpus = max(1, mp_ncpus); 120294439Szbb 121294439Szbb return (mp_ncpus); 122294439Szbb} 123294439Szbb 124294439Szbbvoid 125294439Szbbplatform_mp_setmaxid(void) 126294439Szbb{ 127294439Szbb 128294439Szbb /* Armada38x family supports maximum 2 cores */ 129294439Szbb mp_ncpus = platform_cnt_cpus(); 130294439Szbb mp_maxid = 1; 131294439Szbb} 132294439Szbb 133294439Szbbvoid 134294439Szbbplatform_mp_start_ap(void) 135294439Szbb{ 136294439Szbb int rv; 137294439Szbb 138294439Szbb /* Write secondary entry address to PMSU register */ 139294439Szbb rv = pmsu_boot_secondary_cpu(); 140294439Szbb if (rv != 0) 141294439Szbb return; 142294439Szbb 143294439Szbb /* Release CPU1 from reset */ 144294439Szbb cpu_reset_deassert(); 145294439Szbb} 146