sysreg.h revision 272209
1272209Sandrew/*- 2272209Sandrew * Copyright 2014 Svatopluk Kraus <onwahe@gmail.com> 3272209Sandrew * Copyright 2014 Michal Meloun <meloun@miracle.cz> 4272209Sandrew * All rights reserved. 5272209Sandrew * 6272209Sandrew * Redistribution and use in source and binary forms, with or without 7272209Sandrew * modification, are permitted provided that the following conditions 8272209Sandrew * are met: 9272209Sandrew * 1. Redistributions of source code must retain the above copyright 10272209Sandrew * notice, this list of conditions and the following disclaimer. 11272209Sandrew * 2. Redistributions in binary form must reproduce the above copyright 12272209Sandrew * notice, this list of conditions and the following disclaimer in the 13272209Sandrew * documentation and/or other materials provided with the distribution. 14272209Sandrew * 15272209Sandrew * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16272209Sandrew * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17272209Sandrew * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18272209Sandrew * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19272209Sandrew * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20272209Sandrew * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21272209Sandrew * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22272209Sandrew * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23272209Sandrew * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24272209Sandrew * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25272209Sandrew * SUCH DAMAGE. 26272209Sandrew * 27272209Sandrew * $FreeBSD: head/sys/arm/include/sysreg.h 272209 2014-09-27 09:57:34Z andrew $ 28272209Sandrew */ 29272209Sandrew 30272209Sandrew/* 31272209Sandrew * Macros to make working with the System Control Registers simpler. 32272209Sandrew */ 33272209Sandrew 34272209Sandrew#ifndef MACHINE_SYSREG_H 35272209Sandrew#define MACHINE_SYSREG_H 36272209Sandrew 37272209Sandrew/* 38272209Sandrew * CP15 C0 registers 39272209Sandrew */ 40272209Sandrew#define CP15_MIDR(rr) p15, 0, rr, c0, c0, 0 /* Main ID Register */ 41272209Sandrew#define CP15_CTR(rr) p15, 0, rr, c0, c0, 1 /* Cache Type Register */ 42272209Sandrew#define CP15_TCMTR(rr) p15, 0, rr, c0, c0, 2 /* TCM Type Register */ 43272209Sandrew#define CP15_TLBTR(rr) p15, 0, rr, c0, c0, 3 /* TLB Type Register */ 44272209Sandrew#define CP15_MPIDR(rr) p15, 0, rr, c0, c0, 5 /* Multiprocessor Affinity Register */ 45272209Sandrew#define CP15_REVIDR(rr) p15, 0, rr, c0, c0, 6 /* Revision ID Register */ 46272209Sandrew 47272209Sandrew#define CP15_ID_PFR0(rr) p15, 0, rr, c0, c1, 0 /* Processor Feature Register 0 */ 48272209Sandrew#define CP15_ID_PFR1(rr) p15, 0, rr, c0, c1, 1 /* Processor Feature Register 1 */ 49272209Sandrew#define CP15_ID_DFR0(rr) p15, 0, rr, c0, c1, 2 /* Debug Feature Register 0 */ 50272209Sandrew#define CP15_ID_AFR0(rr) p15, 0, rr, c0, c1, 3 /* Auxiliary Feature Register 0 */ 51272209Sandrew#define CP15_ID_MMFR0(rr) p15, 0, rr, c0, c1, 4 /* Memory Model Feature Register 0 */ 52272209Sandrew#define CP15_ID_MMFR1(rr) p15, 0, rr, c0, c1, 5 /* Memory Model Feature Register 1 */ 53272209Sandrew#define CP15_ID_MMFR2(rr) p15, 0, rr, c0, c1, 6 /* Memory Model Feature Register 2 */ 54272209Sandrew#define CP15_ID_MMFR3(rr) p15, 0, rr, c0, c1, 7 /* Memory Model Feature Register 3 */ 55272209Sandrew 56272209Sandrew#define CP15_ID_ISAR0(rr) p15, 0, rr, c0, c2, 0 /* Instruction Set Attribute Register 0 */ 57272209Sandrew#define CP15_ID_ISAR1(rr) p15, 0, rr, c0, c2, 1 /* Instruction Set Attribute Register 1 */ 58272209Sandrew#define CP15_ID_ISAR2(rr) p15, 0, rr, c0, c2, 2 /* Instruction Set Attribute Register 2 */ 59272209Sandrew#define CP15_ID_ISAR3(rr) p15, 0, rr, c0, c2, 3 /* Instruction Set Attribute Register 3 */ 60272209Sandrew#define CP15_ID_ISAR4(rr) p15, 0, rr, c0, c2, 4 /* Instruction Set Attribute Register 4 */ 61272209Sandrew#define CP15_ID_ISAR5(rr) p15, 0, rr, c0, c2, 5 /* Instruction Set Attribute Register 5 */ 62272209Sandrew 63272209Sandrew#define CP15_CCSIDR(rr) p15, 1, rr, c0, c0, 0 /* Cache Size ID Registers */ 64272209Sandrew#define CP15_CLIDR(rr) p15, 1, rr, c0, c0, 1 /* Cache Level ID Register */ 65272209Sandrew#define CP15_AIDR(rr) p15, 1, rr, c0, c0, 7 /* Auxiliary ID Register */ 66272209Sandrew 67272209Sandrew#define CP15_CSSELR(rr) p15, 2, rr, c0, c0, 0 /* Cache Size Selection Register */ 68272209Sandrew 69272209Sandrew/* 70272209Sandrew * CP15 C1 registers 71272209Sandrew */ 72272209Sandrew#define CP15_SCTLR(rr) p15, 0, rr, c1, c0, 0 /* System Control Register */ 73272209Sandrew#define CP15_ACTLR(rr) p15, 0, rr, c1, c0, 1 /* IMPLEMENTATION DEFINED Auxiliary Control Register */ 74272209Sandrew#define CP15_CPACR(rr) p15, 0, rr, c1, c0, 2 /* Coprocessor Access Control Register */ 75272209Sandrew 76272209Sandrew#define CP15_SCR(rr) p15, 0, rr, c1, c1, 0 /* Secure Configuration Register */ 77272209Sandrew#define CP15_SDER(rr) p15, 0, rr, c1, c1, 1 /* Secure Debug Enable Register */ 78272209Sandrew#define CP15_NSACR(rr) p15, 0, rr, c1, c1, 2 /* Non-Secure Access Control Register */ 79272209Sandrew 80272209Sandrew/* 81272209Sandrew * CP15 C2 registers 82272209Sandrew */ 83272209Sandrew#define CP15_TTBR0(rr) p15, 0, rr, c2, c0, 0 /* Translation Table Base Register 0 */ 84272209Sandrew#define CP15_TTBR1(rr) p15, 0, rr, c2, c0, 1 /* Translation Table Base Register 1 */ 85272209Sandrew#define CP15_TTBCR(rr) p15, 0, rr, c2, c0, 2 /* Translation Table Base Control Register */ 86272209Sandrew 87272209Sandrew/* 88272209Sandrew * CP15 C3 registers 89272209Sandrew */ 90272209Sandrew#define CP15_DACR(rr) p15, 0, rr, c3, c0, 0 /* Domain Access Control Register */ 91272209Sandrew 92272209Sandrew/* 93272209Sandrew * CP15 C5 registers 94272209Sandrew */ 95272209Sandrew#define CP15_DFSR(rr) p15, 0, rr, c5, c0, 0 /* Data Fault Status Register */ 96272209Sandrew 97272209Sandrew#if __ARM_ARCH >= 6 98272209Sandrew/* From ARMv6: */ 99272209Sandrew#define CP15_IFSR(rr) p15, 0, rr, c5, c0, 1 /* Instruction Fault Status Register */ 100272209Sandrew/* From ARMv7: */ 101272209Sandrew#define CP15_ADFSR(rr) p15, 0, rr, c5, c1, 0 /* Auxiliary Data Fault Status Register */ 102272209Sandrew#define CP15_AIFSR(rr) p15, 0, rr, c5, c1, 1 /* Auxiliary Instruction Fault Status Register */ 103272209Sandrew#endif 104272209Sandrew 105272209Sandrew 106272209Sandrew/* 107272209Sandrew * CP15 C6 registers 108272209Sandrew */ 109272209Sandrew#define CP15_DFAR(rr) p15, 0, rr, c6, c0, 0 /* Data Fault Address Register */ 110272209Sandrew 111272209Sandrew#if __ARM_ARCH >= 6 112272209Sandrew/* From ARMv6k: */ 113272209Sandrew#define CP15_IFAR(rr) p15, 0, rr, c6, c0, 2 /* Instruction Fault Address Register */ 114272209Sandrew#endif 115272209Sandrew 116272209Sandrew/* 117272209Sandrew * CP15 C7 registers 118272209Sandrew */ 119272209Sandrew#if __ARM_ARCH >= 6 120272209Sandrew/* From ARMv7: */ 121272209Sandrew#define CP15_ICIALLUIS p15, 0, r0, c7, c1, 0 /* Instruction cache invalidate all PoU, IS */ 122272209Sandrew#define CP15_BPIALLIS p15, 0, r0, c7, c1, 6 /* Branch predictor invalidate all IS */ 123272209Sandrew#endif 124272209Sandrew 125272209Sandrew#define CP15_PAR p15, 0, r0, c7, c4, 0 /* Physical Address Register */ 126272209Sandrew 127272209Sandrew#define CP15_ICIALLU p15, 0, r0, c7, c5, 0 /* Instruction cache invalidate all PoU */ 128272209Sandrew#define CP15_ICIMVAU(rr) p15, 0, rr, c7, c5, 1 /* Instruction cache invalidate */ 129272209Sandrew#if __ARM_ARCH >= 6 130272209Sandrew/* Deprecated in ARMv7 */ 131272209Sandrew#define CP15_CP15ISB p15, 0, r0, c7, c5, 4 /* ISB */ 132272209Sandrew#endif 133272209Sandrew#define CP15_BPIALL p15, 0, r0, c7, c5, 6 /* Branch predictor invalidate all */ 134272209Sandrew#define CP15_BPIMVA p15, 0, rr, c7, c5, 7 /* Branch predictor invalidate by MVA */ 135272209Sandrew 136272209Sandrew#if __ARM_ARCH >= 6 137272209Sandrew/* Only ARMv6: */ 138272209Sandrew#define CP15_DCIALL p15, 0, r0, c7, c6, 0 /* Data cache invalidate all */ 139272209Sandrew#endif 140272209Sandrew#define CP15_DCIMVAC(rr) p15, 0, rr, c7, c6, 1 /* Data cache invalidate by MVA PoC */ 141272209Sandrew#define CP15_DCISW(rr) p15, 0, rr, c7, c6, 2 /* Data cache invalidate by set/way */ 142272209Sandrew 143272209Sandrew#define CP15_ATS1CPR(rr) p15, 0, rr, c7, c8, 0 /* Stage 1 Current state PL1 read */ 144272209Sandrew#define CP15_ATS1CPW(rr) p15, 0, rr, c7, c8, 1 /* Stage 1 Current state PL1 write */ 145272209Sandrew#define CP15_ATS1CUR(rr) p15, 0, rr, c7, c8, 2 /* Stage 1 Current state unprivileged read */ 146272209Sandrew#define CP15_ATS1CUW(rr) p15, 0, rr, c7, c8, 3 /* Stage 1 Current state unprivileged write */ 147272209Sandrew 148272209Sandrew#if __ARM_ARCH >= 6 149272209Sandrew/* From ARMv7: */ 150272209Sandrew#define CP15_ATS12NSOPR(rr) p15, 0, rr, c7, c8, 4 /* Stages 1 and 2 Non-secure only PL1 read */ 151272209Sandrew#define CP15_ATS12NSOPW(rr) p15, 0, rr, c7, c8, 5 /* Stages 1 and 2 Non-secure only PL1 write */ 152272209Sandrew#define CP15_ATS12NSOUR(rr) p15, 0, rr, c7, c8, 6 /* Stages 1 and 2 Non-secure only unprivileged read */ 153272209Sandrew#define CP15_ATS12NSOUW(rr) p15, 0, rr, c7, c8, 7 /* Stages 1 and 2 Non-secure only unprivileged write */ 154272209Sandrew#endif 155272209Sandrew 156272209Sandrew#if __ARM_ARCH >= 6 157272209Sandrew/* Only ARMv6: */ 158272209Sandrew#define CP15_DCCALL p15, 0, r0, c7, c10, 0 /* Data cache clean all */ 159272209Sandrew#endif 160272209Sandrew#define CP15_DCCMVAC(rr) p15, 0, rr, c7, c10, 1 /* Data cache clean by MVA PoC */ 161272209Sandrew#define CP15_DCCSW(rr) p15, 0, rr, c7, c10, 2 /* Data cache clean by set/way */ 162272209Sandrew#if __ARM_ARCH >= 6 163272209Sandrew/* Only ARMv6: */ 164272209Sandrew#define CP15_CP15DSB p15, 0, r0, c7, c10, 4 /* DSB */ 165272209Sandrew#define CP15_CP15DMB p15, 0, r0, c7, c10, 5 /* DMB */ 166272209Sandrew#endif 167272209Sandrew 168272209Sandrew#if __ARM_ARCH >= 6 169272209Sandrew/* From ARMv7: */ 170272209Sandrew#define CP15_DCCMVAU(rr) p15, 0, rr, c7, c11, 1 /* Data cache clean by MVA PoU */ 171272209Sandrew#endif 172272209Sandrew 173272209Sandrew#if __ARM_ARCH >= 6 174272209Sandrew/* Only ARMv6: */ 175272209Sandrew#define CP15_DCCIALL p15, 0, r0, c7, c14, 0 /* Data cache clean and invalidate all */ 176272209Sandrew#endif 177272209Sandrew#define CP15_DCCIMVAC(rr) p15, 0, rr, c7, c14, 1 /* Data cache clean and invalidate by MVA PoC */ 178272209Sandrew#define CP15_DCCISW(rr) p15, 0, rr, c7, c14, 2 /* Data cache clean and invalidate by set/way */ 179272209Sandrew 180272209Sandrew/* 181272209Sandrew * CP15 C8 registers 182272209Sandrew */ 183272209Sandrew#if __ARM_ARCH >= 6 184272209Sandrew/* From ARMv7: */ 185272209Sandrew#define CP15_TLBIALLIS p15, 0, r0, c8, c3, 0 /* Invalidate entire unified TLB IS */ 186272209Sandrew#define CP15_TLBIMVAIS(rr) p15, 0, rr, c8, c3, 1 /* Invalidate unified TLB by MVA IS */ 187272209Sandrew#define CP15_TLBIASIDIS(rr) p15, 0, rr, c8, c3, 2 /* Invalidate unified TLB by ASID IS */ 188272209Sandrew#define CP15_TLBIMVAAIS(rr) p15, 0, rr, c8, c3, 3 /* Invalidate unified TLB by MVA, all ASID IS */ 189272209Sandrew#endif 190272209Sandrew 191272209Sandrew#define CP15_TLBIALL p15, 0, r0, c8, c7, 0 /* Invalidate entire unified TLB */ 192272209Sandrew#define CP15_TLBIMVA(rr) p15, 0, rr, c8, c7, 1 /* Invalidate unified TLB by MVA */ 193272209Sandrew#define CP15_TLBIASID(rr) p15, 0, rr, c8, c7, 2 /* Invalidate unified TLB by ASID */ 194272209Sandrew 195272209Sandrew#if __ARM_ARCH >= 6 196272209Sandrew/* From ARMv6: */ 197272209Sandrew#define CP15_TLBIMVAA(rr) p15, 0, rr, c8, c7, 3 /* Invalidate unified TLB by MVA, all ASID */ 198272209Sandrew#endif 199272209Sandrew 200272209Sandrew/* 201272209Sandrew * CP15 C10 registers 202272209Sandrew */ 203272209Sandrew/* Without LPAE this is PRRR, with LPAE it's MAIR0 */ 204272209Sandrew#define CP15_PRRR(rr) p15, 0, rr, c10, c2, 0 /* Primary Region Remap Register */ 205272209Sandrew#define CP15_MAIR0(rr) p15, 0, rr, c10, c2, 0 /* Memory Attribute Indirection Register 0 */ 206272209Sandrew/* Without LPAE this is NMRR, with LPAE it's MAIR1 */ 207272209Sandrew#define CP15_NMRR(rr) p15, 0, rr, c10, c2, 1 /* Normal Memory Remap Register */ 208272209Sandrew#define CP15_MAIR1(rr) p15, 0, rr, c10, c2, 1 /* Memory Attribute Indirection Register 1 */ 209272209Sandrew 210272209Sandrew#define CP15_AMAIR0(rr) p15, 0, rr, c10, c3, 0 /* Auxiliary Memory Attribute Indirection Register 0 */ 211272209Sandrew#define CP15_AMAIR1(rr) p15, 0, rr, c10, c3, 1 /* Auxiliary Memory Attribute Indirection Register 1 */ 212272209Sandrew 213272209Sandrew/* 214272209Sandrew * CP15 C12 registers 215272209Sandrew */ 216272209Sandrew#define CP15_VBAR(rr) p15, 0, rr, c12, c0, 0 /* Vector Base Address Register */ 217272209Sandrew#define CP15_MVBAR(rr) p15, 0, rr, c12, c0, 1 /* Monitor Vector Base Address Register */ 218272209Sandrew 219272209Sandrew#define CP15_ISR(rr) p15, 0, rr, c12, c1, 0 /* Interrupt Status Register */ 220272209Sandrew 221272209Sandrew/* 222272209Sandrew * CP15 C13 registers 223272209Sandrew */ 224272209Sandrew#define CP15_FCSEIDR(rr) p15, 0, rr, c13, c0, 0 /* FCSE Process ID Register */ 225272209Sandrew#define CP15_CONTEXTIDR(rr) p15, 0, rr, c13, c0, 1 /* Context ID Register */ 226272209Sandrew#define CP15_TPIDRURW(rr) p15, 0, rr, c13, c0, 2 /* User Read/Write Thread ID Register */ 227272209Sandrew#define CP15_TPIDRURO(rr) p15, 0, rr, c13, c0, 3 /* User Read-Only Thread ID Register */ 228272209Sandrew#define CP15_TPIDRPRW(rr) p15, 0, rr, c13, c0, 4 /* PL1 only Thread ID Register */ 229272209Sandrew 230272209Sandrew#endif /* !MACHINE_SYSREG_H */ 231