1135642Scognet/* $NetBSD: sysarch.h,v 1.5 2003/09/11 09:40:12 kleink Exp $ */ 2135642Scognet 3139735Simp/*- 4135642Scognet * Copyright (c) 1996-1997 Mark Brinicombe. 5135642Scognet * All rights reserved. 6135642Scognet * 7135642Scognet * Redistribution and use in source and binary forms, with or without 8135642Scognet * modification, are permitted provided that the following conditions 9135642Scognet * are met: 10135642Scognet * 1. Redistributions of source code must retain the above copyright 11135642Scognet * notice, this list of conditions and the following disclaimer. 12135642Scognet * 2. Redistributions in binary form must reproduce the above copyright 13135642Scognet * notice, this list of conditions and the following disclaimer in the 14135642Scognet * documentation and/or other materials provided with the distribution. 15135642Scognet * 3. All advertising materials mentioning features or use of this software 16135642Scognet * must display the following acknowledgement: 17135642Scognet * This product includes software developed by Mark Brinicombe. 18135642Scognet * 4. The name of the company nor the name of the author may be used to 19135642Scognet * endorse or promote products derived from this software without specific 20135642Scognet * prior written permission. 21135642Scognet * 22135642Scognet * THIS SOFTWARE IS PROVIDED BY AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 23135642Scognet * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 24135642Scognet * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25135642Scognet * IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 26135642Scognet * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 27135642Scognet * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 28135642Scognet * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29135642Scognet * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30135642Scognet * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31135642Scognet * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32135642Scognet * SUCH DAMAGE. 33135642Scognet */ 34135642Scognet 35135642Scognet/* $FreeBSD: stable/11/sys/arm/include/sysarch.h 360659 2020-05-05 15:29:16Z dim $ */ 36135642Scognet 37135642Scognet#ifndef _ARM_SYSARCH_H_ 38135642Scognet#define _ARM_SYSARCH_H_ 39135642Scognet 40175982Sraj#include <machine/armreg.h> 41294138Sandrew 42175982Sraj/* 43175982Sraj * The ARM_TP_ADDRESS points to a special purpose page, which is used as local 44175982Sraj * store for the ARM per-thread data and Restartable Atomic Sequences support. 45175982Sraj * Put it just above the "high" vectors' page. 46226443Scognet * The cpu_switch() code assumes ARM_RAS_START is ARM_TP_ADDRESS + 4, and 47188540Scognet * ARM_RAS_END is ARM_TP_ADDRESS + 8, so if that ever changes, be sure to 48188540Scognet * update the cpu_switch() (and cpu_throw()) code as well. 49263057Sian * In addition, code in arm/include/atomic.h and arm/arm/exception.S 50226443Scognet * assumes that ARM_RAS_END is at ARM_RAS_START+4, so be sure to update those 51249582Sgabor * if ARM_RAS_END moves in relation to ARM_RAS_START (look for occurrences 52226443Scognet * of ldr/str rm,[rn, #4]). 53175982Sraj */ 54239268Sgonzo 55239268Sgonzo/* ARM_TP_ADDRESS is needed for processors that don't support 56239268Sgonzo * the exclusive-access opcodes introduced with ARMv6K. */ 57294138Sandrew#if __ARM_ARCH <= 5 58175982Sraj#define ARM_TP_ADDRESS (ARM_VECTORS_HIGH + 0x1000) 59175982Sraj#define ARM_RAS_START (ARM_TP_ADDRESS + 4) 60175982Sraj#define ARM_RAS_END (ARM_TP_ADDRESS + 8) 61239268Sgonzo#endif 62175982Sraj 63175982Sraj#ifndef LOCORE 64234337Sandrew#ifndef __ASSEMBLER__ 65175982Sraj 66135642Scognet/* 67360659Sdim * Pickup definition of various __types. 68135642Scognet */ 69360659Sdim#include <sys/_types.h> 70135642Scognet 71135642Scognet/* 72135642Scognet * Architecture specific syscalls (arm) 73135642Scognet */ 74135642Scognet 75135642Scognet#define ARM_SYNC_ICACHE 0 76135642Scognet#define ARM_DRAIN_WRITEBUF 1 77142519Scognet#define ARM_SET_TP 2 78142519Scognet#define ARM_GET_TP 3 79325307Smmel#define ARM_GET_VFPSTATE 4 80135642Scognet 81135642Scognetstruct arm_sync_icache_args { 82360659Sdim __uintptr_t addr; /* Virtual start address */ 83360659Sdim __size_t len; /* Region size */ 84135642Scognet}; 85135642Scognet 86325307Smmelstruct arm_get_vfpstate_args { 87360659Sdim __size_t mc_vfp_size; 88325307Smmel void *mc_vfp; 89325307Smmel}; 90325307Smmel 91135642Scognet#ifndef _KERNEL 92135642Scognet__BEGIN_DECLS 93360659Sdimint arm_sync_icache(unsigned int, int); 94360659Sdimint arm_drain_writebuf(void); 95142519Scognetint sysarch(int, void *); 96135642Scognet__END_DECLS 97135642Scognet#endif 98135642Scognet 99234337Sandrew#endif /* __ASSEMBLER__ */ 100175982Sraj#endif /* LOCORE */ 101175982Sraj 102135642Scognet#endif /* !_ARM_SYSARCH_H_ */ 103