pte-v4.h revision 295751
1/* $NetBSD: pte.h,v 1.1 2001/11/23 17:39:04 thorpej Exp $ */ 2 3/*- 4 * Copyright (c) 1994 Mark Brinicombe. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by the RiscBSD team. 18 * 4. The name "RiscBSD" nor the name of the author may be used to 19 * endorse or promote products derived from this software without specific 20 * prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY RISCBSD ``AS IS'' AND ANY EXPRESS OR IMPLIED 23 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL RISCBSD OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 26 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 27 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * $FreeBSD: head/sys/arm/include/pte.h 295751 2016-02-18 09:28:16Z skra $ 35 */ 36#include <machine/acle-compat.h> 37 38#if __ARM_ARCH >= 6 39#include <machine/pte-v6.h> 40#else /* __ARM_ARCH >= 6 */ 41 42#ifndef _MACHINE_PTE_H_ 43#define _MACHINE_PTE_H_ 44 45#ifndef LOCORE 46typedef uint32_t pd_entry_t; /* page directory entry */ 47typedef uint32_t pt_entry_t; /* page table entry */ 48typedef pt_entry_t pt2_entry_t; /* compatibility with v6 */ 49#endif 50 51#define PG_FRAME 0xfffff000 52 53/* The PT_SIZE definition is misleading... A page table is only 0x400 54 * bytes long. But since VM mapping can only be done to 0x1000 a single 55 * 1KB blocks cannot be steered to a va by itself. Therefore the 56 * pages tables are allocated in blocks of 4. i.e. if a 1 KB block 57 * was allocated for a PT then the other 3KB would also get mapped 58 * whenever the 1KB was mapped. 59 */ 60 61#define PT_RSIZE 0x0400 /* Real page table size */ 62#define PT_SIZE 0x1000 63#define PD_SIZE 0x4000 64 65/* Page table types and masks */ 66#define L1_PAGE 0x01 /* L1 page table mapping */ 67#define L1_SECTION 0x02 /* L1 section mapping */ 68#define L1_FPAGE 0x03 /* L1 fine page mapping */ 69#define L1_MASK 0x03 /* Mask for L1 entry type */ 70#define L2_LPAGE 0x01 /* L2 large page (64KB) */ 71#define L2_SPAGE 0x02 /* L2 small page (4KB) */ 72#define L2_MASK 0x03 /* Mask for L2 entry type */ 73#define L2_INVAL 0x00 /* L2 invalid type */ 74 75/* 76 * The ARM MMU architecture was introduced with ARM v3 (previous ARM 77 * architecture versions used an optional off-CPU memory controller 78 * to perform address translation). 79 * 80 * The ARM MMU consists of a TLB and translation table walking logic. 81 * There is typically one TLB per memory interface (or, put another 82 * way, one TLB per software-visible cache). 83 * 84 * The ARM MMU is capable of mapping memory in the following chunks: 85 * 86 * 1M Sections (L1 table) 87 * 88 * 64K Large Pages (L2 table) 89 * 90 * 4K Small Pages (L2 table) 91 * 92 * 1K Tiny Pages (L2 table) 93 * 94 * There are two types of L2 tables: Coarse Tables and Fine Tables. 95 * Coarse Tables can map Large and Small Pages. Fine Tables can 96 * map Tiny Pages. 97 * 98 * Coarse Tables can define 4 Subpages within Large and Small pages. 99 * Subpages define different permissions for each Subpage within 100 * a Page. 101 * 102 * Coarse Tables are 1K in length. Fine tables are 4K in length. 103 * 104 * The Translation Table Base register holds the pointer to the 105 * L1 Table. The L1 Table is a 16K contiguous chunk of memory 106 * aligned to a 16K boundary. Each entry in the L1 Table maps 107 * 1M of virtual address space, either via a Section mapping or 108 * via an L2 Table. 109 * 110 * In addition, the Fast Context Switching Extension (FCSE) is available 111 * on some ARM v4 and ARM v5 processors. FCSE is a way of eliminating 112 * TLB/cache flushes on context switch by use of a smaller address space 113 * and a "process ID" that modifies the virtual address before being 114 * presented to the translation logic. 115 */ 116 117/* ARMv6 super-sections. */ 118#define L1_SUP_SIZE 0x01000000 /* 16M */ 119#define L1_SUP_OFFSET (L1_SUP_SIZE - 1) 120#define L1_SUP_FRAME (~L1_SUP_OFFSET) 121#define L1_SUP_SHIFT 24 122 123#define L1_S_SIZE 0x00100000 /* 1M */ 124#define L1_S_OFFSET (L1_S_SIZE - 1) 125#define L1_S_FRAME (~L1_S_OFFSET) 126#define L1_S_SHIFT 20 127 128#define L2_L_SIZE 0x00010000 /* 64K */ 129#define L2_L_OFFSET (L2_L_SIZE - 1) 130#define L2_L_FRAME (~L2_L_OFFSET) 131#define L2_L_SHIFT 16 132 133#define L2_S_SIZE 0x00001000 /* 4K */ 134#define L2_S_OFFSET (L2_S_SIZE - 1) 135#define L2_S_FRAME (~L2_S_OFFSET) 136#define L2_S_SHIFT 12 137 138#define L2_T_SIZE 0x00000400 /* 1K */ 139#define L2_T_OFFSET (L2_T_SIZE - 1) 140#define L2_T_FRAME (~L2_T_OFFSET) 141#define L2_T_SHIFT 10 142 143/* 144 * The NetBSD VM implementation only works on whole pages (4K), 145 * whereas the ARM MMU's Coarse tables are sized in terms of 1K 146 * (16K L1 table, 1K L2 table). 147 * 148 * So, we allocate L2 tables 4 at a time, thus yielding a 4K L2 149 * table. 150 */ 151#define L2_ADDR_BITS 0x000ff000 /* L2 PTE address bits */ 152 153#define L1_TABLE_SIZE 0x4000 /* 16K */ 154#define L2_TABLE_SIZE 0x1000 /* 4K */ 155/* 156 * The new pmap deals with the 1KB coarse L2 tables by 157 * allocating them from a pool. Until every port has been converted, 158 * keep the old L2_TABLE_SIZE define lying around. Converted ports 159 * should use L2_TABLE_SIZE_REAL until then. 160 */ 161#define L2_TABLE_SIZE_REAL 0x400 /* 1K */ 162 163/* Total number of page table entries in L2 table */ 164#define L2_PTE_NUM_TOTAL (L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)) 165 166/* 167 * ARM L1 Descriptors 168 */ 169 170#define L1_TYPE_INV 0x00 /* Invalid (fault) */ 171#define L1_TYPE_C 0x01 /* Coarse L2 */ 172#define L1_TYPE_S 0x02 /* Section */ 173#define L1_TYPE_F 0x03 /* Fine L2 */ 174#define L1_TYPE_MASK 0x03 /* mask of type bits */ 175 176/* L1 Section Descriptor */ 177#define L1_S_B 0x00000004 /* bufferable Section */ 178#define L1_S_C 0x00000008 /* cacheable Section */ 179#define L1_S_IMP 0x00000010 /* implementation defined */ 180#define L1_S_XN (1 << 4) /* execute not */ 181#define L1_S_DOM(x) ((x) << 5) /* domain */ 182#define L1_S_DOM_MASK L1_S_DOM(0xf) 183#define L1_S_AP(x) ((x) << 10) /* access permissions */ 184#define L1_S_ADDR_MASK 0xfff00000 /* phys address of section */ 185#define L1_S_TEX(x) (((x) & 0x7) << 12) /* Type Extension */ 186#define L1_S_TEX_MASK (0x7 << 12) /* Type Extension */ 187#define L1_S_APX (1 << 15) 188#define L1_SHARED (1 << 16) 189 190#define L1_S_XSCALE_P 0x00000200 /* ECC enable for this section */ 191#define L1_S_XSCALE_TEX(x) ((x) << 12) /* Type Extension */ 192 193#define L1_S_SUPERSEC ((1) << 18) /* Section is a super-section. */ 194 195/* L1 Coarse Descriptor */ 196#define L1_C_IMP0 0x00000004 /* implementation defined */ 197#define L1_C_IMP1 0x00000008 /* implementation defined */ 198#define L1_C_IMP2 0x00000010 /* implementation defined */ 199#define L1_C_DOM(x) ((x) << 5) /* domain */ 200#define L1_C_DOM_MASK L1_C_DOM(0xf) 201#define L1_C_ADDR_MASK 0xfffffc00 /* phys address of L2 Table */ 202 203#define L1_C_XSCALE_P 0x00000200 /* ECC enable for this section */ 204 205/* L1 Fine Descriptor */ 206#define L1_F_IMP0 0x00000004 /* implementation defined */ 207#define L1_F_IMP1 0x00000008 /* implementation defined */ 208#define L1_F_IMP2 0x00000010 /* implementation defined */ 209#define L1_F_DOM(x) ((x) << 5) /* domain */ 210#define L1_F_DOM_MASK L1_F_DOM(0xf) 211#define L1_F_ADDR_MASK 0xfffff000 /* phys address of L2 Table */ 212 213#define L1_F_XSCALE_P 0x00000200 /* ECC enable for this section */ 214 215/* 216 * ARM L2 Descriptors 217 */ 218 219#define L2_TYPE_INV 0x00 /* Invalid (fault) */ 220#define L2_TYPE_L 0x01 /* Large Page */ 221#define L2_TYPE_S 0x02 /* Small Page */ 222#define L2_TYPE_T 0x03 /* Tiny Page */ 223#define L2_TYPE_MASK 0x03 /* mask of type bits */ 224 225 /* 226 * This L2 Descriptor type is available on XScale processors 227 * when using a Coarse L1 Descriptor. The Extended Small 228 * Descriptor has the same format as the XScale Tiny Descriptor, 229 * but describes a 4K page, rather than a 1K page. 230 */ 231#define L2_TYPE_XSCALE_XS 0x03 /* XScale Extended Small Page */ 232 233#define L2_B 0x00000004 /* Bufferable page */ 234#define L2_C 0x00000008 /* Cacheable page */ 235#define L2_AP0(x) ((x) << 4) /* access permissions (sp 0) */ 236#define L2_AP1(x) ((x) << 6) /* access permissions (sp 1) */ 237#define L2_AP2(x) ((x) << 8) /* access permissions (sp 2) */ 238#define L2_AP3(x) ((x) << 10) /* access permissions (sp 3) */ 239 240#define L2_SHARED (1 << 10) 241#define L2_APX (1 << 9) 242#define L2_XN (1 << 0) 243#define L2_L_TEX_MASK (0x7 << 12) /* Type Extension */ 244#define L2_L_TEX(x) (((x) & 0x7) << 12) 245#define L2_S_TEX_MASK (0x7 << 6) /* Type Extension */ 246#define L2_S_TEX(x) (((x) & 0x7) << 6) 247 248#define L2_XSCALE_L_TEX(x) ((x) << 12) /* Type Extension */ 249#define L2_XSCALE_L_S(x) (1 << 15) /* Shared */ 250#define L2_XSCALE_T_TEX(x) ((x) << 6) /* Type Extension */ 251 252/* 253 * Access Permissions for L1 and L2 Descriptors. 254 */ 255#define AP_W 0x01 /* writable */ 256#define AP_REF 0x01 /* referenced flag */ 257#define AP_U 0x02 /* user */ 258 259/* 260 * Short-hand for common AP_* constants. 261 * 262 * Note: These values assume the S (System) bit is set and 263 * the R (ROM) bit is clear in CP15 register 1. 264 */ 265#define AP_KR 0x00 /* kernel read */ 266#define AP_KRW 0x01 /* kernel read/write */ 267#define AP_KRWUR 0x02 /* kernel read/write usr read */ 268#define AP_KRWURW 0x03 /* kernel read/write usr read/write */ 269 270/* 271 * Domain Types for the Domain Access Control Register. 272 */ 273#define DOMAIN_FAULT 0x00 /* no access */ 274#define DOMAIN_CLIENT 0x01 /* client */ 275#define DOMAIN_RESERVED 0x02 /* reserved */ 276#define DOMAIN_MANAGER 0x03 /* manager */ 277 278/* 279 * Type Extension bits for XScale processors. 280 * 281 * Behavior of C and B when X == 0: 282 * 283 * C B Cacheable Bufferable Write Policy Line Allocate Policy 284 * 0 0 N N - - 285 * 0 1 N Y - - 286 * 1 0 Y Y Write-through Read Allocate 287 * 1 1 Y Y Write-back Read Allocate 288 * 289 * Behavior of C and B when X == 1: 290 * C B Cacheable Bufferable Write Policy Line Allocate Policy 291 * 0 0 - - - - DO NOT USE 292 * 0 1 N Y - - 293 * 1 0 Mini-Data - - - 294 * 1 1 Y Y Write-back R/W Allocate 295 */ 296#define TEX_XSCALE_X 0x01 /* X modifies C and B */ 297#define TEX_XSCALE_E 0x02 298#define TEX_XSCALE_T 0x04 299 300/* Xscale core 3 */ 301 302/* 303 * 304 * Cache attributes with L2 present, S = 0 305 * T E X C B L1 i-cache L1 d-cache L1 DC WP L2 cacheable write coalesce 306 * 0 0 0 0 0 N N - N N 307 * 0 0 0 0 1 N N - N Y 308 * 0 0 0 1 0 Y Y WT N Y 309 * 0 0 0 1 1 Y Y WB Y Y 310 * 0 0 1 0 0 N N - Y Y 311 * 0 0 1 0 1 N N - N N 312 * 0 0 1 1 0 Y Y - - N 313 * 0 0 1 1 1 Y Y WT Y Y 314 * 0 1 0 0 0 N N - N N 315 * 0 1 0 0 1 N/A N/A N/A N/A N/A 316 * 0 1 0 1 0 N/A N/A N/A N/A N/A 317 * 0 1 0 1 1 N/A N/A N/A N/A N/A 318 * 0 1 1 X X N/A N/A N/A N/A N/A 319 * 1 X 0 0 0 N N - N Y 320 * 1 X 0 0 1 Y N WB N Y 321 * 1 X 0 1 0 Y N WT N Y 322 * 1 X 0 1 1 Y N WB Y Y 323 * 1 X 1 0 0 N N - Y Y 324 * 1 X 1 0 1 Y Y WB Y Y 325 * 1 X 1 1 0 Y Y WT Y Y 326 * 1 X 1 1 1 Y Y WB Y Y 327 * 328 * 329 * 330 * 331 * Cache attributes with L2 present, S = 1 332 * T E X C B L1 i-cache L1 d-cache L1 DC WP L2 cacheable write coalesce 333 * 0 0 0 0 0 N N - N N 334 * 0 0 0 0 1 N N - N Y 335 * 0 0 0 1 0 Y Y - N Y 336 * 0 0 0 1 1 Y Y WT Y Y 337 * 0 0 1 0 0 N N - Y Y 338 * 0 0 1 0 1 N N - N N 339 * 0 0 1 1 0 Y Y - - N 340 * 0 0 1 1 1 Y Y WT Y Y 341 * 0 1 0 0 0 N N - N N 342 * 0 1 0 0 1 N/A N/A N/A N/A N/A 343 * 0 1 0 1 0 N/A N/A N/A N/A N/A 344 * 0 1 0 1 1 N/A N/A N/A N/A N/A 345 * 0 1 1 X X N/A N/A N/A N/A N/A 346 * 1 X 0 0 0 N N - N Y 347 * 1 X 0 0 1 Y N - N Y 348 * 1 X 0 1 0 Y N - N Y 349 * 1 X 0 1 1 Y N - Y Y 350 * 1 X 1 0 0 N N - Y Y 351 * 1 X 1 0 1 Y Y WT Y Y 352 * 1 X 1 1 0 Y Y WT Y Y 353 * 1 X 1 1 1 Y Y WT Y Y 354 */ 355#endif /* !_MACHINE_PTE_H_ */ 356#endif /* __ARM_ARCH >= 6 */ 357 358/* End of pte.h */ 359