pte-v4.h revision 280712
1/* $NetBSD: pte.h,v 1.1 2001/11/23 17:39:04 thorpej Exp $ */ 2 3/*- 4 * Copyright (c) 1994 Mark Brinicombe. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by the RiscBSD team. 18 * 4. The name "RiscBSD" nor the name of the author may be used to 19 * endorse or promote products derived from this software without specific 20 * prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY RISCBSD ``AS IS'' AND ANY EXPRESS OR IMPLIED 23 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL RISCBSD OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 26 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 27 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * $FreeBSD: head/sys/arm/include/pte.h 280712 2015-03-26 21:13:53Z ian $ 35 */ 36#ifdef ARM_NEW_PMAP 37#include <machine/pte-v6.h> 38#else /* ARM_NEW_PMAP */ 39 40#ifndef _MACHINE_PTE_H_ 41#define _MACHINE_PTE_H_ 42 43#ifndef LOCORE 44typedef uint32_t pd_entry_t; /* page directory entry */ 45typedef uint32_t pt_entry_t; /* page table entry */ 46#endif 47 48#define PG_FRAME 0xfffff000 49 50/* The PT_SIZE definition is misleading... A page table is only 0x400 51 * bytes long. But since VM mapping can only be done to 0x1000 a single 52 * 1KB blocks cannot be steered to a va by itself. Therefore the 53 * pages tables are allocated in blocks of 4. i.e. if a 1 KB block 54 * was allocated for a PT then the other 3KB would also get mapped 55 * whenever the 1KB was mapped. 56 */ 57 58#define PT_RSIZE 0x0400 /* Real page table size */ 59#define PT_SIZE 0x1000 60#define PD_SIZE 0x4000 61 62/* Page table types and masks */ 63#define L1_PAGE 0x01 /* L1 page table mapping */ 64#define L1_SECTION 0x02 /* L1 section mapping */ 65#define L1_FPAGE 0x03 /* L1 fine page mapping */ 66#define L1_MASK 0x03 /* Mask for L1 entry type */ 67#define L2_LPAGE 0x01 /* L2 large page (64KB) */ 68#define L2_SPAGE 0x02 /* L2 small page (4KB) */ 69#define L2_MASK 0x03 /* Mask for L2 entry type */ 70#define L2_INVAL 0x00 /* L2 invalid type */ 71 72/* L1 and L2 address masks */ 73#define L1_ADDR_MASK 0xfffffc00 74#define L2_ADDR_MASK 0xfffff000 75 76/* 77 * The ARM MMU architecture was introduced with ARM v3 (previous ARM 78 * architecture versions used an optional off-CPU memory controller 79 * to perform address translation). 80 * 81 * The ARM MMU consists of a TLB and translation table walking logic. 82 * There is typically one TLB per memory interface (or, put another 83 * way, one TLB per software-visible cache). 84 * 85 * The ARM MMU is capable of mapping memory in the following chunks: 86 * 87 * 1M Sections (L1 table) 88 * 89 * 64K Large Pages (L2 table) 90 * 91 * 4K Small Pages (L2 table) 92 * 93 * 1K Tiny Pages (L2 table) 94 * 95 * There are two types of L2 tables: Coarse Tables and Fine Tables. 96 * Coarse Tables can map Large and Small Pages. Fine Tables can 97 * map Tiny Pages. 98 * 99 * Coarse Tables can define 4 Subpages within Large and Small pages. 100 * Subpages define different permissions for each Subpage within 101 * a Page. 102 * 103 * Coarse Tables are 1K in length. Fine tables are 4K in length. 104 * 105 * The Translation Table Base register holds the pointer to the 106 * L1 Table. The L1 Table is a 16K contiguous chunk of memory 107 * aligned to a 16K boundary. Each entry in the L1 Table maps 108 * 1M of virtual address space, either via a Section mapping or 109 * via an L2 Table. 110 * 111 * In addition, the Fast Context Switching Extension (FCSE) is available 112 * on some ARM v4 and ARM v5 processors. FCSE is a way of eliminating 113 * TLB/cache flushes on context switch by use of a smaller address space 114 * and a "process ID" that modifies the virtual address before being 115 * presented to the translation logic. 116 */ 117 118/* ARMv6 super-sections. */ 119#define L1_SUP_SIZE 0x01000000 /* 16M */ 120#define L1_SUP_OFFSET (L1_SUP_SIZE - 1) 121#define L1_SUP_FRAME (~L1_SUP_OFFSET) 122#define L1_SUP_SHIFT 24 123 124#define L1_S_SIZE 0x00100000 /* 1M */ 125#define L1_S_OFFSET (L1_S_SIZE - 1) 126#define L1_S_FRAME (~L1_S_OFFSET) 127#define L1_S_SHIFT 20 128 129#define L2_L_SIZE 0x00010000 /* 64K */ 130#define L2_L_OFFSET (L2_L_SIZE - 1) 131#define L2_L_FRAME (~L2_L_OFFSET) 132#define L2_L_SHIFT 16 133 134#define L2_S_SIZE 0x00001000 /* 4K */ 135#define L2_S_OFFSET (L2_S_SIZE - 1) 136#define L2_S_FRAME (~L2_S_OFFSET) 137#define L2_S_SHIFT 12 138 139#define L2_T_SIZE 0x00000400 /* 1K */ 140#define L2_T_OFFSET (L2_T_SIZE - 1) 141#define L2_T_FRAME (~L2_T_OFFSET) 142#define L2_T_SHIFT 10 143 144/* 145 * The NetBSD VM implementation only works on whole pages (4K), 146 * whereas the ARM MMU's Coarse tables are sized in terms of 1K 147 * (16K L1 table, 1K L2 table). 148 * 149 * So, we allocate L2 tables 4 at a time, thus yielding a 4K L2 150 * table. 151 */ 152#define L1_ADDR_BITS 0xfff00000 /* L1 PTE address bits */ 153#define L2_ADDR_BITS 0x000ff000 /* L2 PTE address bits */ 154 155#define L1_TABLE_SIZE 0x4000 /* 16K */ 156#define L2_TABLE_SIZE 0x1000 /* 4K */ 157/* 158 * The new pmap deals with the 1KB coarse L2 tables by 159 * allocating them from a pool. Until every port has been converted, 160 * keep the old L2_TABLE_SIZE define lying around. Converted ports 161 * should use L2_TABLE_SIZE_REAL until then. 162 */ 163#define L2_TABLE_SIZE_REAL 0x400 /* 1K */ 164 165/* Total number of page table entries in L2 table */ 166#define L2_PTE_NUM_TOTAL (L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)) 167 168/* 169 * ARM L1 Descriptors 170 */ 171 172#define L1_TYPE_INV 0x00 /* Invalid (fault) */ 173#define L1_TYPE_C 0x01 /* Coarse L2 */ 174#define L1_TYPE_S 0x02 /* Section */ 175#define L1_TYPE_F 0x03 /* Fine L2 */ 176#define L1_TYPE_MASK 0x03 /* mask of type bits */ 177 178/* L1 Section Descriptor */ 179#define L1_S_B 0x00000004 /* bufferable Section */ 180#define L1_S_C 0x00000008 /* cacheable Section */ 181#define L1_S_IMP 0x00000010 /* implementation defined */ 182#define L1_S_XN (1 << 4) /* execute not */ 183#define L1_S_DOM(x) ((x) << 5) /* domain */ 184#define L1_S_DOM_MASK L1_S_DOM(0xf) 185#define L1_S_AP(x) ((x) << 10) /* access permissions */ 186#define L1_S_ADDR_MASK 0xfff00000 /* phys address of section */ 187#define L1_S_TEX(x) (((x) & 0x7) << 12) /* Type Extension */ 188#define L1_S_TEX_MASK (0x7 << 12) /* Type Extension */ 189#define L1_S_APX (1 << 15) 190#define L1_SHARED (1 << 16) 191 192#define L1_S_XSCALE_P 0x00000200 /* ECC enable for this section */ 193#define L1_S_XSCALE_TEX(x) ((x) << 12) /* Type Extension */ 194 195#define L1_S_SUPERSEC ((1) << 18) /* Section is a super-section. */ 196 197/* L1 Coarse Descriptor */ 198#define L1_C_IMP0 0x00000004 /* implementation defined */ 199#define L1_C_IMP1 0x00000008 /* implementation defined */ 200#define L1_C_IMP2 0x00000010 /* implementation defined */ 201#define L1_C_DOM(x) ((x) << 5) /* domain */ 202#define L1_C_DOM_MASK L1_C_DOM(0xf) 203#define L1_C_ADDR_MASK 0xfffffc00 /* phys address of L2 Table */ 204 205#define L1_C_XSCALE_P 0x00000200 /* ECC enable for this section */ 206 207/* L1 Fine Descriptor */ 208#define L1_F_IMP0 0x00000004 /* implementation defined */ 209#define L1_F_IMP1 0x00000008 /* implementation defined */ 210#define L1_F_IMP2 0x00000010 /* implementation defined */ 211#define L1_F_DOM(x) ((x) << 5) /* domain */ 212#define L1_F_DOM_MASK L1_F_DOM(0xf) 213#define L1_F_ADDR_MASK 0xfffff000 /* phys address of L2 Table */ 214 215#define L1_F_XSCALE_P 0x00000200 /* ECC enable for this section */ 216 217/* 218 * ARM L2 Descriptors 219 */ 220 221#define L2_TYPE_INV 0x00 /* Invalid (fault) */ 222#define L2_TYPE_L 0x01 /* Large Page */ 223#define L2_TYPE_S 0x02 /* Small Page */ 224#define L2_TYPE_T 0x03 /* Tiny Page */ 225#define L2_TYPE_MASK 0x03 /* mask of type bits */ 226 227 /* 228 * This L2 Descriptor type is available on XScale processors 229 * when using a Coarse L1 Descriptor. The Extended Small 230 * Descriptor has the same format as the XScale Tiny Descriptor, 231 * but describes a 4K page, rather than a 1K page. 232 */ 233#define L2_TYPE_XSCALE_XS 0x03 /* XScale Extended Small Page */ 234 235#define L2_B 0x00000004 /* Bufferable page */ 236#define L2_C 0x00000008 /* Cacheable page */ 237#define L2_AP0(x) ((x) << 4) /* access permissions (sp 0) */ 238#define L2_AP1(x) ((x) << 6) /* access permissions (sp 1) */ 239#define L2_AP2(x) ((x) << 8) /* access permissions (sp 2) */ 240#define L2_AP3(x) ((x) << 10) /* access permissions (sp 3) */ 241 242#define L2_SHARED (1 << 10) 243#define L2_APX (1 << 9) 244#define L2_XN (1 << 0) 245#define L2_L_TEX_MASK (0x7 << 12) /* Type Extension */ 246#define L2_L_TEX(x) (((x) & 0x7) << 12) 247#define L2_S_TEX_MASK (0x7 << 6) /* Type Extension */ 248#define L2_S_TEX(x) (((x) & 0x7) << 6) 249 250#define L2_XSCALE_L_TEX(x) ((x) << 12) /* Type Extension */ 251#define L2_XSCALE_L_S(x) (1 << 15) /* Shared */ 252#define L2_XSCALE_T_TEX(x) ((x) << 6) /* Type Extension */ 253 254/* 255 * Access Permissions for L1 and L2 Descriptors. 256 */ 257#define AP_W 0x01 /* writable */ 258#define AP_REF 0x01 /* referenced flag */ 259#define AP_U 0x02 /* user */ 260 261/* 262 * Short-hand for common AP_* constants. 263 * 264 * Note: These values assume the S (System) bit is set and 265 * the R (ROM) bit is clear in CP15 register 1. 266 */ 267#define AP_KR 0x00 /* kernel read */ 268#define AP_KRW 0x01 /* kernel read/write */ 269#define AP_KRWUR 0x02 /* kernel read/write usr read */ 270#define AP_KRWURW 0x03 /* kernel read/write usr read/write */ 271 272/* 273 * Domain Types for the Domain Access Control Register. 274 */ 275#define DOMAIN_FAULT 0x00 /* no access */ 276#define DOMAIN_CLIENT 0x01 /* client */ 277#define DOMAIN_RESERVED 0x02 /* reserved */ 278#define DOMAIN_MANAGER 0x03 /* manager */ 279 280/* 281 * Type Extension bits for XScale processors. 282 * 283 * Behavior of C and B when X == 0: 284 * 285 * C B Cacheable Bufferable Write Policy Line Allocate Policy 286 * 0 0 N N - - 287 * 0 1 N Y - - 288 * 1 0 Y Y Write-through Read Allocate 289 * 1 1 Y Y Write-back Read Allocate 290 * 291 * Behavior of C and B when X == 1: 292 * C B Cacheable Bufferable Write Policy Line Allocate Policy 293 * 0 0 - - - - DO NOT USE 294 * 0 1 N Y - - 295 * 1 0 Mini-Data - - - 296 * 1 1 Y Y Write-back R/W Allocate 297 */ 298#define TEX_XSCALE_X 0x01 /* X modifies C and B */ 299#define TEX_XSCALE_E 0x02 300#define TEX_XSCALE_T 0x04 301 302/* Xscale core 3 */ 303 304/* 305 * 306 * Cache attributes with L2 present, S = 0 307 * T E X C B L1 i-cache L1 d-cache L1 DC WP L2 cacheable write coalesce 308 * 0 0 0 0 0 N N - N N 309 * 0 0 0 0 1 N N - N Y 310 * 0 0 0 1 0 Y Y WT N Y 311 * 0 0 0 1 1 Y Y WB Y Y 312 * 0 0 1 0 0 N N - Y Y 313 * 0 0 1 0 1 N N - N N 314 * 0 0 1 1 0 Y Y - - N 315 * 0 0 1 1 1 Y Y WT Y Y 316 * 0 1 0 0 0 N N - N N 317 * 0 1 0 0 1 N/A N/A N/A N/A N/A 318 * 0 1 0 1 0 N/A N/A N/A N/A N/A 319 * 0 1 0 1 1 N/A N/A N/A N/A N/A 320 * 0 1 1 X X N/A N/A N/A N/A N/A 321 * 1 X 0 0 0 N N - N Y 322 * 1 X 0 0 1 Y N WB N Y 323 * 1 X 0 1 0 Y N WT N Y 324 * 1 X 0 1 1 Y N WB Y Y 325 * 1 X 1 0 0 N N - Y Y 326 * 1 X 1 0 1 Y Y WB Y Y 327 * 1 X 1 1 0 Y Y WT Y Y 328 * 1 X 1 1 1 Y Y WB Y Y 329 * 330 * 331 * 332 * 333 * Cache attributes with L2 present, S = 1 334 * T E X C B L1 i-cache L1 d-cache L1 DC WP L2 cacheable write coalesce 335 * 0 0 0 0 0 N N - N N 336 * 0 0 0 0 1 N N - N Y 337 * 0 0 0 1 0 Y Y - N Y 338 * 0 0 0 1 1 Y Y WT Y Y 339 * 0 0 1 0 0 N N - Y Y 340 * 0 0 1 0 1 N N - N N 341 * 0 0 1 1 0 Y Y - - N 342 * 0 0 1 1 1 Y Y WT Y Y 343 * 0 1 0 0 0 N N - N N 344 * 0 1 0 0 1 N/A N/A N/A N/A N/A 345 * 0 1 0 1 0 N/A N/A N/A N/A N/A 346 * 0 1 0 1 1 N/A N/A N/A N/A N/A 347 * 0 1 1 X X N/A N/A N/A N/A N/A 348 * 1 X 0 0 0 N N - N Y 349 * 1 X 0 0 1 Y N - N Y 350 * 1 X 0 1 0 Y N - N Y 351 * 1 X 0 1 1 Y N - Y Y 352 * 1 X 1 0 0 N N - Y Y 353 * 1 X 1 0 1 Y Y WT Y Y 354 * 1 X 1 1 0 Y Y WT Y Y 355 * 1 X 1 1 1 Y Y WT Y Y 356 */ 357#endif /* !_MACHINE_PTE_H_ */ 358#endif /* !ARM_NEW_PMAP */ 359 360/* End of pte.h */ 361