pte-v4.h revision 135641 
1/*	$NetBSD: pte.h,v 1.1 2001/11/23 17:39:04 thorpej Exp $	*/
2
3/*
4 * Copyright (c) 1994 Mark Brinicombe.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 *    notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 *    notice, this list of conditions and the following disclaimer in the
14 *    documentation and/or other materials provided with the distribution.
15 * 3. All advertising materials mentioning features or use of this software
16 *    must display the following acknowledgement:
17 *	This product includes software developed by the RiscBSD team.
18 * 4. The name "RiscBSD" nor the name of the author may be used to
19 *    endorse or promote products derived from this software without specific
20 *    prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY RISCBSD ``AS IS'' AND ANY EXPRESS OR IMPLIED
23 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
25 * IN NO EVENT SHALL RISCBSD OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
26 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
27 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 * SUCH DAMAGE.
33 *
34 * $FreeBSD: head/sys/arm/include/pte.h 135641 2004-09-23 21:54:25Z cognet $
35 */
36
37#ifndef _MACHINE_PTE_H_
38#define _MACHINE_PTE_H_
39
40#define PDSHIFT		20		/* LOG2(NBPDR) */
41#define NBPD		(1 << PDSHIFT)	/* bytes/page dir */
42#define NPTEPD		(NBPD / PAGE_SIZE)
43
44#ifndef LOCORE
45typedef	uint32_t	pd_entry_t;		/* page directory entry */
46typedef	uint32_t	pt_entry_t;		/* page table entry */
47#endif
48
49#define PD_MASK		0xfff00000	/* page directory address bits */
50#define PT_MASK		0x000ff000	/* page table address bits */
51
52#define PG_FRAME	0xfffff000
53
54/* The PT_SIZE definition is misleading... A page table is only 0x400
55 * bytes long. But since VM mapping can only be done to 0x1000 a single
56 * 1KB blocks cannot be steered to a va by itself. Therefore the
57 * pages tables are allocated in blocks of 4. i.e. if a 1 KB block
58 * was allocated for a PT then the other 3KB would also get mapped
59 * whenever the 1KB was mapped.
60 */
61
62#define PT_RSIZE	0x0400		/* Real page table size */
63#define PT_SIZE		0x1000
64#define PD_SIZE		0x4000
65
66/* Page table types and masks */
67#define L1_PAGE		0x01	/* L1 page table mapping */
68#define L1_SECTION	0x02	/* L1 section mapping */
69#define L1_FPAGE	0x03	/* L1 fine page mapping */
70#define L1_MASK		0x03	/* Mask for L1 entry type */
71#define L2_LPAGE	0x01	/* L2 large page (64KB) */
72#define L2_SPAGE	0x02	/* L2 small page (4KB) */
73#define L2_MASK		0x03	/* Mask for L2 entry type */
74#define L2_INVAL	0x00	/* L2 invalid type */
75
76/* PTE construction macros */
77#define	L2_LPTE(p, a, f)	((p) | PT_AP(a) | L2_LPAGE | (f))
78#define L2_SPTE(p, a, f)	((p) | PT_AP(a) | L2_SPAGE | (f))
79#define L2_PTE(p, a)		L2_SPTE((p), (a), PT_CACHEABLE)
80#define L2_PTE_NC(p, a)		L2_SPTE((p), (a), PT_B)
81#define L2_PTE_NC_NB(p, a)	L2_SPTE((p), (a), 0)
82#define L1_SECPTE(p, a, f)	((p) | ((a) << AP_SECTION_SHIFT) | (f) \
83				| L1_SECTION | PT_U)
84
85#define L1_PTE(p)	((p) | 0x00 | L1_PAGE | PT_U)
86#define L1_SEC(p, c)	L1_SECPTE((p), AP_KRW, (c))
87
88#define L1_SEC_SIZE	(1 << PDSHIFT)
89#define L2_LPAGE_SIZE	(NBPG * 16)
90
91/* Domain types */
92#define DOMAIN_FAULT		0x00
93#define DOMAIN_CLIENT		0x01
94#define DOMAIN_RESERVED		0x02
95#define DOMAIN_MANAGER		0x03
96
97/* L1 and L2 address masks */
98#define L1_ADDR_MASK		0xfffffc00
99#define L2_ADDR_MASK		0xfffff000
100
101/*
102 * The ARM MMU architecture was introduced with ARM v3 (previous ARM
103 * architecture versions used an optional off-CPU memory controller
104 * to perform address translation).
105 *
106 * The ARM MMU consists of a TLB and translation table walking logic.
107 * There is typically one TLB per memory interface (or, put another
108 * way, one TLB per software-visible cache).
109 *
110 * The ARM MMU is capable of mapping memory in the following chunks:
111 *
112 *	1M	Sections (L1 table)
113 *
114 *	64K	Large Pages (L2 table)
115 *
116 *	4K	Small Pages (L2 table)
117 *
118 *	1K	Tiny Pages (L2 table)
119 *
120 * There are two types of L2 tables: Coarse Tables and Fine Tables.
121 * Coarse Tables can map Large and Small Pages.  Fine Tables can
122 * map Tiny Pages.
123 *
124 * Coarse Tables can define 4 Subpages within Large and Small pages.
125 * Subpages define different permissions for each Subpage within
126 * a Page.
127 *
128 * Coarse Tables are 1K in length.  Fine tables are 4K in length.
129 *
130 * The Translation Table Base register holds the pointer to the
131 * L1 Table.  The L1 Table is a 16K contiguous chunk of memory
132 * aligned to a 16K boundary.  Each entry in the L1 Table maps
133 * 1M of virtual address space, either via a Section mapping or
134 * via an L2 Table.
135 *
136 * In addition, the Fast Context Switching Extension (FCSE) is available
137 * on some ARM v4 and ARM v5 processors.  FCSE is a way of eliminating
138 * TLB/cache flushes on context switch by use of a smaller address space
139 * and a "process ID" that modifies the virtual address before being
140 * presented to the translation logic.
141 */
142
143#define	L1_S_SIZE	0x00100000	/* 1M */
144#define	L1_S_OFFSET	(L1_S_SIZE - 1)
145#define	L1_S_FRAME	(~L1_S_OFFSET)
146#define	L1_S_SHIFT	20
147
148#define	L2_L_SIZE	0x00010000	/* 64K */
149#define	L2_L_OFFSET	(L2_L_SIZE - 1)
150#define	L2_L_FRAME	(~L2_L_OFFSET)
151#define	L2_L_SHIFT	16
152
153#define	L2_S_SIZE	0x00001000	/* 4K */
154#define	L2_S_OFFSET	(L2_S_SIZE - 1)
155#define	L2_S_FRAME	(~L2_S_OFFSET)
156#define	L2_S_SHIFT	12
157
158#define	L2_T_SIZE	0x00000400	/* 1K */
159#define	L2_T_OFFSET	(L2_T_SIZE - 1)
160#define	L2_T_FRAME	(~L2_T_OFFSET)
161#define	L2_T_SHIFT	10
162
163/*
164 * The NetBSD VM implementation only works on whole pages (4K),
165 * whereas the ARM MMU's Coarse tables are sized in terms of 1K
166 * (16K L1 table, 1K L2 table).
167 *
168 * So, we allocate L2 tables 4 at a time, thus yielding a 4K L2
169 * table.
170 */
171#define	L1_ADDR_BITS	0xfff00000	/* L1 PTE address bits */
172#define	L2_ADDR_BITS	0x000ff000	/* L2 PTE address bits */
173
174#define	L1_TABLE_SIZE	0x4000		/* 16K */
175#define	L2_TABLE_SIZE	0x1000		/* 4K */
176/*
177 * The new pmap deals with the 1KB coarse L2 tables by
178 * allocating them from a pool. Until every port has been converted,
179 * keep the old L2_TABLE_SIZE define lying around. Converted ports
180 * should use L2_TABLE_SIZE_REAL until then.
181 */
182#define	L2_TABLE_SIZE_REAL	0x400	/* 1K */
183
184/*
185 * ARM L1 Descriptors
186 */
187
188#define	L1_TYPE_INV	0x00		/* Invalid (fault) */
189#define	L1_TYPE_C	0x01		/* Coarse L2 */
190#define	L1_TYPE_S	0x02		/* Section */
191#define	L1_TYPE_F	0x03		/* Fine L2 */
192#define	L1_TYPE_MASK	0x03		/* mask of type bits */
193
194/* L1 Section Descriptor */
195#define	L1_S_B		0x00000004	/* bufferable Section */
196#define	L1_S_C		0x00000008	/* cacheable Section */
197#define	L1_S_IMP	0x00000010	/* implementation defined */
198#define	L1_S_DOM(x)	((x) << 5)	/* domain */
199#define	L1_S_DOM_MASK	L1_S_DOM(0xf)
200#define	L1_S_AP(x)	((x) << 10)	/* access permissions */
201#define	L1_S_ADDR_MASK	0xfff00000	/* phys address of section */
202
203#define	L1_S_XSCALE_P	0x00000200	/* ECC enable for this section */
204#define	L1_S_XSCALE_TEX(x) ((x) << 12)	/* Type Extension */
205
206/* L1 Coarse Descriptor */
207#define	L1_C_IMP0	0x00000004	/* implementation defined */
208#define	L1_C_IMP1	0x00000008	/* implementation defined */
209#define	L1_C_IMP2	0x00000010	/* implementation defined */
210#define	L1_C_DOM(x)	((x) << 5)	/* domain */
211#define	L1_C_DOM_MASK	L1_C_DOM(0xf)
212#define	L1_C_ADDR_MASK	0xfffffc00	/* phys address of L2 Table */
213
214#define	L1_C_XSCALE_P	0x00000200	/* ECC enable for this section */
215
216/* L1 Fine Descriptor */
217#define	L1_F_IMP0	0x00000004	/* implementation defined */
218#define	L1_F_IMP1	0x00000008	/* implementation defined */
219#define	L1_F_IMP2	0x00000010	/* implementation defined */
220#define	L1_F_DOM(x)	((x) << 5)	/* domain */
221#define	L1_F_DOM_MASK	L1_F_DOM(0xf)
222#define	L1_F_ADDR_MASK	0xfffff000	/* phys address of L2 Table */
223
224#define	L1_F_XSCALE_P	0x00000200	/* ECC enable for this section */
225
226/*
227 * ARM L2 Descriptors
228 */
229
230#define	L2_TYPE_INV	0x00		/* Invalid (fault) */
231#define	L2_TYPE_L	0x01		/* Large Page */
232#define	L2_TYPE_S	0x02		/* Small Page */
233#define	L2_TYPE_T	0x03		/* Tiny Page */
234#define	L2_TYPE_MASK	0x03		/* mask of type bits */
235
236	/*
237	 * This L2 Descriptor type is available on XScale processors
238	 * when using a Coarse L1 Descriptor.  The Extended Small
239	 * Descriptor has the same format as the XScale Tiny Descriptor,
240	 * but describes a 4K page, rather than a 1K page.
241	 */
242#define	L2_TYPE_XSCALE_XS 0x03		/* XScale Extended Small Page */
243
244#define	L2_B		0x00000004	/* Bufferable page */
245#define	L2_C		0x00000008	/* Cacheable page */
246#define	L2_AP0(x)	((x) << 4)	/* access permissions (sp 0) */
247#define	L2_AP1(x)	((x) << 6)	/* access permissions (sp 1) */
248#define	L2_AP2(x)	((x) << 8)	/* access permissions (sp 2) */
249#define	L2_AP3(x)	((x) << 10)	/* access permissions (sp 3) */
250#define	L2_AP(x)	(L2_AP0(x) | L2_AP1(x) | L2_AP2(x) | L2_AP3(x))
251
252#define	L2_XSCALE_L_TEX(x) ((x) << 12)	/* Type Extension */
253#define	L2_XSCALE_T_TEX(x) ((x) << 6)	/* Type Extension */
254
255/*
256 * Access Permissions for L1 and L2 Descriptors.
257 */
258#define	AP_W		0x01		/* writable */
259#define	AP_U		0x02		/* user */
260
261/*
262 * Short-hand for common AP_* constants.
263 *
264 * Note: These values assume the S (System) bit is set and
265 * the R (ROM) bit is clear in CP15 register 1.
266 */
267#define	AP_KR		0x00		/* kernel read */
268#define	AP_KRW		0x01		/* kernel read/write */
269#define	AP_KRWUR	0x02		/* kernel read/write usr read */
270#define	AP_KRWURW	0x03		/* kernel read/write usr read/write */
271
272/*
273 * Domain Types for the Domain Access Control Register.
274 */
275#define	DOMAIN_FAULT	0x00		/* no access */
276#define	DOMAIN_CLIENT	0x01		/* client */
277#define	DOMAIN_RESERVED	0x02		/* reserved */
278#define	DOMAIN_MANAGER	0x03		/* manager */
279
280/*
281 * Type Extension bits for XScale processors.
282 *
283 * Behavior of C and B when X == 0:
284 *
285 * C B  Cacheable  Bufferable  Write Policy  Line Allocate Policy
286 * 0 0      N          N            -                 -
287 * 0 1      N          Y            -                 -
288 * 1 0      Y          Y       Write-through    Read Allocate
289 * 1 1      Y          Y        Write-back      Read Allocate
290 *
291 * Behavior of C and B when X == 1:
292 * C B  Cacheable  Bufferable  Write Policy  Line Allocate Policy
293 * 0 0      -          -            -                 -           DO NOT USE
294 * 0 1      N          Y            -                 -
295 * 1 0  Mini-Data      -            -                 -
296 * 1 1      Y          Y        Write-back       R/W Allocate
297 */
298#define	TEX_XSCALE_X	0x01		/* X modifies C and B */
299#endif /* !_MACHINE_PTE_H_ */
300
301/* End of pte.h */
302