1129198Scognet/* $NetBSD: pte.h,v 1.1 2001/11/23 17:39:04 thorpej Exp $ */ 2129198Scognet 3139735Simp/*- 4129198Scognet * Copyright (c) 1994 Mark Brinicombe. 5129198Scognet * All rights reserved. 6129198Scognet * 7129198Scognet * Redistribution and use in source and binary forms, with or without 8129198Scognet * modification, are permitted provided that the following conditions 9129198Scognet * are met: 10129198Scognet * 1. Redistributions of source code must retain the above copyright 11129198Scognet * notice, this list of conditions and the following disclaimer. 12129198Scognet * 2. Redistributions in binary form must reproduce the above copyright 13129198Scognet * notice, this list of conditions and the following disclaimer in the 14129198Scognet * documentation and/or other materials provided with the distribution. 15129198Scognet * 3. All advertising materials mentioning features or use of this software 16129198Scognet * must display the following acknowledgement: 17129198Scognet * This product includes software developed by the RiscBSD team. 18129198Scognet * 4. The name "RiscBSD" nor the name of the author may be used to 19129198Scognet * endorse or promote products derived from this software without specific 20129198Scognet * prior written permission. 21129198Scognet * 22129198Scognet * THIS SOFTWARE IS PROVIDED BY RISCBSD ``AS IS'' AND ANY EXPRESS OR IMPLIED 23129198Scognet * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 24129198Scognet * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25129198Scognet * IN NO EVENT SHALL RISCBSD OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 26129198Scognet * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 27129198Scognet * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 28129198Scognet * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29129198Scognet * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30129198Scognet * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31129198Scognet * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32129198Scognet * SUCH DAMAGE. 33129198Scognet * 34129198Scognet * $FreeBSD$ 35129198Scognet */ 36295036Smmel 37295801Sskra#ifndef _MACHINE_PTE_V4_H_ 38295801Sskra#define _MACHINE_PTE_V4_H_ 39129198Scognet 40129198Scognet#ifndef LOCORE 41129198Scognettypedef uint32_t pd_entry_t; /* page directory entry */ 42129198Scognettypedef uint32_t pt_entry_t; /* page table entry */ 43294722Sskratypedef pt_entry_t pt2_entry_t; /* compatibility with v6 */ 44129198Scognet#endif 45129198Scognet 46129198Scognet#define PG_FRAME 0xfffff000 47129198Scognet 48129198Scognet/* The PT_SIZE definition is misleading... A page table is only 0x400 49129198Scognet * bytes long. But since VM mapping can only be done to 0x1000 a single 50129198Scognet * 1KB blocks cannot be steered to a va by itself. Therefore the 51129198Scognet * pages tables are allocated in blocks of 4. i.e. if a 1 KB block 52129198Scognet * was allocated for a PT then the other 3KB would also get mapped 53129198Scognet * whenever the 1KB was mapped. 54129198Scognet */ 55236992Simp 56129198Scognet#define PT_RSIZE 0x0400 /* Real page table size */ 57129198Scognet#define PT_SIZE 0x1000 58129198Scognet#define PD_SIZE 0x4000 59129198Scognet 60129198Scognet/* Page table types and masks */ 61129198Scognet#define L1_PAGE 0x01 /* L1 page table mapping */ 62129198Scognet#define L1_SECTION 0x02 /* L1 section mapping */ 63129198Scognet#define L1_FPAGE 0x03 /* L1 fine page mapping */ 64129198Scognet#define L1_MASK 0x03 /* Mask for L1 entry type */ 65129198Scognet#define L2_LPAGE 0x01 /* L2 large page (64KB) */ 66129198Scognet#define L2_SPAGE 0x02 /* L2 small page (4KB) */ 67129198Scognet#define L2_MASK 0x03 /* Mask for L2 entry type */ 68129198Scognet#define L2_INVAL 0x00 /* L2 invalid type */ 69129198Scognet 70129198Scognet/* 71129198Scognet * The ARM MMU architecture was introduced with ARM v3 (previous ARM 72129198Scognet * architecture versions used an optional off-CPU memory controller 73129198Scognet * to perform address translation). 74129198Scognet * 75129198Scognet * The ARM MMU consists of a TLB and translation table walking logic. 76129198Scognet * There is typically one TLB per memory interface (or, put another 77129198Scognet * way, one TLB per software-visible cache). 78129198Scognet * 79129198Scognet * The ARM MMU is capable of mapping memory in the following chunks: 80129198Scognet * 81129198Scognet * 1M Sections (L1 table) 82129198Scognet * 83129198Scognet * 64K Large Pages (L2 table) 84129198Scognet * 85129198Scognet * 4K Small Pages (L2 table) 86129198Scognet * 87129198Scognet * 1K Tiny Pages (L2 table) 88129198Scognet * 89129198Scognet * There are two types of L2 tables: Coarse Tables and Fine Tables. 90129198Scognet * Coarse Tables can map Large and Small Pages. Fine Tables can 91129198Scognet * map Tiny Pages. 92129198Scognet * 93129198Scognet * Coarse Tables can define 4 Subpages within Large and Small pages. 94129198Scognet * Subpages define different permissions for each Subpage within 95129198Scognet * a Page. 96129198Scognet * 97129198Scognet * Coarse Tables are 1K in length. Fine tables are 4K in length. 98129198Scognet * 99129198Scognet * The Translation Table Base register holds the pointer to the 100129198Scognet * L1 Table. The L1 Table is a 16K contiguous chunk of memory 101129198Scognet * aligned to a 16K boundary. Each entry in the L1 Table maps 102129198Scognet * 1M of virtual address space, either via a Section mapping or 103129198Scognet * via an L2 Table. 104129198Scognet * 105129198Scognet * In addition, the Fast Context Switching Extension (FCSE) is available 106129198Scognet * on some ARM v4 and ARM v5 processors. FCSE is a way of eliminating 107129198Scognet * TLB/cache flushes on context switch by use of a smaller address space 108129198Scognet * and a "process ID" that modifies the virtual address before being 109129198Scognet * presented to the translation logic. 110129198Scognet */ 111129198Scognet 112170582Scognet/* ARMv6 super-sections. */ 113170582Scognet#define L1_SUP_SIZE 0x01000000 /* 16M */ 114170582Scognet#define L1_SUP_OFFSET (L1_SUP_SIZE - 1) 115170582Scognet#define L1_SUP_FRAME (~L1_SUP_OFFSET) 116170582Scognet#define L1_SUP_SHIFT 24 117170582Scognet 118129198Scognet#define L1_S_SIZE 0x00100000 /* 1M */ 119129198Scognet#define L1_S_OFFSET (L1_S_SIZE - 1) 120129198Scognet#define L1_S_FRAME (~L1_S_OFFSET) 121129198Scognet#define L1_S_SHIFT 20 122129198Scognet 123129198Scognet#define L2_L_SIZE 0x00010000 /* 64K */ 124129198Scognet#define L2_L_OFFSET (L2_L_SIZE - 1) 125129198Scognet#define L2_L_FRAME (~L2_L_OFFSET) 126129198Scognet#define L2_L_SHIFT 16 127129198Scognet 128129198Scognet#define L2_S_SIZE 0x00001000 /* 4K */ 129129198Scognet#define L2_S_OFFSET (L2_S_SIZE - 1) 130129198Scognet#define L2_S_FRAME (~L2_S_OFFSET) 131129198Scognet#define L2_S_SHIFT 12 132129198Scognet 133129198Scognet#define L2_T_SIZE 0x00000400 /* 1K */ 134129198Scognet#define L2_T_OFFSET (L2_T_SIZE - 1) 135129198Scognet#define L2_T_FRAME (~L2_T_OFFSET) 136129198Scognet#define L2_T_SHIFT 10 137129198Scognet 138129198Scognet/* 139129198Scognet * The NetBSD VM implementation only works on whole pages (4K), 140129198Scognet * whereas the ARM MMU's Coarse tables are sized in terms of 1K 141129198Scognet * (16K L1 table, 1K L2 table). 142129198Scognet * 143129198Scognet * So, we allocate L2 tables 4 at a time, thus yielding a 4K L2 144129198Scognet * table. 145129198Scognet */ 146129198Scognet#define L1_TABLE_SIZE 0x4000 /* 16K */ 147129198Scognet#define L2_TABLE_SIZE 0x1000 /* 4K */ 148129198Scognet/* 149129198Scognet * The new pmap deals with the 1KB coarse L2 tables by 150129198Scognet * allocating them from a pool. Until every port has been converted, 151129198Scognet * keep the old L2_TABLE_SIZE define lying around. Converted ports 152129198Scognet * should use L2_TABLE_SIZE_REAL until then. 153129198Scognet */ 154129198Scognet#define L2_TABLE_SIZE_REAL 0x400 /* 1K */ 155129198Scognet 156254918Sraj/* Total number of page table entries in L2 table */ 157254918Sraj#define L2_PTE_NUM_TOTAL (L2_TABLE_SIZE_REAL / sizeof(pt_entry_t)) 158254918Sraj 159129198Scognet/* 160129198Scognet * ARM L1 Descriptors 161129198Scognet */ 162129198Scognet 163129198Scognet#define L1_TYPE_INV 0x00 /* Invalid (fault) */ 164129198Scognet#define L1_TYPE_C 0x01 /* Coarse L2 */ 165129198Scognet#define L1_TYPE_S 0x02 /* Section */ 166129198Scognet#define L1_TYPE_F 0x03 /* Fine L2 */ 167129198Scognet#define L1_TYPE_MASK 0x03 /* mask of type bits */ 168129198Scognet 169129198Scognet/* L1 Section Descriptor */ 170129198Scognet#define L1_S_B 0x00000004 /* bufferable Section */ 171129198Scognet#define L1_S_C 0x00000008 /* cacheable Section */ 172129198Scognet#define L1_S_IMP 0x00000010 /* implementation defined */ 173254918Sraj#define L1_S_XN (1 << 4) /* execute not */ 174129198Scognet#define L1_S_DOM(x) ((x) << 5) /* domain */ 175129198Scognet#define L1_S_DOM_MASK L1_S_DOM(0xf) 176129198Scognet#define L1_S_AP(x) ((x) << 10) /* access permissions */ 177129198Scognet#define L1_S_ADDR_MASK 0xfff00000 /* phys address of section */ 178239268Sgonzo#define L1_S_TEX(x) (((x) & 0x7) << 12) /* Type Extension */ 179239268Sgonzo#define L1_S_TEX_MASK (0x7 << 12) /* Type Extension */ 180239268Sgonzo#define L1_S_APX (1 << 15) 181239268Sgonzo#define L1_SHARED (1 << 16) 182129198Scognet 183129198Scognet#define L1_S_XSCALE_P 0x00000200 /* ECC enable for this section */ 184129198Scognet#define L1_S_XSCALE_TEX(x) ((x) << 12) /* Type Extension */ 185129198Scognet 186170582Scognet#define L1_S_SUPERSEC ((1) << 18) /* Section is a super-section. */ 187170582Scognet 188129198Scognet/* L1 Coarse Descriptor */ 189129198Scognet#define L1_C_IMP0 0x00000004 /* implementation defined */ 190129198Scognet#define L1_C_IMP1 0x00000008 /* implementation defined */ 191129198Scognet#define L1_C_IMP2 0x00000010 /* implementation defined */ 192129198Scognet#define L1_C_DOM(x) ((x) << 5) /* domain */ 193129198Scognet#define L1_C_DOM_MASK L1_C_DOM(0xf) 194129198Scognet#define L1_C_ADDR_MASK 0xfffffc00 /* phys address of L2 Table */ 195129198Scognet 196129198Scognet#define L1_C_XSCALE_P 0x00000200 /* ECC enable for this section */ 197129198Scognet 198129198Scognet/* L1 Fine Descriptor */ 199129198Scognet#define L1_F_IMP0 0x00000004 /* implementation defined */ 200129198Scognet#define L1_F_IMP1 0x00000008 /* implementation defined */ 201129198Scognet#define L1_F_IMP2 0x00000010 /* implementation defined */ 202129198Scognet#define L1_F_DOM(x) ((x) << 5) /* domain */ 203129198Scognet#define L1_F_DOM_MASK L1_F_DOM(0xf) 204129198Scognet#define L1_F_ADDR_MASK 0xfffff000 /* phys address of L2 Table */ 205129198Scognet 206129198Scognet#define L1_F_XSCALE_P 0x00000200 /* ECC enable for this section */ 207129198Scognet 208129198Scognet/* 209129198Scognet * ARM L2 Descriptors 210129198Scognet */ 211129198Scognet 212129198Scognet#define L2_TYPE_INV 0x00 /* Invalid (fault) */ 213129198Scognet#define L2_TYPE_L 0x01 /* Large Page */ 214129198Scognet#define L2_TYPE_S 0x02 /* Small Page */ 215129198Scognet#define L2_TYPE_T 0x03 /* Tiny Page */ 216129198Scognet#define L2_TYPE_MASK 0x03 /* mask of type bits */ 217129198Scognet 218129198Scognet /* 219129198Scognet * This L2 Descriptor type is available on XScale processors 220129198Scognet * when using a Coarse L1 Descriptor. The Extended Small 221129198Scognet * Descriptor has the same format as the XScale Tiny Descriptor, 222129198Scognet * but describes a 4K page, rather than a 1K page. 223129198Scognet */ 224129198Scognet#define L2_TYPE_XSCALE_XS 0x03 /* XScale Extended Small Page */ 225129198Scognet 226129198Scognet#define L2_B 0x00000004 /* Bufferable page */ 227129198Scognet#define L2_C 0x00000008 /* Cacheable page */ 228129198Scognet#define L2_AP0(x) ((x) << 4) /* access permissions (sp 0) */ 229129198Scognet#define L2_AP1(x) ((x) << 6) /* access permissions (sp 1) */ 230129198Scognet#define L2_AP2(x) ((x) << 8) /* access permissions (sp 2) */ 231129198Scognet#define L2_AP3(x) ((x) << 10) /* access permissions (sp 3) */ 232129198Scognet 233239268Sgonzo#define L2_SHARED (1 << 10) 234239268Sgonzo#define L2_APX (1 << 9) 235239268Sgonzo#define L2_XN (1 << 0) 236239268Sgonzo#define L2_L_TEX_MASK (0x7 << 12) /* Type Extension */ 237239268Sgonzo#define L2_L_TEX(x) (((x) & 0x7) << 12) 238239268Sgonzo#define L2_S_TEX_MASK (0x7 << 6) /* Type Extension */ 239239268Sgonzo#define L2_S_TEX(x) (((x) & 0x7) << 6) 240239268Sgonzo 241129198Scognet#define L2_XSCALE_L_TEX(x) ((x) << 12) /* Type Extension */ 242170582Scognet#define L2_XSCALE_L_S(x) (1 << 15) /* Shared */ 243129198Scognet#define L2_XSCALE_T_TEX(x) ((x) << 6) /* Type Extension */ 244129198Scognet 245129198Scognet/* 246129198Scognet * Access Permissions for L1 and L2 Descriptors. 247129198Scognet */ 248129198Scognet#define AP_W 0x01 /* writable */ 249254918Sraj#define AP_REF 0x01 /* referenced flag */ 250129198Scognet#define AP_U 0x02 /* user */ 251129198Scognet 252129198Scognet/* 253129198Scognet * Short-hand for common AP_* constants. 254129198Scognet * 255129198Scognet * Note: These values assume the S (System) bit is set and 256129198Scognet * the R (ROM) bit is clear in CP15 register 1. 257129198Scognet */ 258129198Scognet#define AP_KR 0x00 /* kernel read */ 259129198Scognet#define AP_KRW 0x01 /* kernel read/write */ 260129198Scognet#define AP_KRWUR 0x02 /* kernel read/write usr read */ 261129198Scognet#define AP_KRWURW 0x03 /* kernel read/write usr read/write */ 262129198Scognet 263129198Scognet/* 264129198Scognet * Domain Types for the Domain Access Control Register. 265129198Scognet */ 266129198Scognet#define DOMAIN_FAULT 0x00 /* no access */ 267129198Scognet#define DOMAIN_CLIENT 0x01 /* client */ 268129198Scognet#define DOMAIN_RESERVED 0x02 /* reserved */ 269129198Scognet#define DOMAIN_MANAGER 0x03 /* manager */ 270129198Scognet 271129198Scognet/* 272129198Scognet * Type Extension bits for XScale processors. 273129198Scognet * 274129198Scognet * Behavior of C and B when X == 0: 275129198Scognet * 276129198Scognet * C B Cacheable Bufferable Write Policy Line Allocate Policy 277129198Scognet * 0 0 N N - - 278129198Scognet * 0 1 N Y - - 279129198Scognet * 1 0 Y Y Write-through Read Allocate 280129198Scognet * 1 1 Y Y Write-back Read Allocate 281129198Scognet * 282129198Scognet * Behavior of C and B when X == 1: 283129198Scognet * C B Cacheable Bufferable Write Policy Line Allocate Policy 284129198Scognet * 0 0 - - - - DO NOT USE 285129198Scognet * 0 1 N Y - - 286129198Scognet * 1 0 Mini-Data - - - 287129198Scognet * 1 1 Y Y Write-back R/W Allocate 288129198Scognet */ 289129198Scognet#define TEX_XSCALE_X 0x01 /* X modifies C and B */ 290170582Scognet#define TEX_XSCALE_E 0x02 291170582Scognet#define TEX_XSCALE_T 0x04 292170582Scognet 293170582Scognet/* Xscale core 3 */ 294170582Scognet 295170582Scognet/* 296170582Scognet * 297170582Scognet * Cache attributes with L2 present, S = 0 298170582Scognet * T E X C B L1 i-cache L1 d-cache L1 DC WP L2 cacheable write coalesce 299236992Simp * 0 0 0 0 0 N N - N N 300170582Scognet * 0 0 0 0 1 N N - N Y 301170582Scognet * 0 0 0 1 0 Y Y WT N Y 302170582Scognet * 0 0 0 1 1 Y Y WB Y Y 303170582Scognet * 0 0 1 0 0 N N - Y Y 304170582Scognet * 0 0 1 0 1 N N - N N 305170582Scognet * 0 0 1 1 0 Y Y - - N 306170582Scognet * 0 0 1 1 1 Y Y WT Y Y 307170582Scognet * 0 1 0 0 0 N N - N N 308170582Scognet * 0 1 0 0 1 N/A N/A N/A N/A N/A 309170582Scognet * 0 1 0 1 0 N/A N/A N/A N/A N/A 310170582Scognet * 0 1 0 1 1 N/A N/A N/A N/A N/A 311170582Scognet * 0 1 1 X X N/A N/A N/A N/A N/A 312170582Scognet * 1 X 0 0 0 N N - N Y 313171621Scognet * 1 X 0 0 1 Y N WB N Y 314171621Scognet * 1 X 0 1 0 Y N WT N Y 315171621Scognet * 1 X 0 1 1 Y N WB Y Y 316170582Scognet * 1 X 1 0 0 N N - Y Y 317171621Scognet * 1 X 1 0 1 Y Y WB Y Y 318170582Scognet * 1 X 1 1 0 Y Y WT Y Y 319171621Scognet * 1 X 1 1 1 Y Y WB Y Y 320170582Scognet * 321170582Scognet * 322170582Scognet * 323170582Scognet * 324170582Scognet * Cache attributes with L2 present, S = 1 325170582Scognet * T E X C B L1 i-cache L1 d-cache L1 DC WP L2 cacheable write coalesce 326236992Simp * 0 0 0 0 0 N N - N N 327170582Scognet * 0 0 0 0 1 N N - N Y 328170582Scognet * 0 0 0 1 0 Y Y - N Y 329170582Scognet * 0 0 0 1 1 Y Y WT Y Y 330170582Scognet * 0 0 1 0 0 N N - Y Y 331170582Scognet * 0 0 1 0 1 N N - N N 332170582Scognet * 0 0 1 1 0 Y Y - - N 333170582Scognet * 0 0 1 1 1 Y Y WT Y Y 334170582Scognet * 0 1 0 0 0 N N - N N 335170582Scognet * 0 1 0 0 1 N/A N/A N/A N/A N/A 336170582Scognet * 0 1 0 1 0 N/A N/A N/A N/A N/A 337170582Scognet * 0 1 0 1 1 N/A N/A N/A N/A N/A 338170582Scognet * 0 1 1 X X N/A N/A N/A N/A N/A 339170582Scognet * 1 X 0 0 0 N N - N Y 340170582Scognet * 1 X 0 0 1 Y N - N Y 341170582Scognet * 1 X 0 1 0 Y N - N Y 342170582Scognet * 1 X 0 1 1 Y N - Y Y 343170582Scognet * 1 X 1 0 0 N N - Y Y 344170582Scognet * 1 X 1 0 1 Y Y WT Y Y 345170582Scognet * 1 X 1 1 0 Y Y WT Y Y 346170582Scognet * 1 X 1 1 1 Y Y WT Y Y 347170582Scognet */ 348295801Sskra#endif /* !_MACHINE_PTE_V4_H_ */ 349129198Scognet 350129198Scognet/* End of pte.h */ 351