1239268Sgonzo/*- 2239268Sgonzo * Copyright (c) 2012 Olivier Houchard. All rights reserved. 3239268Sgonzo * 4239268Sgonzo * Redistribution and use in source and binary forms, with or without 5239268Sgonzo * modification, are permitted provided that the following conditions 6239268Sgonzo * are met: 7239268Sgonzo * 1. Redistributions of source code must retain the above copyright 8239268Sgonzo * notice, this list of conditions and the following disclaimer. 9239268Sgonzo * 2. Redistributions in binary form must reproduce the above copyright 10239268Sgonzo * notice, this list of conditions and the following disclaimer in the 11239268Sgonzo * documentation and/or other materials provided with the distribution. 12239268Sgonzo * 13239268Sgonzo * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 14239268Sgonzo * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 15239268Sgonzo * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 16239268Sgonzo * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 17239268Sgonzo * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 18239268Sgonzo * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 19239268Sgonzo * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 20239268Sgonzo * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 21239268Sgonzo * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 22239268Sgonzo * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 23239268Sgonzo */ 24239268Sgonzo 25239268Sgonzo 26239268Sgonzo/* 27239268Sgonzo * $FreeBSD$ 28239268Sgonzo */ 29239268Sgonzo 30239268Sgonzo#ifndef PL310_H_ 31239268Sgonzo#define PL310_H_ 32244914Sgonzo 33244914Sgonzo/** 34244914Sgonzo * PL310 - L2 Cache Controller register offsets. 35244914Sgonzo * 36244914Sgonzo */ 37244914Sgonzo#define PL310_CACHE_ID 0x000 38244914Sgonzo#define CACHE_ID_RELEASE_SHIFT 0 39244914Sgonzo#define CACHE_ID_RELEASE_MASK 0x3f 40244919Sandrew#define CACHE_ID_RELEASE_r0p0 0x00 41244919Sandrew#define CACHE_ID_RELEASE_r1p0 0x02 42244919Sandrew#define CACHE_ID_RELEASE_r2p0 0x04 43244919Sandrew#define CACHE_ID_RELEASE_r3p0 0x05 44244919Sandrew#define CACHE_ID_RELEASE_r3p1 0x06 45244919Sandrew#define CACHE_ID_RELEASE_r3p2 0x08 46244919Sandrew#define CACHE_ID_RELEASE_r3p3 0x09 47244914Sgonzo#define CACHE_ID_PARTNUM_SHIFT 6 48244914Sgonzo#define CACHE_ID_PARTNUM_MASK 0xf 49244919Sandrew#define CACHE_ID_PARTNUM_VALUE 0x3 50244914Sgonzo#define PL310_CACHE_TYPE 0x004 51244914Sgonzo#define PL310_CTRL 0x100 52244914Sgonzo#define CTRL_ENABLED 0x01 53244914Sgonzo#define CTRL_DISABLED 0x00 54244914Sgonzo#define PL310_AUX_CTRL 0x104 55244914Sgonzo#define AUX_CTRL_MASK 0xc0000fff 56244914Sgonzo#define AUX_CTRL_ASSOCIATIVITY_SHIFT 16 57244914Sgonzo#define AUX_CTRL_WAY_SIZE_SHIFT 17 58244914Sgonzo#define AUX_CTRL_WAY_SIZE_MASK (0x7 << 17) 59244914Sgonzo#define AUX_CTRL_SHARE_OVERRIDE (1 << 22) 60244914Sgonzo#define AUX_CTRL_NS_LOCKDOWN (1 << 26) 61244914Sgonzo#define AUX_CTRL_NS_INT_CTRL (1 << 27) 62244914Sgonzo#define AUX_CTRL_DATA_PREFETCH (1 << 28) 63244914Sgonzo#define AUX_CTRL_INSTR_PREFETCH (1 << 29) 64244914Sgonzo#define AUX_CTRL_EARLY_BRESP (1 << 30) 65265446Sian#define PL310_TAG_RAM_CTRL 0x108 66265446Sian#define PL310_DATA_RAM_CTRL 0x10C 67265446Sian#define RAM_CTRL_WRITE_SHIFT 8 68265446Sian#define RAM_CTRL_WRITE_MASK (0x7 << 8) 69265446Sian#define RAM_CTRL_READ_SHIFT 4 70265446Sian#define RAM_CTRL_READ_MASK (0x7 << 4) 71265446Sian#define RAM_CTRL_SETUP_SHIFT 0 72265446Sian#define RAM_CTRL_SETUP_MASK (0x7 << 0) 73244914Sgonzo#define PL310_EVENT_COUNTER_CTRL 0x200 74244914Sgonzo#define EVENT_COUNTER_CTRL_ENABLED (1 << 0) 75244914Sgonzo#define EVENT_COUNTER_CTRL_C0_RESET (1 << 1) 76244914Sgonzo#define EVENT_COUNTER_CTRL_C1_RESET (1 << 2) 77244914Sgonzo#define PL310_EVENT_COUNTER1_CONF 0x204 78244914Sgonzo#define PL310_EVENT_COUNTER0_CONF 0x208 79244914Sgonzo#define EVENT_COUNTER_CONF_NOINTR 0 80244914Sgonzo#define EVENT_COUNTER_CONF_INCR 1 81244914Sgonzo#define EVENT_COUNTER_CONF_OVFW 2 82244914Sgonzo#define EVENT_COUNTER_CONF_NOEV (0 << 2) 83244914Sgonzo#define EVENT_COUNTER_CONF_CO (1 << 2) 84244914Sgonzo#define EVENT_COUNTER_CONF_DRHIT (2 << 2) 85244914Sgonzo#define EVENT_COUNTER_CONF_DRREQ (3 << 2) 86244914Sgonzo#define EVENT_COUNTER_CONF_DWHIT (4 << 2) 87244914Sgonzo#define EVENT_COUNTER_CONF_DWREQ (5 << 2) 88244914Sgonzo#define EVENT_COUNTER_CONF_DWTREQ (6 << 2) 89244914Sgonzo#define EVENT_COUNTER_CONF_DIRHIT (7 << 2) 90244914Sgonzo#define EVENT_COUNTER_CONF_DIRREQ (8 << 2) 91244914Sgonzo#define EVENT_COUNTER_CONF_WA (9 << 2) 92244914Sgonzo#define PL310_EVENT_COUNTER1_VAL 0x20C 93244914Sgonzo#define PL310_EVENT_COUNTER0_VAL 0x210 94244914Sgonzo#define PL310_INTR_MASK 0x214 95244914Sgonzo#define PL310_MASKED_INTR_STAT 0x218 96244914Sgonzo#define PL310_RAW_INTR_STAT 0x21C 97244914Sgonzo#define PL310_INTR_CLEAR 0x220 98244914Sgonzo#define INTR_MASK_ALL ((1 << 9) - 1) 99244914Sgonzo#define INTR_MASK_ECNTR (1 << 0) 100244914Sgonzo#define INTR_MASK_PARRT (1 << 1) 101244914Sgonzo#define INTR_MASK_PARRD (1 << 2) 102244914Sgonzo#define INTR_MASK_ERRWT (1 << 3) 103244914Sgonzo#define INTR_MASK_ERRWD (1 << 4) 104244914Sgonzo#define INTR_MASK_ERRRT (1 << 5) 105244914Sgonzo#define INTR_MASK_ERRRD (1 << 6) 106244914Sgonzo#define INTR_MASK_SLVERR (1 << 7) 107244914Sgonzo#define INTR_MASK_DECERR (1 << 8) 108244914Sgonzo#define PL310_CACHE_SYNC 0x730 109244914Sgonzo#define PL310_INV_LINE_PA 0x770 110244914Sgonzo#define PL310_INV_WAY 0x77C 111244914Sgonzo#define PL310_CLEAN_LINE_PA 0x7B0 112244914Sgonzo#define PL310_CLEAN_LINE_IDX 0x7B8 113244914Sgonzo#define PL310_CLEAN_WAY 0x7BC 114244914Sgonzo#define PL310_CLEAN_INV_LINE_PA 0x7F0 115244914Sgonzo#define PL310_CLEAN_INV_LINE_IDX 0x7F8 116244914Sgonzo#define PL310_CLEAN_INV_WAY 0x7FC 117244914Sgonzo#define PL310_LOCKDOWN_D_WAY(x) (0x900 + ((x) * 8)) 118244914Sgonzo#define PL310_LOCKDOWN_I_WAY(x) (0x904 + ((x) * 8)) 119244914Sgonzo#define PL310_LOCKDOWN_LINE_ENABLE 0x950 120244914Sgonzo#define PL310_UNLOCK_ALL_LINES_WAY 0x954 121244914Sgonzo#define PL310_ADDR_FILTER_STAR 0xC00 122244914Sgonzo#define PL310_ADDR_FILTER_END 0xC04 123244914Sgonzo#define PL310_DEBUG_CTRL 0xF40 124265445Sian#define DEBUG_CTRL_DISABLE_LINEFILL (1 << 0) 125265445Sian#define DEBUG_CTRL_DISABLE_WRITEBACK (1 << 1) 126265446Sian#define DEBUG_CTRL_SPNIDEN (1 << 2) 127244914Sgonzo#define PL310_PREFETCH_CTRL 0xF60 128244914Sgonzo#define PREFETCH_CTRL_OFFSET_MASK (0x1f) 129244914Sgonzo#define PREFETCH_CTRL_NOTSAMEID (1 << 21) 130244914Sgonzo#define PREFETCH_CTRL_INCR_DL (1 << 23) 131244914Sgonzo#define PREFETCH_CTRL_PREFETCH_DROP (1 << 24) 132244914Sgonzo#define PREFETCH_CTRL_DL_ON_WRAP (1 << 27) 133244914Sgonzo#define PREFETCH_CTRL_DATA_PREFETCH (1 << 28) 134244914Sgonzo#define PREFETCH_CTRL_INSTR_PREFETCH (1 << 29) 135244914Sgonzo#define PREFETCH_CTRL_DL (1 << 30) 136282586Semaste#define PL310_POWER_CTRL 0xF80 137265446Sian#define POWER_CTRL_ENABLE_GATING (1 << 0) 138265446Sian#define POWER_CTRL_ENABLE_STANDBY (1 << 1) 139244914Sgonzo 140269598Sianstruct intr_config_hook; 141269598Sian 142239268Sgonzostruct pl310_softc { 143244914Sgonzo device_t sc_dev; 144239268Sgonzo struct resource *sc_mem_res; 145244914Sgonzo struct resource *sc_irq_res; 146244914Sgonzo void* sc_irq_h; 147244914Sgonzo int sc_enabled; 148244914Sgonzo struct mtx sc_mtx; 149245083Sandrew u_int sc_rtl_revision; 150269598Sian struct intr_config_hook *sc_ich; 151239268Sgonzo}; 152239268Sgonzo 153244914Sgonzo/** 154244914Sgonzo * pl310_read4 - read a 32-bit value from the PL310 registers 155244914Sgonzo * pl310_write4 - write a 32-bit value from the PL310 registers 156244914Sgonzo * @off: byte offset within the register set to read from 157244914Sgonzo * @val: the value to write into the register 158244914Sgonzo * 159290648Smmel * 160244914Sgonzo * LOCKING: 161244914Sgonzo * None 162244914Sgonzo * 163244914Sgonzo * RETURNS: 164244914Sgonzo * nothing in case of write function, if read function returns the value read. 165244914Sgonzo */ 166244914Sgonzostatic __inline uint32_t 167244914Sgonzopl310_read4(struct pl310_softc *sc, bus_size_t off) 168244914Sgonzo{ 169239268Sgonzo 170244914Sgonzo return bus_read_4(sc->sc_mem_res, off); 171244914Sgonzo} 172244914Sgonzo 173244914Sgonzostatic __inline void 174244914Sgonzopl310_write4(struct pl310_softc *sc, bus_size_t off, uint32_t val) 175244914Sgonzo{ 176244914Sgonzo 177244914Sgonzo bus_write_4(sc->sc_mem_res, off, val); 178244914Sgonzo} 179244914Sgonzo 180265446Sianvoid pl310_set_ram_latency(struct pl310_softc *sc, uint32_t which_reg, 181265446Sian uint32_t read, uint32_t write, uint32_t setup); 182265035Sian 183244914Sgonzovoid platform_pl310_init(struct pl310_softc *); 184244914Sgonzovoid platform_pl310_write_ctrl(struct pl310_softc *, uint32_t); 185244914Sgonzovoid platform_pl310_write_debug(struct pl310_softc *, uint32_t); 186244914Sgonzo 187239268Sgonzo#endif /* PL310_H_ */ 188