cpu-v6.h revision 282547
1/*- 2 * Copyright 2014 Svatopluk Kraus <onwahe@gmail.com> 3 * Copyright 2014 Michal Meloun <meloun@miracle.cz> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD: head/sys/arm/include/cpu-v6.h 282547 2015-05-06 15:17:28Z zbb $ 28 */ 29#ifndef MACHINE_CPU_V6_H 30#define MACHINE_CPU_V6_H 31 32#include "machine/atomic.h" 33#include "machine/cpufunc.h" 34#include "machine/cpuinfo.h" 35#include "machine/sysreg.h" 36 37 38#define CPU_ASID_KERNEL 0 39 40vm_offset_t dcache_wb_pou_checked(vm_offset_t, vm_size_t); 41vm_offset_t icache_inv_pou_checked(vm_offset_t, vm_size_t); 42 43/* 44 * Macros to generate CP15 (system control processor) read/write functions. 45 */ 46#define _FX(s...) #s 47 48#define _RF0(fname, aname...) \ 49static __inline register_t \ 50fname(void) \ 51{ \ 52 register_t reg; \ 53 __asm __volatile("mrc\t" _FX(aname): "=r" (reg)); \ 54 return(reg); \ 55} 56 57#define _R64F0(fname, aname) \ 58static __inline uint64_t \ 59fname(void) \ 60{ \ 61 uint64_t reg; \ 62 __asm __volatile("mrrc\t" _FX(aname): "=r" (reg)); \ 63 return(reg); \ 64} 65 66#define _WF0(fname, aname...) \ 67static __inline void \ 68fname(void) \ 69{ \ 70 __asm __volatile("mcr\t" _FX(aname)); \ 71} 72 73#define _WF1(fname, aname...) \ 74static __inline void \ 75fname(register_t reg) \ 76{ \ 77 __asm __volatile("mcr\t" _FX(aname):: "r" (reg)); \ 78} 79 80#define _W64F1(fname, aname...) \ 81static __inline void \ 82fname(uint64_t reg) \ 83{ \ 84 __asm __volatile("mcrr\t" _FX(aname):: "r" (reg)); \ 85} 86 87/* 88 * Raw CP15 maintenance operations 89 * !!! not for external use !!! 90 */ 91 92/* TLB */ 93 94_WF0(_CP15_TLBIALL, CP15_TLBIALL) /* Invalidate entire unified TLB */ 95#if __ARM_ARCH >= 7 && defined SMP 96_WF0(_CP15_TLBIALLIS, CP15_TLBIALLIS) /* Invalidate entire unified TLB IS */ 97#endif 98_WF1(_CP15_TLBIASID, CP15_TLBIASID(%0)) /* Invalidate unified TLB by ASID */ 99#if __ARM_ARCH >= 7 && defined SMP 100_WF1(_CP15_TLBIASIDIS, CP15_TLBIASIDIS(%0)) /* Invalidate unified TLB by ASID IS */ 101#endif 102_WF1(_CP15_TLBIMVAA, CP15_TLBIMVAA(%0)) /* Invalidate unified TLB by MVA, all ASID */ 103#if __ARM_ARCH >= 7 && defined SMP 104_WF1(_CP15_TLBIMVAAIS, CP15_TLBIMVAAIS(%0)) /* Invalidate unified TLB by MVA, all ASID IS */ 105#endif 106_WF1(_CP15_TLBIMVA, CP15_TLBIMVA(%0)) /* Invalidate unified TLB by MVA */ 107 108_WF1(_CP15_TTB_SET, CP15_TTBR0(%0)) 109 110/* Cache and Branch predictor */ 111 112_WF0(_CP15_BPIALL, CP15_BPIALL) /* Branch predictor invalidate all */ 113#if __ARM_ARCH >= 7 && defined SMP 114_WF0(_CP15_BPIALLIS, CP15_BPIALLIS) /* Branch predictor invalidate all IS */ 115#endif 116_WF1(_CP15_BPIMVA, CP15_BPIMVA(%0)) /* Branch predictor invalidate by MVA */ 117_WF1(_CP15_DCCIMVAC, CP15_DCCIMVAC(%0)) /* Data cache clean and invalidate by MVA PoC */ 118_WF1(_CP15_DCCISW, CP15_DCCISW(%0)) /* Data cache clean and invalidate by set/way */ 119_WF1(_CP15_DCCMVAC, CP15_DCCMVAC(%0)) /* Data cache clean by MVA PoC */ 120#if __ARM_ARCH >= 7 121_WF1(_CP15_DCCMVAU, CP15_DCCMVAU(%0)) /* Data cache clean by MVA PoU */ 122#endif 123_WF1(_CP15_DCCSW, CP15_DCCSW(%0)) /* Data cache clean by set/way */ 124_WF1(_CP15_DCIMVAC, CP15_DCIMVAC(%0)) /* Data cache invalidate by MVA PoC */ 125_WF1(_CP15_DCISW, CP15_DCISW(%0)) /* Data cache invalidate by set/way */ 126_WF0(_CP15_ICIALLU, CP15_ICIALLU) /* Instruction cache invalidate all PoU */ 127#if __ARM_ARCH >= 7 && defined SMP 128_WF0(_CP15_ICIALLUIS, CP15_ICIALLUIS) /* Instruction cache invalidate all PoU IS */ 129#endif 130_WF1(_CP15_ICIMVAU, CP15_ICIMVAU(%0)) /* Instruction cache invalidate */ 131 132/* 133 * Publicly accessible functions 134 */ 135 136/* Various control registers */ 137 138_RF0(cp15_dfsr_get, CP15_DFSR(%0)) 139_RF0(cp15_ifsr_get, CP15_IFSR(%0)) 140_WF1(cp15_prrr_set, CP15_PRRR(%0)) 141_WF1(cp15_nmrr_set, CP15_NMRR(%0)) 142_RF0(cp15_ttbr_get, CP15_TTBR0(%0)) 143_RF0(cp15_dfar_get, CP15_DFAR(%0)) 144#if __ARM_ARCH >= 7 145_RF0(cp15_ifar_get, CP15_IFAR(%0)) 146_RF0(cp15_l2ctlr_get, CP15_L2CTLR(%0)) 147#endif 148#if __ARM_ARCH >= 6 149_RF0(cp15_actlr_get, CP15_ACTLR(%0)) 150_WF1(cp15_ats1cpr_set, CP15_ATS1CPR(%0)); 151_RF0(cp15_par_get, CP15_PAR); 152_RF0(cp15_sctlr_get, CP15_SCTLR(%0)) 153#endif 154 155/*CPU id registers */ 156_RF0(cp15_midr_get, CP15_MIDR(%0)) 157_RF0(cp15_ctr_get, CP15_CTR(%0)) 158_RF0(cp15_tcmtr_get, CP15_TCMTR(%0)) 159_RF0(cp15_tlbtr_get, CP15_TLBTR(%0)) 160_RF0(cp15_mpidr_get, CP15_MPIDR(%0)) 161_RF0(cp15_revidr_get, CP15_REVIDR(%0)) 162_RF0(cp15_aidr_get, CP15_AIDR(%0)) 163_RF0(cp15_id_pfr0_get, CP15_ID_PFR0(%0)) 164_RF0(cp15_id_pfr1_get, CP15_ID_PFR1(%0)) 165_RF0(cp15_id_dfr0_get, CP15_ID_DFR0(%0)) 166_RF0(cp15_id_afr0_get, CP15_ID_AFR0(%0)) 167_RF0(cp15_id_mmfr0_get, CP15_ID_MMFR0(%0)) 168_RF0(cp15_id_mmfr1_get, CP15_ID_MMFR1(%0)) 169_RF0(cp15_id_mmfr2_get, CP15_ID_MMFR2(%0)) 170_RF0(cp15_id_mmfr3_get, CP15_ID_MMFR3(%0)) 171_RF0(cp15_id_isar0_get, CP15_ID_ISAR0(%0)) 172_RF0(cp15_id_isar1_get, CP15_ID_ISAR1(%0)) 173_RF0(cp15_id_isar2_get, CP15_ID_ISAR2(%0)) 174_RF0(cp15_id_isar3_get, CP15_ID_ISAR3(%0)) 175_RF0(cp15_id_isar4_get, CP15_ID_ISAR4(%0)) 176_RF0(cp15_id_isar5_get, CP15_ID_ISAR5(%0)) 177_RF0(cp15_cbar_get, CP15_CBAR(%0)) 178 179/* Performance Monitor registers */ 180 181#if __ARM_ARCH == 6 && defined(CPU_ARM1176) 182_RF0(cp15_pmccntr_get, CP15_PMCCNTR(%0)) 183_WF1(cp15_pmccntr_set, CP15_PMCCNTR(%0)) 184#elif __ARM_ARCH > 6 185_RF0(cp15_pmcr_get, CP15_PMCR(%0)) 186_WF1(cp15_pmcr_set, CP15_PMCR(%0)) 187_RF0(cp15_pmcnten_get, CP15_PMCNTENSET(%0)) 188_WF1(cp15_pmcnten_set, CP15_PMCNTENSET(%0)) 189_WF1(cp15_pmcnten_clr, CP15_PMCNTENCLR(%0)) 190_RF0(cp15_pmovsr_get, CP15_PMOVSR(%0)) 191_WF1(cp15_pmovsr_set, CP15_PMOVSR(%0)) 192_WF1(cp15_pmswinc_set, CP15_PMSWINC(%0)) 193_RF0(cp15_pmselr_get, CP15_PMSELR(%0)) 194_WF1(cp15_pmselr_set, CP15_PMSELR(%0)) 195_RF0(cp15_pmccntr_get, CP15_PMCCNTR(%0)) 196_WF1(cp15_pmccntr_set, CP15_PMCCNTR(%0)) 197_RF0(cp15_pmxevtyper_get, CP15_PMXEVTYPER(%0)) 198_WF1(cp15_pmxevtyper_set, CP15_PMXEVTYPER(%0)) 199_RF0(cp15_pmxevcntr_get, CP15_PMXEVCNTRR(%0)) 200_WF1(cp15_pmxevcntr_set, CP15_PMXEVCNTRR(%0)) 201_RF0(cp15_pmuserenr_get, CP15_PMUSERENR(%0)) 202_WF1(cp15_pmuserenr_set, CP15_PMUSERENR(%0)) 203_RF0(cp15_pminten_get, CP15_PMINTENSET(%0)) 204_WF1(cp15_pminten_set, CP15_PMINTENSET(%0)) 205_WF1(cp15_pminten_clr, CP15_PMINTENCLR(%0)) 206#endif 207 208_RF0(cp15_tpidrurw_get, CP15_TPIDRURW(%0)) 209_WF1(cp15_tpidrurw_set, CP15_TPIDRURW(%0)) 210_RF0(cp15_tpidruro_get, CP15_TPIDRURO(%0)) 211_WF1(cp15_tpidruro_set, CP15_TPIDRURO(%0)) 212_RF0(cp15_tpidrpwr_get, CP15_TPIDRPRW(%0)) 213_WF1(cp15_tpidrpwr_set, CP15_TPIDRPRW(%0)) 214 215/* Generic Timer registers - only use when you know the hardware is available */ 216_RF0(cp15_cntfrq_get, CP15_CNTFRQ(%0)) 217_WF1(cp15_cntfrq_set, CP15_CNTFRQ(%0)) 218_RF0(cp15_cntkctl_get, CP15_CNTKCTL(%0)) 219_WF1(cp15_cntkctl_set, CP15_CNTKCTL(%0)) 220_RF0(cp15_cntp_tval_get, CP15_CNTP_TVAL(%0)) 221_WF1(cp15_cntp_tval_set, CP15_CNTP_TVAL(%0)) 222_RF0(cp15_cntp_ctl_get, CP15_CNTP_CTL(%0)) 223_WF1(cp15_cntp_ctl_set, CP15_CNTP_CTL(%0)) 224_RF0(cp15_cntv_tval_get, CP15_CNTV_TVAL(%0)) 225_WF1(cp15_cntv_tval_set, CP15_CNTV_TVAL(%0)) 226_RF0(cp15_cntv_ctl_get, CP15_CNTV_CTL(%0)) 227_WF1(cp15_cntv_ctl_set, CP15_CNTV_CTL(%0)) 228_RF0(cp15_cnthctl_get, CP15_CNTHCTL(%0)) 229_WF1(cp15_cnthctl_set, CP15_CNTHCTL(%0)) 230_RF0(cp15_cnthp_tval_get, CP15_CNTHP_TVAL(%0)) 231_WF1(cp15_cnthp_tval_set, CP15_CNTHP_TVAL(%0)) 232_RF0(cp15_cnthp_ctl_get, CP15_CNTHP_CTL(%0)) 233_WF1(cp15_cnthp_ctl_set, CP15_CNTHP_CTL(%0)) 234 235_R64F0(cp15_cntpct_get, CP15_CNTPCT(%Q0, %R0)) 236_R64F0(cp15_cntvct_get, CP15_CNTVCT(%Q0, %R0)) 237_R64F0(cp15_cntp_cval_get, CP15_CNTP_CVAL(%Q0, %R0)) 238_W64F1(cp15_cntp_cval_set, CP15_CNTP_CVAL(%Q0, %R0)) 239_R64F0(cp15_cntv_cval_get, CP15_CNTV_CVAL(%Q0, %R0)) 240_W64F1(cp15_cntv_cval_set, CP15_CNTV_CVAL(%Q0, %R0)) 241_R64F0(cp15_cntvoff_get, CP15_CNTVOFF(%Q0, %R0)) 242_W64F1(cp15_cntvoff_set, CP15_CNTVOFF(%Q0, %R0)) 243_R64F0(cp15_cnthp_cval_get, CP15_CNTHP_CVAL(%Q0, %R0)) 244_W64F1(cp15_cnthp_cval_set, CP15_CNTHP_CVAL(%Q0, %R0)) 245 246#undef _FX 247#undef _RF0 248#undef _WF0 249#undef _WF1 250 251/* 252 * TLB maintenance operations. 253 */ 254 255/* Local (i.e. not broadcasting ) operations. */ 256 257/* Flush all TLB entries (even global). */ 258static __inline void 259tlb_flush_all_local(void) 260{ 261 262 dsb(); 263 _CP15_TLBIALL(); 264 dsb(); 265} 266 267/* Flush all not global TLB entries. */ 268static __inline void 269tlb_flush_all_ng_local(void) 270{ 271 272 dsb(); 273 _CP15_TLBIASID(CPU_ASID_KERNEL); 274 dsb(); 275} 276 277/* Flush single TLB entry (even global). */ 278static __inline void 279tlb_flush_local(vm_offset_t sva) 280{ 281 282 dsb(); 283 _CP15_TLBIMVA((sva & ~PAGE_MASK ) | CPU_ASID_KERNEL); 284 dsb(); 285} 286 287/* Flush range of TLB entries (even global). */ 288static __inline void 289tlb_flush_range_local(vm_offset_t sva, vm_size_t size) 290{ 291 vm_offset_t va; 292 vm_offset_t eva = sva + size; 293 294 dsb(); 295 for (va = sva; va < eva; va += PAGE_SIZE) 296 _CP15_TLBIMVA((va & ~PAGE_MASK ) | CPU_ASID_KERNEL); 297 dsb(); 298} 299 300/* Broadcasting operations. */ 301#if __ARM_ARCH >= 7 && defined SMP 302 303static __inline void 304tlb_flush_all(void) 305{ 306 307 dsb(); 308 _CP15_TLBIALLIS(); 309 dsb(); 310} 311 312static __inline void 313tlb_flush_all_ng(void) 314{ 315 316 dsb(); 317 _CP15_TLBIASIDIS(CPU_ASID_KERNEL); 318 dsb(); 319} 320 321static __inline void 322tlb_flush(vm_offset_t sva) 323{ 324 325 dsb(); 326 _CP15_TLBIMVAAIS(sva); 327 dsb(); 328} 329 330static __inline void 331tlb_flush_range(vm_offset_t sva, vm_size_t size) 332{ 333 vm_offset_t va; 334 vm_offset_t eva = sva + size; 335 336 dsb(); 337 for (va = sva; va < eva; va += PAGE_SIZE) 338 _CP15_TLBIMVAAIS(va); 339 dsb(); 340} 341#else /* SMP */ 342 343#define tlb_flush_all() tlb_flush_all_local() 344#define tlb_flush_all_ng() tlb_flush_all_ng_local() 345#define tlb_flush(sva) tlb_flush_local(sva) 346#define tlb_flush_range(sva, size) tlb_flush_range_local(sva, size) 347 348#endif /* SMP */ 349 350/* 351 * Cache maintenance operations. 352 */ 353 354/* Sync I and D caches to PoU */ 355static __inline void 356icache_sync(vm_offset_t sva, vm_size_t size) 357{ 358 vm_offset_t va; 359 vm_offset_t eva = sva + size; 360 361 dsb(); 362 for (va = sva; va < eva; va += cpuinfo.dcache_line_size) { 363#if __ARM_ARCH >= 7 && defined SMP 364 _CP15_DCCMVAU(va); 365#else 366 _CP15_DCCMVAC(va); 367#endif 368 } 369 dsb(); 370#if __ARM_ARCH >= 7 && defined SMP 371 _CP15_ICIALLUIS(); 372#else 373 _CP15_ICIALLU(); 374#endif 375 dsb(); 376 isb(); 377} 378 379/* Invalidate I cache */ 380static __inline void 381icache_inv_all(void) 382{ 383#if __ARM_ARCH >= 7 && defined SMP 384 _CP15_ICIALLUIS(); 385#else 386 _CP15_ICIALLU(); 387#endif 388 dsb(); 389 isb(); 390} 391 392/* Invalidate branch predictor buffer */ 393static __inline void 394bpb_inv_all(void) 395{ 396#if __ARM_ARCH >= 7 && defined SMP 397 _CP15_BPIALLIS(); 398#else 399 _CP15_BPIALL(); 400#endif 401 dsb(); 402 isb(); 403} 404 405/* Write back D-cache to PoU */ 406static __inline void 407dcache_wb_pou(vm_offset_t sva, vm_size_t size) 408{ 409 vm_offset_t va; 410 vm_offset_t eva = sva + size; 411 412 dsb(); 413 for (va = sva; va < eva; va += cpuinfo.dcache_line_size) { 414#if __ARM_ARCH >= 7 && defined SMP 415 _CP15_DCCMVAU(va); 416#else 417 _CP15_DCCMVAC(va); 418#endif 419 } 420 dsb(); 421} 422 423/* Invalidate D-cache to PoC */ 424static __inline void 425dcache_inv_poc(vm_offset_t sva, vm_paddr_t pa, vm_size_t size) 426{ 427 vm_offset_t va; 428 vm_offset_t eva = sva + size; 429 430 /* invalidate L1 first */ 431 for (va = sva; va < eva; va += cpuinfo.dcache_line_size) { 432 _CP15_DCIMVAC(va); 433 } 434 dsb(); 435 436 /* then L2 */ 437 cpu_l2cache_inv_range(pa, size); 438 dsb(); 439 440 /* then L1 again */ 441 for (va = sva; va < eva; va += cpuinfo.dcache_line_size) { 442 _CP15_DCIMVAC(va); 443 } 444 dsb(); 445} 446 447/* Write back D-cache to PoC */ 448static __inline void 449dcache_wb_poc(vm_offset_t sva, vm_paddr_t pa, vm_size_t size) 450{ 451 vm_offset_t va; 452 vm_offset_t eva = sva + size; 453 454 dsb(); 455 456 for (va = sva; va < eva; va += cpuinfo.dcache_line_size) { 457 _CP15_DCCMVAC(va); 458 } 459 dsb(); 460 461 cpu_l2cache_wb_range(pa, size); 462} 463 464/* Write back and invalidate D-cache to PoC */ 465static __inline void 466dcache_wbinv_poc(vm_offset_t sva, vm_paddr_t pa, vm_size_t size) 467{ 468 vm_offset_t va; 469 vm_offset_t eva = sva + size; 470 471 dsb(); 472 473 /* write back L1 first */ 474 for (va = sva; va < eva; va += cpuinfo.dcache_line_size) { 475 _CP15_DCCMVAC(va); 476 } 477 dsb(); 478 479 /* then write back and invalidate L2 */ 480 cpu_l2cache_wbinv_range(pa, size); 481 482 /* then invalidate L1 */ 483 for (va = sva; va < eva; va += cpuinfo.dcache_line_size) { 484 _CP15_DCIMVAC(va); 485 } 486 dsb(); 487} 488 489/* Set TTB0 register */ 490static __inline void 491cp15_ttbr_set(uint32_t reg) 492{ 493 dsb(); 494 _CP15_TTB_SET(reg); 495 dsb(); 496 _CP15_BPIALL(); 497 dsb(); 498 isb(); 499 tlb_flush_all_ng_local(); 500} 501 502#endif /* !MACHINE_CPU_V6_H */ 503