atomic.h revision 151340 
1/* $NetBSD: atomic.h,v 1.1 2002/10/19 12:22:34 bsh Exp $ */
2
3/*-
4 * Copyright (C) 2003-2004 Olivier Houchard
5 * Copyright (C) 1994-1997 Mark Brinicombe
6 * Copyright (C) 1994 Brini
7 * All rights reserved.
8 *
9 * This code is derived from software written for Brini by Mark Brinicombe
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 * 1. Redistributions of source code must retain the above copyright
15 *    notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 *    notice, this list of conditions and the following disclaimer in the
18 *    documentation and/or other materials provided with the distribution.
19 * 3. All advertising materials mentioning features or use of this software
20 *    must display the following acknowledgement:
21 *	This product includes software developed by Brini.
22 * 4. The name of Brini may not be used to endorse or promote products
23 *    derived from this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR
26 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
27 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
28 * IN NO EVENT SHALL BRINI BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
29 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
30 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
31 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
32 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
33 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
34 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 *
36 * $FreeBSD: head/sys/arm/include/atomic.h 151340 2005-10-14 18:36:49Z jhb $
37 */
38
39#ifndef	_MACHINE_ATOMIC_H_
40#define	_MACHINE_ATOMIC_H_
41
42
43
44#ifndef _LOCORE
45
46#include <sys/types.h>
47
48#ifndef I32_bit
49#define I32_bit (1 << 7)        /* IRQ disable */
50#endif
51#ifndef F32_bit
52#define F32_bit (1 << 6)        /* FIQ disable */
53#endif
54
55#define __with_interrupts_disabled(expr) \
56	do {						\
57		u_int cpsr_save, tmp;			\
58							\
59		__asm __volatile(			\
60			"mrs  %0, cpsr;"		\
61			"orr  %1, %0, %2;"		\
62			"msr  cpsr_all, %1;"		\
63			: "=r" (cpsr_save), "=r" (tmp)	\
64			: "I" (I32_bit)		\
65		        : "cc" );		\
66		(expr);				\
67		 __asm __volatile(		\
68			"msr  cpsr_all, %0"	\
69			: /* no output */	\
70			: "r" (cpsr_save)	\
71			: "cc" );		\
72	} while(0)
73
74#define ARM_RAS_START	0xe0000004
75#define ARM_RAS_END	0xe0000008
76
77static __inline uint32_t
78__swp(uint32_t val, volatile uint32_t *ptr)
79{
80	__asm __volatile("swp	%0, %2, [%3]"
81	    : "=&r" (val), "=m" (*ptr)
82	    : "r" (val), "r" (ptr), "m" (*ptr)
83	    : "memory");
84	return (val);
85}
86
87
88#ifdef _KERNEL
89static __inline void
90atomic_set_32(volatile uint32_t *address, uint32_t setmask)
91{
92	__with_interrupts_disabled(*address |= setmask);
93}
94
95static __inline void
96atomic_clear_32(volatile uint32_t *address, uint32_t clearmask)
97{
98	__with_interrupts_disabled(*address &= ~clearmask);
99}
100
101static __inline u_int32_t
102atomic_cmpset_32(volatile u_int32_t *p, volatile u_int32_t cmpval, volatile u_int32_t newval)
103{
104	int ret;
105
106	__with_interrupts_disabled(
107	 {
108	    	if (*p == cmpval) {
109			*p = newval;
110			ret = 1;
111		} else {
112			ret = 0;
113		}
114	});
115	return (ret);
116}
117
118static __inline void
119atomic_add_32(volatile u_int32_t *p, u_int32_t val)
120{
121	__with_interrupts_disabled(*p += val);
122}
123
124static __inline void
125atomic_subtract_32(volatile u_int32_t *p, u_int32_t val)
126{
127	__with_interrupts_disabled(*p -= val);
128}
129
130static __inline uint32_t
131atomic_fetchadd_32(volatile uint32_t *p, uint32_t v)
132{
133	uint32_t value;
134
135	__with_interrupts_disabled(
136	{
137	    	value = *p;
138		*p += v;
139	});
140	return (value);
141}
142
143#else /* !_KERNEL */
144
145static __inline u_int32_t
146atomic_cmpset_32(volatile u_int32_t *p, volatile u_int32_t cmpval, volatile u_int32_t newval)
147{
148	register int done, ras_start;
149
150	__asm __volatile("1:\n"
151	    "mov	%0, #0xe0000008\n"
152	    "adr	%1, 2f\n"
153	    "str	%1, [%0]\n"
154	    "adr	%1, 1b\n"
155	    "mov	%0, #0xe0000004\n"
156	    "str	%1, [%0]\n"
157	    "ldr	%1, %2\n"
158	    "cmp	%1, %3\n"
159	    "streq	%4, %2\n"
160	    "2:\n"
161	    "mov	%1, #0\n"
162	    "str	%1, [%0]\n"
163	    "moveq	%1, #1\n"
164	    "movne	%1, #0\n"
165	    : "=r" (ras_start), "=r" (done)
166	    ,"=m" (*p), "+r" (cmpval), "+r" (newval)
167	    : "m" (*p));
168	return (done);
169}
170
171static __inline void
172atomic_add_32(volatile u_int32_t *p, u_int32_t val)
173{
174	int ras_start, start;
175
176	__asm __volatile("1:\n"
177	    "mov	%0, #0xe0000008\n"
178	    "adr	%1, 2f\n"
179	    "str	%1, [%0]\n"
180	    "adr	%1, 1b\n"
181	    "mov	%0, #0xe0000004\n"
182	    "str	%1, [%0]\n"
183	    "ldr	%1, %2\n"
184	    "add	%1, %1, %3\n"
185	    "str	%1, %2\n"
186	    "2:\n"
187	    "mov	%1, #0\n"
188	    "str	%1, [%0]\n"
189	    : "=r" (ras_start), "=r" (start), "=m" (*p), "+r" (val)
190	    : "m" (*p));
191}
192
193static __inline void
194atomic_subtract_32(volatile u_int32_t *p, u_int32_t val)
195{
196	int ras_start, start;
197
198	__asm __volatile("1:\n"
199	    "mov	%0, #0xe0000008\n"
200	    "adr	%1, 2f\n"
201	    "str	%1, [%0]\n"
202	    "adr	%1, 1b\n"
203	    "mov	%0, #0xe0000004\n"
204	    "str	%1, [%0]\n"
205	    "ldr	%1, %2\n"
206	    "sub	%1, %1, %3\n"
207	    "str	%1, %2\n"
208	    "2:\n"
209	    "mov	%1, #0\n"
210	    "str	%1, [%0]\n"
211
212	    : "=r" (ras_start), "=r" (start), "=m" (*p), "+r" (val)
213	    : "m" (*p));
214}
215
216static __inline void
217atomic_set_32(volatile uint32_t *address, uint32_t setmask)
218{
219	int ras_start, start;
220
221	__asm __volatile("1:\n"
222	    "mov	%0, #0xe0000008\n"
223	    "adr	%1, 2f\n"
224	    "str	%1, [%0]\n"
225	    "adr	%1, 1b\n"
226	    "mov	%0, #0xe0000004\n"
227	    "str	%1, [%0]\n"
228	    "ldr	%1, %2\n"
229	    "orr	%1, %1, %3\n"
230	    "str	%1, %2\n"
231	    "2:\n"
232	    "mov	%1, #0\n"
233	    "str	%1, [%0]\n"
234
235	    : "=r" (ras_start), "=r" (start), "=m" (*address), "+r" (setmask)
236	    : "m" (*address));
237}
238
239static __inline void
240atomic_clear_32(volatile uint32_t *address, uint32_t clearmask)
241{
242	int ras_start, start;
243
244	__asm __volatile("1:\n"
245	    "mov	%0, #0xe0000008\n"
246	    "adr	%1, 2f\n"
247	    "str	%1, [%0]\n"
248	    "adr	%1, 1b\n"
249	    "mov	%0, #0xe0000004\n"
250	    "str	%1, [%0]\n"
251	    "ldr	%1, %2\n"
252	    "bic	%1, %1, %3\n"
253	    "str	%1, %2\n"
254	    "2:\n"
255	    "mov	%1, #0\n"
256	    "str	%1, [%0]\n"
257	    : "=r" (ras_start), "=r" (start), "=m" (*address), "+r" (clearmask)
258	    : "m" (*address));
259
260}
261
262static __inline uint32_t
263atomic_fetchadd_32(volatile uint32_t *p, uint32_t v)
264{
265	uint32_t ras_start, start;
266
267	__asm __volatile("1:\n"
268	    "mov	%0, #0xe0000008\n"
269	    "adr	%1, 2f\n"
270	    "str	%1, [%0]\n"
271	    "adr	%1, 1b\n"
272	    "mov	%0, #0xe0000004\n"
273	    "str	%1, [%0]\n"
274	    "ldr	%1, %2\n"
275	    "add	%3, %1, %3\n"
276	    "str	%3, %2\n"
277	    "2:\n"
278	    "mov	%3, #0\n"
279	    "str	%3, [%0]\n"
280	    : "=r" (ras_start), "=r" (start), "=m" (*p), "+r" (v)
281	    : "m" (*p));
282	return (start);
283}
284
285
286#endif /* _KERNEL */
287
288static __inline int
289atomic_load_32(volatile uint32_t *v)
290{
291
292	return (*v);
293}
294
295static __inline void
296atomic_store_32(volatile uint32_t *dst, uint32_t src)
297{
298	*dst = src;
299}
300
301static __inline uint32_t
302atomic_readandclear_32(volatile u_int32_t *p)
303{
304
305	return (__swp(0, p));
306}
307
308#undef __with_interrupts_disabled
309
310#endif /* _LOCORE */
311
312
313#define atomic_set_rel_int		atomic_set_32
314#define atomic_set_int			atomic_set_32
315#define atomic_readandclear_int		atomic_readandclear_32
316#define atomic_clear_int		atomic_clear_32
317#define atomic_subtract_int		atomic_subtract_32
318#define atomic_subtract_rel_int		atomic_subtract_32
319#define atomic_subtract_acq_int		atomic_subtract_32
320#define atomic_add_int			atomic_add_32
321#define atomic_add_rel_int		atomic_add_32
322#define atomic_add_acq_int		atomic_add_32
323#define atomic_cmpset_int		atomic_cmpset_32
324#define atomic_cmpset_rel_int		atomic_cmpset_32
325#define atomic_cmpset_rel_ptr		atomic_cmpset_ptr
326#define atomic_cmpset_acq_int		atomic_cmpset_32
327#define atomic_cmpset_acq_ptr		atomic_cmpset_ptr
328#define atomic_store_rel_ptr		atomic_store_ptr
329#define atomic_store_rel_int		atomic_store_32
330#define atomic_cmpset_rel_32		atomic_cmpset_32
331#define atomic_cmpset_rel_ptr		atomic_cmpset_ptr
332#define atomic_load_acq_int		atomic_load_32
333#define	atomic_clear_ptr		atomic_clear_32
334#define	atomic_store_ptr		atomic_store_32
335#define	atomic_cmpset_ptr		atomic_cmpset_32
336#define	atomic_set_ptr			atomic_set_32
337#define	atomic_fetchadd_int		atomic_fetchadd_32
338
339#endif /* _MACHINE_ATOMIC_H_ */
340