atomic.h revision 148453
1/* $NetBSD: atomic.h,v 1.1 2002/10/19 12:22:34 bsh Exp $ */ 2 3/*- 4 * Copyright (C) 2003-2004 Olivier Houchard 5 * Copyright (C) 1994-1997 Mark Brinicombe 6 * Copyright (C) 1994 Brini 7 * All rights reserved. 8 * 9 * This code is derived from software written for Brini by Mark Brinicombe 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by Brini. 22 * 4. The name of Brini may not be used to endorse or promote products 23 * derived from this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR 26 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 27 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 28 * IN NO EVENT SHALL BRINI BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 29 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 30 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 31 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 32 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 33 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 34 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 * 36 * $FreeBSD: head/sys/arm/include/atomic.h 148453 2005-07-27 20:01:45Z jhb $ 37 */ 38 39#ifndef _MACHINE_ATOMIC_H_ 40#define _MACHINE_ATOMIC_H_ 41 42 43 44#ifndef _LOCORE 45 46#include <sys/types.h> 47 48#ifndef I32_bit 49#define I32_bit (1 << 7) /* IRQ disable */ 50#endif 51#ifndef F32_bit 52#define F32_bit (1 << 6) /* FIQ disable */ 53#endif 54 55#define __with_interrupts_disabled(expr) \ 56 do { \ 57 u_int cpsr_save, tmp; \ 58 \ 59 __asm __volatile( \ 60 "mrs %0, cpsr;" \ 61 "orr %1, %0, %2;" \ 62 "msr cpsr_all, %1;" \ 63 : "=r" (cpsr_save), "=r" (tmp) \ 64 : "I" (I32_bit) \ 65 : "cc" ); \ 66 (expr); \ 67 __asm __volatile( \ 68 "msr cpsr_all, %0" \ 69 : /* no output */ \ 70 : "r" (cpsr_save) \ 71 : "cc" ); \ 72 } while(0) 73 74#define ARM_RAS_START 0xe0000004 75#define ARM_RAS_END 0xe0000008 76 77static __inline uint32_t 78__swp(uint32_t val, volatile uint32_t *ptr) 79{ 80 __asm __volatile("swp %0, %2, [%3]" 81 : "=&r" (val), "=m" (*ptr) 82 : "r" (val) , "r" (ptr), "m" (*ptr) 83 : "memory"); 84 return (val); 85} 86 87 88#ifdef _KERNEL 89static __inline void 90atomic_set_32(volatile uint32_t *address, uint32_t setmask) 91{ 92 __with_interrupts_disabled(*address |= setmask); 93} 94 95static __inline void 96atomic_clear_32(volatile uint32_t *address, uint32_t clearmask) 97{ 98 __with_interrupts_disabled(*address &= ~clearmask); 99} 100 101static __inline u_int32_t 102atomic_cmpset_32(volatile u_int32_t *p, volatile u_int32_t cmpval, volatile u_int32_t newval) 103{ 104 int ret; 105 106 __with_interrupts_disabled( 107 { 108 if (*p == cmpval) { 109 *p = newval; 110 ret = 1; 111 } else { 112 ret = 0; 113 } 114 }); 115 return (ret); 116} 117 118static __inline void 119atomic_add_32(volatile u_int32_t *p, u_int32_t val) 120{ 121 __with_interrupts_disabled(*p += val); 122} 123 124static __inline void 125atomic_subtract_32(volatile u_int32_t *p, u_int32_t val) 126{ 127 __with_interrupts_disabled(*p -= val); 128} 129 130#else /* !_KERNEL */ 131 132static __inline u_int32_t 133atomic_cmpset_32(volatile u_int32_t *p, volatile u_int32_t cmpval, volatile u_int32_t newval) 134{ 135 register int done, ras_start; 136 137 __asm __volatile("1:\n" 138 "mov %0, #0xe0000008\n" 139 "adr %1, 2f\n" 140 "str %1, [%0]\n" 141 "adr %1, 1b\n" 142 "mov %0, #0xe0000004\n" 143 "str %1, [%0]\n" 144 "ldr %1, [%2]\n" 145 "cmp %1, %3\n" 146 "streq %4, [%2]\n" 147 "2:\n" 148 "mov %1, #0\n" 149 "str %1, [%0]\n" 150 "moveq %1, #1\n" 151 "movne %1, #0\n" 152 : "=r" (ras_start), "=r" (done) 153 ,"+r" (p), "+r" (cmpval), "+r" (newval)); 154 return (done); 155} 156 157static __inline void 158atomic_add_32(volatile u_int32_t *p, u_int32_t val) 159{ 160 int ras_start, start; 161 162 __asm __volatile("1:\n" 163 "mov %0, #0xe0000008\n" 164 "adr %1, 2f\n" 165 "str %1, [%0]\n" 166 "adr %1, 1b\n" 167 "mov %0, #0xe0000004\n" 168 "str %1, [%0]\n" 169 "ldr %1, [%2]\n" 170 "add %1, %1, %3\n" 171 "str %1, [%2]\n" 172 "2:\n" 173 "mov %1, #0\n" 174 "str %1, [%0]\n" 175 : "=r" (ras_start), "=r" (start), "+r" (p), "+r" (val)); 176} 177 178static __inline void 179atomic_subtract_32(volatile u_int32_t *p, u_int32_t val) 180{ 181 int ras_start, start; 182 183 __asm __volatile("1:\n" 184 "mov %0, #0xe0000008\n" 185 "adr %1, 2f\n" 186 "str %1, [%0]\n" 187 "adr %1, 1b\n" 188 "mov %0, #0xe0000004\n" 189 "str %1, [%0]\n" 190 "ldr %1, [%2]\n" 191 "sub %1, %1, %3\n" 192 "str %1, [%2]\n" 193 "2:\n" 194 "mov %1, #0\n" 195 "str %1, [%0]\n" 196 197 : "=r" (ras_start), "=r" (start), "+r" (p), "+r" (val)); 198} 199 200static __inline void 201atomic_set_32(volatile uint32_t *address, uint32_t setmask) 202{ 203 int ras_start, start; 204 205 __asm __volatile("1:\n" 206 "mov %0, #0xe0000008\n" 207 "adr %1, 2f\n" 208 "str %1, [%0]\n" 209 "adr %1, 1b\n" 210 "mov %0, #0xe0000004\n" 211 "str %1, [%0]\n" 212 "ldr %1, [%2]\n" 213 "orr %1, %1, %3\n" 214 "str %1, [%2]\n" 215 "2:\n" 216 "mov %1, #0\n" 217 "str %1, [%0]\n" 218 219 : "=r" (ras_start), "=r" (start), "+r" (address), "+r" (setmask)); 220} 221 222static __inline void 223atomic_clear_32(volatile uint32_t *address, uint32_t clearmask) 224{ 225 int ras_start, start; 226 227 __asm __volatile("1:\n" 228 "mov %0, #0xe0000008\n" 229 "adr %1, 2f\n" 230 "str %1, [%0]\n" 231 "adr %1, 1b\n" 232 "mov %0, #0xe0000004\n" 233 "str %1, [%0]\n" 234 "ldr %1, [%2]\n" 235 "bic %1, %1, %3\n" 236 "str %1, [%2]\n" 237 "2:\n" 238 "mov %1, #0\n" 239 "str %1, [%0]\n" 240 : "=r" (ras_start), "=r" (start), "+r" (address), "+r" (clearmask)); 241 242} 243#endif /* _KERNEL */ 244 245static __inline int 246atomic_load_32(volatile uint32_t *v) 247{ 248 249 return (*v); 250} 251 252static __inline void 253atomic_store_32(volatile uint32_t *dst, uint32_t src) 254{ 255 *dst = src; 256} 257 258static __inline uint32_t 259atomic_readandclear_32(volatile u_int32_t *p) 260{ 261 262 return (__swp(0, p)); 263} 264 265#undef __with_interrupts_disabled 266 267#endif /* _LOCORE */ 268 269 270#define atomic_set_rel_int atomic_set_32 271#define atomic_set_int atomic_set_32 272#define atomic_readandclear_int atomic_readandclear_32 273#define atomic_clear_int atomic_clear_32 274#define atomic_subtract_int atomic_subtract_32 275#define atomic_subtract_rel_int atomic_subtract_32 276#define atomic_subtract_acq_int atomic_subtract_32 277#define atomic_add_int atomic_add_32 278#define atomic_add_rel_int atomic_add_32 279#define atomic_add_acq_int atomic_add_32 280#define atomic_cmpset_int atomic_cmpset_32 281#define atomic_cmpset_rel_int atomic_cmpset_32 282#define atomic_cmpset_rel_ptr atomic_cmpset_ptr 283#define atomic_cmpset_acq_int atomic_cmpset_32 284#define atomic_cmpset_acq_ptr atomic_cmpset_ptr 285#define atomic_store_rel_ptr atomic_store_ptr 286#define atomic_store_rel_int atomic_store_32 287#define atomic_cmpset_rel_32 atomic_cmpset_32 288#define atomic_cmpset_rel_ptr atomic_cmpset_ptr 289#define atomic_load_acq_int atomic_load_32 290#define atomic_clear_ptr atomic_clear_32 291#define atomic_store_ptr atomic_store_32 292#define atomic_cmpset_ptr atomic_cmpset_32 293#define atomic_set_ptr atomic_set_32 294 295#endif /* _MACHINE_ATOMIC_H_ */ 296