vf_uart.c revision 258057 
1/*-
2 * Copyright (c) 2013 Ruslan Bukin <br@bsdpad.com>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 *    notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 *    notice, this list of conditions and the following disclaimer in the
12 *    documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27/*
28 * Vybrid Family Universal Asynchronous Receiver/Transmitter
29 * Chapter 49, Vybrid Reference Manual, Rev. 5, 07/2013
30 */
31
32#include <sys/cdefs.h>
33__FBSDID("$FreeBSD: head/sys/arm/freescale/vybrid/vf_uart.c 258057 2013-11-12 18:02:56Z br $");
34
35#include "opt_ddb.h"
36
37#include <sys/param.h>
38#include <sys/systm.h>
39#include <sys/bus.h>
40#include <sys/conf.h>
41#include <sys/kdb.h>
42#include <machine/bus.h>
43#include <machine/fdt.h>
44
45#include <dev/uart/uart.h>
46#include <dev/uart/uart_cpu.h>
47#include <dev/uart/uart_bus.h>
48
49#include "uart_if.h"
50
51#define	UART_BDH	0x00	/* Baud Rate Registers: High */
52#define	UART_BDL	0x01	/* Baud Rate Registers: Low */
53#define	UART_C1		0x02	/* Control Register 1 */
54#define	UART_C2		0x03	/* Control Register 2 */
55#define	UART_S1		0x04	/* Status Register 1 */
56#define	UART_S2		0x05	/* Status Register 2 */
57#define	UART_C3		0x06	/* Control Register 3 */
58#define	UART_D		0x07	/* Data Register */
59#define	UART_MA1	0x08	/* Match Address Registers 1 */
60#define	UART_MA2	0x09	/* Match Address Registers 2 */
61#define	UART_C4		0x0A	/* Control Register 4 */
62#define	UART_C5		0x0B	/* Control Register 5 */
63#define	UART_ED		0x0C	/* Extended Data Register */
64#define	UART_MODEM	0x0D	/* Modem Register */
65#define	UART_IR		0x0E	/* Infrared Register */
66#define	UART_PFIFO	0x10	/* FIFO Parameters */
67#define	UART_CFIFO	0x11	/* FIFO Control Register */
68#define	UART_SFIFO	0x12	/* FIFO Status Register */
69#define	UART_TWFIFO	0x13	/* FIFO Transmit Watermark */
70#define	UART_TCFIFO	0x14	/* FIFO Transmit Count */
71#define	UART_RWFIFO	0x15	/* FIFO Receive Watermark */
72#define	UART_RCFIFO	0x16	/* FIFO Receive Count */
73#define	UART_C7816	0x18	/* 7816 Control Register */
74#define	UART_IE7816	0x19	/* 7816 Interrupt Enable Register */
75#define	UART_IS7816	0x1A	/* 7816 Interrupt Status Register */
76#define	UART_WP7816T0	0x1B	/* 7816 Wait Parameter Register */
77#define	UART_WP7816T1	0x1B	/* 7816 Wait Parameter Register */
78#define	UART_WN7816	0x1C	/* 7816 Wait N Register */
79#define	UART_WF7816	0x1D	/* 7816 Wait FD Register */
80#define	UART_ET7816	0x1E	/* 7816 Error Threshold Register */
81#define	UART_TL7816	0x1F	/* 7816 Transmit Length Register */
82#define	UART_C6		0x21	/* CEA709.1-B Control Register 6 */
83#define	UART_PCTH	0x22	/* CEA709.1-B Packet Cycle Time Counter High */
84#define	UART_PCTL	0x23	/* CEA709.1-B Packet Cycle Time Counter Low */
85#define	UART_B1T	0x24	/* CEA709.1-B Beta1 Timer */
86#define	UART_SDTH	0x25	/* CEA709.1-B Secondary Delay Timer High */
87#define	UART_SDTL	0x26	/* CEA709.1-B Secondary Delay Timer Low */
88#define	UART_PRE	0x27	/* CEA709.1-B Preamble */
89#define	UART_TPL	0x28	/* CEA709.1-B Transmit Packet Length */
90#define	UART_IE		0x29	/* CEA709.1-B Interrupt Enable Register */
91#define	UART_WB		0x2A	/* CEA709.1-B WBASE */
92#define	UART_S3		0x2B	/* CEA709.1-B Status Register */
93#define	UART_S4		0x2C	/* CEA709.1-B Status Register */
94#define	UART_RPL	0x2D	/* CEA709.1-B Received Packet Length */
95#define	UART_RPREL	0x2E	/* CEA709.1-B Received Preamble Length */
96#define	UART_CPW	0x2F	/* CEA709.1-B Collision Pulse Width */
97#define	UART_RIDT	0x30	/* CEA709.1-B Receive Indeterminate Time */
98#define	UART_TIDT	0x31	/* CEA709.1-B Transmit Indeterminate Time */
99
100#define	UART_C2_TE	(1 << 3)	/* Transmitter Enable */
101#define	UART_C2_TIE	(1 << 7)	/* Transmitter Interrupt Enable */
102#define	UART_C2_RE	(1 << 2)	/* Receiver Enable */
103#define	UART_C2_RIE	(1 << 5)	/* Receiver Interrupt Enable */
104#define	UART_S1_TDRE	(1 << 7)	/* Transmit Data Register Empty Flag */
105#define	UART_S1_RDRF	(1 << 5)	/* Receive Data Register Full Flag */
106#define	UART_S2_LBKDIF	(1 << 7)	/* LIN Break Detect Interrupt Flag */
107
108#define	UART_C4_BRFA	0x1f	/* Baud Rate Fine Adjust */
109#define	UART_BDH_SBR	0x1f	/* UART Baud Rate Bits */
110
111/*
112 * Low-level UART interface.
113 */
114static int vf_uart_probe(struct uart_bas *bas);
115static void vf_uart_init(struct uart_bas *bas, int, int, int, int);
116static void vf_uart_term(struct uart_bas *bas);
117static void vf_uart_putc(struct uart_bas *bas, int);
118static int vf_uart_rxready(struct uart_bas *bas);
119static int vf_uart_getc(struct uart_bas *bas, struct mtx *);
120
121void uart_reinit(struct uart_softc *,int,int);
122
123static struct uart_ops uart_vybrid_ops = {
124	.probe = vf_uart_probe,
125	.init = vf_uart_init,
126	.term = vf_uart_term,
127	.putc = vf_uart_putc,
128	.rxready = vf_uart_rxready,
129	.getc = vf_uart_getc,
130};
131
132static int
133vf_uart_probe(struct uart_bas *bas)
134{
135
136	return (0);
137}
138
139static void
140vf_uart_init(struct uart_bas *bas, int baudrate, int databits,
141    int stopbits, int parity)
142{
143
144}
145
146static void
147vf_uart_term(struct uart_bas *bas)
148{
149
150}
151
152static void
153vf_uart_putc(struct uart_bas *bas, int c)
154{
155
156	while (!(uart_getreg(bas, UART_S1) & UART_S1_TDRE))
157		;
158
159	uart_setreg(bas, UART_D, c);
160}
161
162static int
163vf_uart_rxready(struct uart_bas *bas)
164{
165	int usr1;
166
167	usr1 = uart_getreg(bas, UART_S1);
168	if (usr1 & UART_S1_RDRF) {
169		return (1);
170	}
171
172	return (0);
173}
174
175static int
176vf_uart_getc(struct uart_bas *bas, struct mtx *hwmtx)
177{
178	int c;
179
180	uart_lock(hwmtx);
181
182	while (!(uart_getreg(bas, UART_S1) & UART_S1_RDRF))
183		;
184
185	c = uart_getreg(bas, UART_D);
186	uart_unlock(hwmtx);
187
188	return (c & 0xff);
189}
190
191/*
192 * High-level UART interface.
193 */
194struct vf_uart_softc {
195	struct uart_softc base;
196};
197
198void
199uart_reinit(struct uart_softc *sc, int clkspeed, int baud)
200{
201	struct uart_bas *bas;
202	int sbr;
203	int brfa;
204	int reg;
205
206	bas = &sc->sc_bas;
207	if (!bas) {
208		printf("Error: cant reconfigure bas\n");
209		return;
210	}
211
212	uart_setreg(bas, UART_MODEM, 0x00);
213
214	/*
215	 * Disable transmitter and receiver
216	 * for a while.
217	 */
218	reg = uart_getreg(bas, UART_C2);
219	reg &= ~(UART_C2_RE | UART_C2_TE);
220	uart_setreg(bas, UART_C2, 0x00);
221
222	uart_setreg(bas, UART_C1, 0x00);
223
224	sbr = (uint16_t) (clkspeed / (baud * 16));
225	brfa = (clkspeed / baud) - (sbr * 16);
226
227	reg = uart_getreg(bas, UART_BDH);
228	reg &= ~UART_BDH_SBR;
229	reg |= ((sbr & 0x1f00) >> 8);
230	uart_setreg(bas, UART_BDH, reg);
231
232	reg = sbr & 0x00ff;
233	uart_setreg(bas, UART_BDL, reg);
234
235	reg = uart_getreg(bas, UART_C4);
236	reg &= ~UART_C4_BRFA;
237	reg |= (brfa & UART_C4_BRFA);
238	uart_setreg(bas, UART_C4, reg);
239
240	reg = uart_getreg(bas, UART_C2);
241	reg |= (UART_C2_RE | UART_C2_TE);
242	uart_setreg(bas, UART_C2, reg);
243
244}
245
246static int vf_uart_bus_attach(struct uart_softc *);
247static int vf_uart_bus_detach(struct uart_softc *);
248static int vf_uart_bus_flush(struct uart_softc *, int);
249static int vf_uart_bus_getsig(struct uart_softc *);
250static int vf_uart_bus_ioctl(struct uart_softc *, int, intptr_t);
251static int vf_uart_bus_ipend(struct uart_softc *);
252static int vf_uart_bus_param(struct uart_softc *, int, int, int, int);
253static int vf_uart_bus_probe(struct uart_softc *);
254static int vf_uart_bus_receive(struct uart_softc *);
255static int vf_uart_bus_setsig(struct uart_softc *, int);
256static int vf_uart_bus_transmit(struct uart_softc *);
257
258static kobj_method_t vf_uart_methods[] = {
259	KOBJMETHOD(uart_attach,		vf_uart_bus_attach),
260	KOBJMETHOD(uart_detach,		vf_uart_bus_detach),
261	KOBJMETHOD(uart_flush,		vf_uart_bus_flush),
262	KOBJMETHOD(uart_getsig,		vf_uart_bus_getsig),
263	KOBJMETHOD(uart_ioctl,		vf_uart_bus_ioctl),
264	KOBJMETHOD(uart_ipend,		vf_uart_bus_ipend),
265	KOBJMETHOD(uart_param,		vf_uart_bus_param),
266	KOBJMETHOD(uart_probe,		vf_uart_bus_probe),
267	KOBJMETHOD(uart_receive,	vf_uart_bus_receive),
268	KOBJMETHOD(uart_setsig,		vf_uart_bus_setsig),
269	KOBJMETHOD(uart_transmit,	vf_uart_bus_transmit),
270	{ 0, 0 }
271};
272
273struct uart_class uart_vybrid_class = {
274	"vybrid",
275	vf_uart_methods,
276	sizeof(struct vf_uart_softc),
277	.uc_ops = &uart_vybrid_ops,
278	.uc_range = 0x100,
279	.uc_rclk = 24000000 /* TODO: get value from CCM */
280};
281
282static int
283vf_uart_bus_attach(struct uart_softc *sc)
284{
285	struct uart_bas *bas;
286	int reg;
287
288	bas = &sc->sc_bas;
289
290	sc->sc_hwiflow = 0;
291	sc->sc_hwoflow = 0;
292
293	uart_reinit(sc, 66000000, 115200);
294
295	reg = uart_getreg(bas, UART_C2);
296	if (sc->sc_sysdev != NULL && sc->sc_sysdev->type == UART_DEV_CONSOLE) {
297		reg &= ~UART_C2_RIE;
298	} else {
299		reg |= UART_C2_RIE;
300	}
301	uart_setreg(bas, UART_C2, reg);
302
303	return (0);
304}
305
306static int
307vf_uart_bus_detach(struct uart_softc *sc)
308{
309
310	/* TODO */
311	return (0);
312}
313
314static int
315vf_uart_bus_flush(struct uart_softc *sc, int what)
316{
317
318	/* TODO */
319	return (0);
320}
321
322static int
323vf_uart_bus_getsig(struct uart_softc *sc)
324{
325
326	/* TODO */
327	return (0);
328}
329
330static int
331vf_uart_bus_ioctl(struct uart_softc *sc, int request, intptr_t data)
332{
333	struct uart_bas *bas;
334	int error;
335
336	bas = &sc->sc_bas;
337	error = 0;
338	uart_lock(sc->sc_hwmtx);
339	switch (request) {
340	case UART_IOCTL_BREAK:
341	/* TODO */
342		break;
343	case UART_IOCTL_BAUD:
344	/* TODO */
345		*(int*)data = 115200;
346		break;
347	default:
348		error = EINVAL;
349		break;
350	}
351	uart_unlock(sc->sc_hwmtx);
352
353	return (error);
354}
355
356static int
357vf_uart_bus_ipend(struct uart_softc *sc)
358{
359	struct uart_bas *bas;
360	int ipend;
361	uint32_t usr1, usr2;
362	int reg;
363	int sfifo;
364
365	bas = &sc->sc_bas;
366	ipend = 0;
367
368	uart_lock(sc->sc_hwmtx);
369
370	usr1 = uart_getreg(bas, UART_S1);
371	usr2 = uart_getreg(bas, UART_S2);
372	sfifo = uart_getreg(bas, UART_SFIFO);
373
374	/* ack usr2 */
375	uart_setreg(bas, UART_S2, usr2);
376
377	if (usr1 & UART_S1_TDRE) {
378		reg = uart_getreg(bas, UART_C2);
379		reg &= ~(UART_C2_TIE);
380		uart_setreg(bas, UART_C2, reg);
381
382		if (sc->sc_txbusy != 0) {
383			ipend |= SER_INT_TXIDLE;
384		}
385	}
386
387	if (usr1 & UART_S1_RDRF) {
388		reg = uart_getreg(bas, UART_C2);
389		reg &= ~(UART_C2_RIE);
390		uart_setreg(bas, UART_C2, reg);
391
392		ipend |= SER_INT_RXREADY;
393	}
394
395	if (usr2 & UART_S2_LBKDIF) {
396		ipend |= SER_INT_BREAK;
397	}
398
399	uart_unlock(sc->sc_hwmtx);
400
401	return (ipend);
402}
403
404static int
405vf_uart_bus_param(struct uart_softc *sc, int baudrate, int databits,
406    int stopbits, int parity)
407{
408
409	uart_lock(sc->sc_hwmtx);
410	vf_uart_init(&sc->sc_bas, baudrate, databits, stopbits, parity);
411	uart_unlock(sc->sc_hwmtx);
412
413	return (0);
414}
415
416static int
417vf_uart_bus_probe(struct uart_softc *sc)
418{
419	int error;
420
421	error = vf_uart_probe(&sc->sc_bas);
422	if (error)
423		return (error);
424
425	sc->sc_rxfifosz = 1;
426	sc->sc_txfifosz = 1;
427
428	device_set_desc(sc->sc_dev, "Vybrid Family UART");
429	return (0);
430}
431
432static int
433vf_uart_bus_receive(struct uart_softc *sc)
434{
435	struct uart_bas *bas;
436	int reg;
437	int c;
438
439	bas = &sc->sc_bas;
440	uart_lock(sc->sc_hwmtx);
441
442	/* Read FIFO */
443	while (uart_getreg(bas, UART_S1) & UART_S1_RDRF) {
444		if (uart_rx_full(sc)) {
445		/* No space left in input buffer */
446			sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN;
447			break;
448		}
449
450		c = uart_getreg(bas, UART_D);
451		uart_rx_put(sc, c);
452	}
453
454	/* Reenable Data Ready interrupt */
455	reg = uart_getreg(bas, UART_C2);
456	reg |= (UART_C2_RIE);
457	uart_setreg(bas, UART_C2, reg);
458
459	uart_unlock(sc->sc_hwmtx);
460	return (0);
461}
462
463static int
464vf_uart_bus_setsig(struct uart_softc *sc, int sig)
465{
466	struct uart_bas *bas;
467	int reg;
468
469	/* TODO: implement (?) */
470
471	/* XXX workaround to have working console on mount prompt */
472	/* Enable RX interrupt */
473	bas = &sc->sc_bas;
474	if (sc->sc_sysdev != NULL && sc->sc_sysdev->type == UART_DEV_CONSOLE) {
475		reg = uart_getreg(bas, UART_C2);
476		reg |= (UART_C2_RIE);
477		uart_setreg(bas, UART_C2, reg);
478	}
479
480	return (0);
481}
482
483static int
484vf_uart_bus_transmit(struct uart_softc *sc)
485{
486	struct uart_bas *bas = &sc->sc_bas;
487	int i;
488	int reg;
489
490	bas = &sc->sc_bas;
491	uart_lock(sc->sc_hwmtx);
492
493	/* Fill TX FIFO */
494	for (i = 0; i < sc->sc_txdatasz; i++) {
495		uart_setreg(bas, UART_D, sc->sc_txbuf[i] & 0xff);
496		uart_barrier(&sc->sc_bas);
497	}
498
499	sc->sc_txbusy = 1;
500
501	/* Call me when ready */
502	reg = uart_getreg(bas, UART_C2);
503	reg |= (UART_C2_TIE);
504	uart_setreg(bas, UART_C2, reg);
505
506	uart_unlock(sc->sc_hwmtx);
507
508	return (0);
509}
510