vf_sai.c revision 314503
1/*- 2 * Copyright (c) 2014 Ruslan Bukin <br@bsdpad.com> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27/* 28 * Vybrid Family Synchronous Audio Interface (SAI) 29 * Chapter 51, Vybrid Reference Manual, Rev. 5, 07/2013 30 */ 31 32#include <sys/cdefs.h> 33__FBSDID("$FreeBSD: stable/11/sys/arm/freescale/vybrid/vf_sai.c 314503 2017-03-01 18:53:05Z ian $"); 34 35#include <sys/param.h> 36#include <sys/systm.h> 37#include <sys/bus.h> 38#include <sys/kernel.h> 39#include <sys/module.h> 40#include <sys/malloc.h> 41#include <sys/rman.h> 42#include <sys/timeet.h> 43#include <sys/timetc.h> 44#include <sys/watchdog.h> 45 46#include <dev/sound/pcm/sound.h> 47#include <dev/sound/chip.h> 48#include <mixer_if.h> 49 50#include <dev/ofw/openfirm.h> 51#include <dev/ofw/ofw_bus.h> 52#include <dev/ofw/ofw_bus_subr.h> 53 54#include <machine/bus.h> 55#include <machine/cpu.h> 56#include <machine/intr.h> 57 58#include <arm/freescale/vybrid/vf_common.h> 59#include <arm/freescale/vybrid/vf_dmamux.h> 60#include <arm/freescale/vybrid/vf_edma.h> 61 62#define I2S_TCSR 0x00 /* SAI Transmit Control */ 63#define I2S_TCR1 0x04 /* SAI Transmit Configuration 1 */ 64#define I2S_TCR2 0x08 /* SAI Transmit Configuration 2 */ 65#define I2S_TCR3 0x0C /* SAI Transmit Configuration 3 */ 66#define I2S_TCR4 0x10 /* SAI Transmit Configuration 4 */ 67#define I2S_TCR5 0x14 /* SAI Transmit Configuration 5 */ 68#define I2S_TDR0 0x20 /* SAI Transmit Data */ 69#define I2S_TFR0 0x40 /* SAI Transmit FIFO */ 70#define I2S_TMR 0x60 /* SAI Transmit Mask */ 71#define I2S_RCSR 0x80 /* SAI Receive Control */ 72#define I2S_RCR1 0x84 /* SAI Receive Configuration 1 */ 73#define I2S_RCR2 0x88 /* SAI Receive Configuration 2 */ 74#define I2S_RCR3 0x8C /* SAI Receive Configuration 3 */ 75#define I2S_RCR4 0x90 /* SAI Receive Configuration 4 */ 76#define I2S_RCR5 0x94 /* SAI Receive Configuration 5 */ 77#define I2S_RDR0 0xA0 /* SAI Receive Data */ 78#define I2S_RFR0 0xC0 /* SAI Receive FIFO */ 79#define I2S_RMR 0xE0 /* SAI Receive Mask */ 80 81#define TCR1_TFW_M 0x1f /* Transmit FIFO Watermark Mask */ 82#define TCR1_TFW_S 0 /* Transmit FIFO Watermark Shift */ 83#define TCR2_MSEL_M 0x3 /* MCLK Select Mask*/ 84#define TCR2_MSEL_S 26 /* MCLK Select Shift*/ 85#define TCR2_BCP (1 << 25) /* Bit Clock Polarity */ 86#define TCR2_BCD (1 << 24) /* Bit Clock Direction */ 87#define TCR3_TCE (1 << 16) /* Transmit Channel Enable */ 88#define TCR4_FRSZ_M 0x1f /* Frame size Mask */ 89#define TCR4_FRSZ_S 16 /* Frame size Shift */ 90#define TCR4_SYWD_M 0x1f /* Sync Width Mask */ 91#define TCR4_SYWD_S 8 /* Sync Width Shift */ 92#define TCR4_MF (1 << 4) /* MSB First */ 93#define TCR4_FSE (1 << 3) /* Frame Sync Early */ 94#define TCR4_FSP (1 << 1) /* Frame Sync Polarity Low */ 95#define TCR4_FSD (1 << 0) /* Frame Sync Direction Master */ 96#define TCR5_FBT_M 0x1f /* First Bit Shifted */ 97#define TCR5_FBT_S 8 /* First Bit Shifted */ 98#define TCR5_W0W_M 0x1f /* Word 0 Width */ 99#define TCR5_W0W_S 16 /* Word 0 Width */ 100#define TCR5_WNW_M 0x1f /* Word N Width */ 101#define TCR5_WNW_S 24 /* Word N Width */ 102#define TCSR_TE (1 << 31) /* Transmitter Enable */ 103#define TCSR_BCE (1 << 28) /* Bit Clock Enable */ 104#define TCSR_FRDE (1 << 0) /* FIFO Request DMA Enable */ 105 106#define SAI_NCHANNELS 1 107 108static MALLOC_DEFINE(M_SAI, "sai", "sai audio"); 109 110struct sai_rate { 111 uint32_t speed; 112 uint32_t div; /* Bit Clock Divide. Division value is (div + 1) * 2. */ 113 uint32_t mfi; /* PLL4 Multiplication Factor Integer */ 114 uint32_t mfn; /* PLL4 Multiplication Factor Numerator */ 115 uint32_t mfd; /* PLL4 Multiplication Factor Denominator */ 116}; 117 118/* 119 * Bit clock divider formula 120 * (div + 1) * 2 = MCLK/(nch * LRCLK * bits/1000000), 121 * where: 122 * MCLK - master clock 123 * nch - number of channels 124 * LRCLK - left right clock 125 * e.g. (div + 1) * 2 = 16.9344/(2 * 44100 * 24/1000000) 126 * 127 * Example for 96khz, 24bit, 18.432 Mhz mclk (192fs) 128 * { 96000, 1, 18, 40176000, 93000000 }, 129 */ 130 131static struct sai_rate rate_map[] = { 132 { 44100, 7, 33, 80798400, 93000000 }, /* 33.8688 Mhz */ 133 { 96000, 3, 36, 80352000, 93000000 }, /* 36.864 Mhz */ 134 { 192000, 1, 36, 80352000, 93000000 }, /* 36.864 Mhz */ 135 { 0, 0 }, 136}; 137 138struct sc_info { 139 struct resource *res[2]; 140 bus_space_tag_t bst; 141 bus_space_handle_t bsh; 142 device_t dev; 143 struct mtx *lock; 144 uint32_t speed; 145 uint32_t period; 146 void *ih; 147 int pos; 148 int dma_size; 149 bus_dma_tag_t dma_tag; 150 bus_dmamap_t dma_map; 151 bus_addr_t buf_base_phys; 152 uint32_t *buf_base; 153 struct tcd_conf *tcd; 154 struct sai_rate *sr; 155 struct edma_softc *edma_sc; 156 int edma_chnum; 157}; 158 159/* Channel registers */ 160struct sc_chinfo { 161 struct snd_dbuf *buffer; 162 struct pcm_channel *channel; 163 struct sc_pcminfo *parent; 164 165 /* Channel information */ 166 uint32_t dir; 167 uint32_t format; 168 169 /* Flags */ 170 uint32_t run; 171}; 172 173/* PCM device private data */ 174struct sc_pcminfo { 175 device_t dev; 176 uint32_t (*ih) (struct sc_pcminfo *scp); 177 uint32_t chnum; 178 struct sc_chinfo chan[SAI_NCHANNELS]; 179 struct sc_info *sc; 180}; 181 182static struct resource_spec sai_spec[] = { 183 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 184 { SYS_RES_IRQ, 0, RF_ACTIVE }, 185 { -1, 0 } 186}; 187 188static int setup_dma(struct sc_pcminfo *scp); 189static void setup_sai(struct sc_info *); 190static void sai_configure_clock(struct sc_info *); 191 192/* 193 * Mixer interface. 194 */ 195 196static int 197saimixer_init(struct snd_mixer *m) 198{ 199 struct sc_pcminfo *scp; 200 struct sc_info *sc; 201 int mask; 202 203 scp = mix_getdevinfo(m); 204 sc = scp->sc; 205 206 if (sc == NULL) 207 return -1; 208 209 mask = SOUND_MASK_PCM; 210 211 snd_mtxlock(sc->lock); 212 pcm_setflags(scp->dev, pcm_getflags(scp->dev) | SD_F_SOFTPCMVOL); 213 mix_setdevs(m, mask); 214 snd_mtxunlock(sc->lock); 215 216 return (0); 217} 218 219static int 220saimixer_set(struct snd_mixer *m, unsigned dev, 221 unsigned left, unsigned right) 222{ 223 struct sc_pcminfo *scp; 224 225 scp = mix_getdevinfo(m); 226 227#if 0 228 device_printf(scp->dev, "saimixer_set() %d %d\n", 229 left, right); 230#endif 231 232 return (0); 233} 234 235static kobj_method_t saimixer_methods[] = { 236 KOBJMETHOD(mixer_init, saimixer_init), 237 KOBJMETHOD(mixer_set, saimixer_set), 238 KOBJMETHOD_END 239}; 240MIXER_DECLARE(saimixer); 241 242/* 243 * Channel interface. 244 */ 245 246static void * 247saichan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b, 248 struct pcm_channel *c, int dir) 249{ 250 struct sc_pcminfo *scp; 251 struct sc_chinfo *ch; 252 struct sc_info *sc; 253 254 scp = (struct sc_pcminfo *)devinfo; 255 sc = scp->sc; 256 257 snd_mtxlock(sc->lock); 258 ch = &scp->chan[0]; 259 ch->dir = dir; 260 ch->run = 0; 261 ch->buffer = b; 262 ch->channel = c; 263 ch->parent = scp; 264 snd_mtxunlock(sc->lock); 265 266 if (sndbuf_setup(ch->buffer, sc->buf_base, sc->dma_size) != 0) { 267 device_printf(scp->dev, "Can't setup sndbuf.\n"); 268 return NULL; 269 } 270 271 return ch; 272} 273 274static int 275saichan_free(kobj_t obj, void *data) 276{ 277 struct sc_chinfo *ch = data; 278 struct sc_pcminfo *scp = ch->parent; 279 struct sc_info *sc = scp->sc; 280 281#if 0 282 device_printf(scp->dev, "saichan_free()\n"); 283#endif 284 285 snd_mtxlock(sc->lock); 286 /* TODO: free channel buffer */ 287 snd_mtxunlock(sc->lock); 288 289 return (0); 290} 291 292static int 293saichan_setformat(kobj_t obj, void *data, uint32_t format) 294{ 295 struct sc_chinfo *ch = data; 296 297 ch->format = format; 298 299 return (0); 300} 301 302static uint32_t 303saichan_setspeed(kobj_t obj, void *data, uint32_t speed) 304{ 305 struct sc_pcminfo *scp; 306 struct sc_chinfo *ch; 307 struct sai_rate *sr; 308 struct sc_info *sc; 309 int threshold; 310 int i; 311 312 ch = data; 313 scp = ch->parent; 314 sc = scp->sc; 315 316 sr = NULL; 317 318 /* First look for equal frequency. */ 319 for (i = 0; rate_map[i].speed != 0; i++) { 320 if (rate_map[i].speed == speed) 321 sr = &rate_map[i]; 322 } 323 324 /* If no match, just find nearest. */ 325 if (sr == NULL) { 326 for (i = 0; rate_map[i].speed != 0; i++) { 327 sr = &rate_map[i]; 328 threshold = sr->speed + ((rate_map[i + 1].speed != 0) ? 329 ((rate_map[i + 1].speed - sr->speed) >> 1) : 0); 330 if (speed < threshold) 331 break; 332 } 333 } 334 335 sc->sr = sr; 336 337 sai_configure_clock(sc); 338 339 return (sr->speed); 340} 341 342static void 343sai_configure_clock(struct sc_info *sc) 344{ 345 struct sai_rate *sr; 346 int reg; 347 348 sr = sc->sr; 349 350 /* 351 * Manual says that TCR/RCR registers must not be 352 * altered when TCSR[TE] is set. 353 * We ignore it since we have problem sometimes 354 * after re-enabling transmitter (DMA goes stall). 355 */ 356 357 reg = READ4(sc, I2S_TCR2); 358 reg &= ~(0xff << 0); 359 reg |= (sr->div << 0); 360 WRITE4(sc, I2S_TCR2, reg); 361 362 pll4_configure_output(sr->mfi, sr->mfn, sr->mfd); 363} 364 365static uint32_t 366saichan_setblocksize(kobj_t obj, void *data, uint32_t blocksize) 367{ 368 struct sc_chinfo *ch = data; 369 struct sc_pcminfo *scp = ch->parent; 370 struct sc_info *sc = scp->sc; 371 372 sndbuf_resize(ch->buffer, sc->dma_size / blocksize, blocksize); 373 374 sc->period = sndbuf_getblksz(ch->buffer); 375 return (sc->period); 376} 377 378uint32_t sai_dma_intr(void *arg, int chn); 379uint32_t 380sai_dma_intr(void *arg, int chn) 381{ 382 struct sc_pcminfo *scp; 383 struct sc_chinfo *ch; 384 struct sc_info *sc; 385 struct tcd_conf *tcd; 386 387 scp = arg; 388 ch = &scp->chan[0]; 389 390 sc = scp->sc; 391 tcd = sc->tcd; 392 393 sc->pos += (tcd->nbytes * tcd->nmajor); 394 if (sc->pos >= sc->dma_size) 395 sc->pos -= sc->dma_size; 396 397 if (ch->run) 398 chn_intr(ch->channel); 399 400 return (0); 401} 402 403static int 404find_edma_controller(struct sc_info *sc) 405{ 406 struct edma_softc *edma_sc; 407 phandle_t node, edma_node; 408 int edma_src_transmit; 409 int edma_mux_group; 410 int edma_device_id; 411 device_t edma_dev; 412 int dts_value; 413 int len; 414 int i; 415 416 if ((node = ofw_bus_get_node(sc->dev)) == -1) 417 return (ENXIO); 418 419 if ((len = OF_getproplen(node, "edma-controller")) <= 0) 420 return (ENXIO); 421 if ((len = OF_getproplen(node, "edma-src-transmit")) <= 0) 422 return (ENXIO); 423 if ((len = OF_getproplen(node, "edma-mux-group")) <= 0) 424 return (ENXIO); 425 426 OF_getencprop(node, "edma-src-transmit", &dts_value, len); 427 edma_src_transmit = dts_value; 428 OF_getencprop(node, "edma-mux-group", &dts_value, len); 429 edma_mux_group = dts_value; 430 OF_getencprop(node, "edma-controller", &dts_value, len); 431 edma_node = OF_node_from_xref(dts_value); 432 433 if ((len = OF_getproplen(edma_node, "device-id")) <= 0) { 434 return (ENXIO); 435 } 436 437 OF_getencprop(edma_node, "device-id", &dts_value, len); 438 edma_device_id = dts_value; 439 440 edma_sc = NULL; 441 442 for (i = 0; i < EDMA_NUM_DEVICES; i++) { 443 edma_dev = devclass_get_device(devclass_find("edma"), i); 444 if (edma_dev) { 445 edma_sc = device_get_softc(edma_dev); 446 if (edma_sc->device_id == edma_device_id) { 447 /* found */ 448 break; 449 } 450 451 edma_sc = NULL; 452 } 453 } 454 455 if (edma_sc == NULL) { 456 device_printf(sc->dev, "no eDMA. can't operate\n"); 457 return (ENXIO); 458 } 459 460 sc->edma_sc = edma_sc; 461 462 sc->edma_chnum = edma_sc->channel_configure(edma_sc, edma_mux_group, 463 edma_src_transmit); 464 if (sc->edma_chnum < 0) { 465 /* cant setup eDMA */ 466 return (ENXIO); 467 } 468 469 return (0); 470}; 471 472static int 473setup_dma(struct sc_pcminfo *scp) 474{ 475 struct tcd_conf *tcd; 476 struct sc_info *sc; 477 478 sc = scp->sc; 479 480 tcd = malloc(sizeof(struct tcd_conf), M_DEVBUF, M_WAITOK | M_ZERO); 481 tcd->channel = sc->edma_chnum; 482 tcd->ih = sai_dma_intr; 483 tcd->ih_user = scp; 484 tcd->saddr = sc->buf_base_phys; 485 tcd->daddr = rman_get_start(sc->res[0]) + I2S_TDR0; 486 487 /* 488 * Bytes to transfer per each minor loop. 489 * Hardware FIFO buffer size is 32x32bits. 490 */ 491 tcd->nbytes = 64; 492 493 tcd->nmajor = 512; 494 tcd->smod = 17; /* dma_size range */ 495 tcd->dmod = 0; 496 tcd->esg = 0; 497 tcd->soff = 0x4; 498 tcd->doff = 0; 499 tcd->ssize = 0x2; 500 tcd->dsize = 0x2; 501 tcd->slast = 0; 502 tcd->dlast_sga = 0; 503 504 sc->tcd = tcd; 505 506 sc->edma_sc->dma_setup(sc->edma_sc, sc->tcd); 507 508 return (0); 509} 510 511static int 512saichan_trigger(kobj_t obj, void *data, int go) 513{ 514 struct sc_chinfo *ch = data; 515 struct sc_pcminfo *scp = ch->parent; 516 struct sc_info *sc = scp->sc; 517 518 snd_mtxlock(sc->lock); 519 520 switch (go) { 521 case PCMTRIG_START: 522#if 0 523 device_printf(scp->dev, "trigger start\n"); 524#endif 525 ch->run = 1; 526 break; 527 528 case PCMTRIG_STOP: 529 case PCMTRIG_ABORT: 530#if 0 531 device_printf(scp->dev, "trigger stop or abort\n"); 532#endif 533 ch->run = 0; 534 break; 535 } 536 537 snd_mtxunlock(sc->lock); 538 539 return (0); 540} 541 542static uint32_t 543saichan_getptr(kobj_t obj, void *data) 544{ 545 struct sc_pcminfo *scp; 546 struct sc_chinfo *ch; 547 struct sc_info *sc; 548 549 ch = data; 550 scp = ch->parent; 551 sc = scp->sc; 552 553 return (sc->pos); 554} 555 556static uint32_t sai_pfmt[] = { 557 /* 558 * eDMA doesn't allow 24-bit coping, 559 * so we use 32. 560 */ 561 SND_FORMAT(AFMT_S32_LE, 2, 0), 562 0 563}; 564 565static struct pcmchan_caps sai_pcaps = {44100, 192000, sai_pfmt, 0}; 566 567static struct pcmchan_caps * 568saichan_getcaps(kobj_t obj, void *data) 569{ 570 571 return (&sai_pcaps); 572} 573 574static kobj_method_t saichan_methods[] = { 575 KOBJMETHOD(channel_init, saichan_init), 576 KOBJMETHOD(channel_free, saichan_free), 577 KOBJMETHOD(channel_setformat, saichan_setformat), 578 KOBJMETHOD(channel_setspeed, saichan_setspeed), 579 KOBJMETHOD(channel_setblocksize, saichan_setblocksize), 580 KOBJMETHOD(channel_trigger, saichan_trigger), 581 KOBJMETHOD(channel_getptr, saichan_getptr), 582 KOBJMETHOD(channel_getcaps, saichan_getcaps), 583 KOBJMETHOD_END 584}; 585CHANNEL_DECLARE(saichan); 586 587static int 588sai_probe(device_t dev) 589{ 590 591 if (!ofw_bus_status_okay(dev)) 592 return (ENXIO); 593 594 if (!ofw_bus_is_compatible(dev, "fsl,mvf600-sai")) 595 return (ENXIO); 596 597 device_set_desc(dev, "Vybrid Family Synchronous Audio Interface"); 598 return (BUS_PROBE_DEFAULT); 599} 600 601static void 602sai_intr(void *arg) 603{ 604 struct sc_pcminfo *scp; 605 struct sc_info *sc; 606 607 scp = arg; 608 sc = scp->sc; 609 610 device_printf(sc->dev, "Error I2S_TCSR == 0x%08x\n", 611 READ4(sc, I2S_TCSR)); 612} 613 614static void 615setup_sai(struct sc_info *sc) 616{ 617 int reg; 618 619 /* 620 * TCR/RCR registers must not be altered when TCSR[TE] is set. 621 */ 622 623 reg = READ4(sc, I2S_TCSR); 624 reg &= ~(TCSR_BCE | TCSR_TE | TCSR_FRDE); 625 WRITE4(sc, I2S_TCSR, reg); 626 627 reg = READ4(sc, I2S_TCR3); 628 reg &= ~(TCR3_TCE); 629 WRITE4(sc, I2S_TCR3, reg); 630 631 reg = (64 << TCR1_TFW_S); 632 WRITE4(sc, I2S_TCR1, reg); 633 634 reg = READ4(sc, I2S_TCR2); 635 reg &= ~(TCR2_MSEL_M << TCR2_MSEL_S); 636 reg |= (1 << TCR2_MSEL_S); 637 reg |= (TCR2_BCP | TCR2_BCD); 638 WRITE4(sc, I2S_TCR2, reg); 639 640 sai_configure_clock(sc); 641 642 reg = READ4(sc, I2S_TCR3); 643 reg |= (TCR3_TCE); 644 WRITE4(sc, I2S_TCR3, reg); 645 646 /* Configure to 32-bit I2S mode */ 647 reg = READ4(sc, I2S_TCR4); 648 reg &= ~(TCR4_FRSZ_M << TCR4_FRSZ_S); 649 reg |= (1 << TCR4_FRSZ_S); /* 2 words per frame */ 650 reg &= ~(TCR4_SYWD_M << TCR4_SYWD_S); 651 reg |= (23 << TCR4_SYWD_S); 652 reg |= (TCR4_MF | TCR4_FSE | TCR4_FSP | TCR4_FSD); 653 WRITE4(sc, I2S_TCR4, reg); 654 655 reg = READ4(sc, I2S_TCR5); 656 reg &= ~(TCR5_W0W_M << TCR5_W0W_S); 657 reg |= (23 << TCR5_W0W_S); 658 reg &= ~(TCR5_WNW_M << TCR5_WNW_S); 659 reg |= (23 << TCR5_WNW_S); 660 reg &= ~(TCR5_FBT_M << TCR5_FBT_S); 661 reg |= (31 << TCR5_FBT_S); 662 WRITE4(sc, I2S_TCR5, reg); 663 664 /* Enable transmitter */ 665 reg = READ4(sc, I2S_TCSR); 666 reg |= (TCSR_BCE | TCSR_TE | TCSR_FRDE); 667 reg |= (1 << 10); /* FEIE */ 668 WRITE4(sc, I2S_TCSR, reg); 669} 670 671 672static void 673sai_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err) 674{ 675 bus_addr_t *addr; 676 677 if (err) 678 return; 679 680 addr = (bus_addr_t*)arg; 681 *addr = segs[0].ds_addr; 682} 683 684static int 685sai_attach(device_t dev) 686{ 687 char status[SND_STATUSLEN]; 688 struct sc_pcminfo *scp; 689 struct sc_info *sc; 690 int err; 691 692 sc = malloc(sizeof(*sc), M_DEVBUF, M_WAITOK | M_ZERO); 693 sc->dev = dev; 694 sc->sr = &rate_map[0]; 695 sc->pos = 0; 696 697 sc->lock = snd_mtxcreate(device_get_nameunit(dev), "sai softc"); 698 if (sc->lock == NULL) { 699 device_printf(dev, "Cant create mtx\n"); 700 return (ENXIO); 701 } 702 703 if (bus_alloc_resources(dev, sai_spec, sc->res)) { 704 device_printf(dev, "could not allocate resources\n"); 705 return (ENXIO); 706 } 707 708 /* Memory interface */ 709 sc->bst = rman_get_bustag(sc->res[0]); 710 sc->bsh = rman_get_bushandle(sc->res[0]); 711 712 /* eDMA */ 713 if (find_edma_controller(sc)) { 714 device_printf(dev, "could not find active eDMA\n"); 715 return (ENXIO); 716 } 717 718 /* Setup PCM */ 719 scp = malloc(sizeof(struct sc_pcminfo), M_DEVBUF, M_NOWAIT | M_ZERO); 720 scp->sc = sc; 721 scp->dev = dev; 722 723 /* DMA */ 724 sc->dma_size = 131072; 725 726 /* 727 * Must use dma_size boundary as modulo feature required. 728 * Modulo feature allows setup circular buffer. 729 */ 730 731 err = bus_dma_tag_create( 732 bus_get_dma_tag(sc->dev), 733 4, sc->dma_size, /* alignment, boundary */ 734 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 735 BUS_SPACE_MAXADDR, /* highaddr */ 736 NULL, NULL, /* filter, filterarg */ 737 sc->dma_size, 1, /* maxsize, nsegments */ 738 sc->dma_size, 0, /* maxsegsize, flags */ 739 NULL, NULL, /* lockfunc, lockarg */ 740 &sc->dma_tag); 741 742 err = bus_dmamem_alloc(sc->dma_tag, (void **)&sc->buf_base, 743 BUS_DMA_NOWAIT | BUS_DMA_COHERENT, &sc->dma_map); 744 if (err) { 745 device_printf(dev, "cannot allocate framebuffer\n"); 746 return (ENXIO); 747 } 748 749 err = bus_dmamap_load(sc->dma_tag, sc->dma_map, sc->buf_base, 750 sc->dma_size, sai_dmamap_cb, &sc->buf_base_phys, BUS_DMA_NOWAIT); 751 if (err) { 752 device_printf(dev, "cannot load DMA map\n"); 753 return (ENXIO); 754 } 755 756 bzero(sc->buf_base, sc->dma_size); 757 758 /* Setup interrupt handler */ 759 err = bus_setup_intr(dev, sc->res[1], INTR_MPSAFE | INTR_TYPE_AV, 760 NULL, sai_intr, scp, &sc->ih); 761 if (err) { 762 device_printf(dev, "Unable to alloc interrupt resource.\n"); 763 return (ENXIO); 764 } 765 766 pcm_setflags(dev, pcm_getflags(dev) | SD_F_MPSAFE); 767 768 err = pcm_register(dev, scp, 1, 0); 769 if (err) { 770 device_printf(dev, "Can't register pcm.\n"); 771 return (ENXIO); 772 } 773 774 scp->chnum = 0; 775 pcm_addchan(dev, PCMDIR_PLAY, &saichan_class, scp); 776 scp->chnum++; 777 778 snprintf(status, SND_STATUSLEN, "at simplebus"); 779 pcm_setstatus(dev, status); 780 781 mixer_init(dev, &saimixer_class, scp); 782 783 setup_dma(scp); 784 setup_sai(sc); 785 786 return (0); 787} 788 789static device_method_t sai_pcm_methods[] = { 790 DEVMETHOD(device_probe, sai_probe), 791 DEVMETHOD(device_attach, sai_attach), 792 { 0, 0 } 793}; 794 795static driver_t sai_pcm_driver = { 796 "pcm", 797 sai_pcm_methods, 798 PCM_SOFTC_SIZE, 799}; 800 801DRIVER_MODULE(sai, simplebus, sai_pcm_driver, pcm_devclass, 0, 0); 802MODULE_DEPEND(sai, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); 803MODULE_VERSION(sai, 1); 804