imx_i2c.c revision 323419
1/*- 2 * Copyright (C) 2008-2009 Semihalf, Michal Hajduk 3 * Copyright (c) 2012, 2013 The FreeBSD Foundation 4 * Copyright (c) 2015 Ian Lepore <ian@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Portions of this software were developed by Oleksandr Rybalko 8 * under sponsorship from the FreeBSD Foundation. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 */ 31 32/* 33 * I2C driver for Freescale i.MX hardware. 34 * 35 * Note that the hardware is capable of running as both a master and a slave. 36 * This driver currently implements only master-mode operations. 37 * 38 * This driver supports multi-master i2c busses, by detecting bus arbitration 39 * loss and returning IIC_EBUSBSY status. Notably, it does not do any kind of 40 * retries if some other master jumps onto the bus and interrupts one of our 41 * transfer cycles resulting in arbitration loss in mid-transfer. The caller 42 * must handle retries in a way that makes sense for the slave being addressed. 43 */ 44 45#include <sys/cdefs.h> 46__FBSDID("$FreeBSD: stable/11/sys/arm/freescale/imx/imx_i2c.c 323419 2017-09-11 02:50:24Z ian $"); 47 48#include <sys/param.h> 49#include <sys/systm.h> 50#include <sys/bus.h> 51#include <sys/gpio.h> 52#include <sys/kernel.h> 53#include <sys/limits.h> 54#include <sys/module.h> 55#include <sys/resource.h> 56 57#include <machine/bus.h> 58#include <machine/resource.h> 59#include <sys/rman.h> 60 61#include <arm/freescale/imx/imx_ccmvar.h> 62 63#include <dev/iicbus/iiconf.h> 64#include <dev/iicbus/iicbus.h> 65#include <dev/iicbus/iic_recover_bus.h> 66#include "iicbus_if.h" 67 68#include <dev/fdt/fdt_common.h> 69#include <dev/ofw/openfirm.h> 70#include <dev/ofw/ofw_bus.h> 71#include <dev/ofw/ofw_bus_subr.h> 72 73#include <dev/fdt/fdt_pinctrl.h> 74#include <dev/gpio/gpiobusvar.h> 75 76#define I2C_ADDR_REG 0x00 /* I2C slave address register */ 77#define I2C_FDR_REG 0x04 /* I2C frequency divider register */ 78#define I2C_CONTROL_REG 0x08 /* I2C control register */ 79#define I2C_STATUS_REG 0x0C /* I2C status register */ 80#define I2C_DATA_REG 0x10 /* I2C data register */ 81#define I2C_DFSRR_REG 0x14 /* I2C Digital Filter Sampling rate */ 82 83#define I2CCR_MEN (1 << 7) /* Module enable */ 84#define I2CCR_MSTA (1 << 5) /* Master/slave mode */ 85#define I2CCR_MTX (1 << 4) /* Transmit/receive mode */ 86#define I2CCR_TXAK (1 << 3) /* Transfer acknowledge */ 87#define I2CCR_RSTA (1 << 2) /* Repeated START */ 88 89#define I2CSR_MCF (1 << 7) /* Data transfer */ 90#define I2CSR_MASS (1 << 6) /* Addressed as a slave */ 91#define I2CSR_MBB (1 << 5) /* Bus busy */ 92#define I2CSR_MAL (1 << 4) /* Arbitration lost */ 93#define I2CSR_SRW (1 << 2) /* Slave read/write */ 94#define I2CSR_MIF (1 << 1) /* Module interrupt */ 95#define I2CSR_RXAK (1 << 0) /* Received acknowledge */ 96 97#define I2C_BAUD_RATE_FAST 0x31 98#define I2C_BAUD_RATE_DEF 0x3F 99#define I2C_DFSSR_DIV 0x10 100 101/* 102 * A table of available divisors and the associated coded values to put in the 103 * FDR register to achieve that divisor.. There is no algorithmic relationship I 104 * can see between divisors and the codes that go into the register. The table 105 * begins and ends with entries that handle insane configuration values. 106 */ 107struct clkdiv { 108 u_int divisor; 109 u_int regcode; 110}; 111static struct clkdiv clkdiv_table[] = { 112 { 0, 0x20 }, { 22, 0x20 }, { 24, 0x21 }, { 26, 0x22 }, 113 { 28, 0x23 }, { 30, 0x00 }, { 32, 0x24 }, { 36, 0x25 }, 114 { 40, 0x26 }, { 42, 0x03 }, { 44, 0x27 }, { 48, 0x28 }, 115 { 52, 0x05 }, { 56, 0x29 }, { 60, 0x06 }, { 64, 0x2a }, 116 { 72, 0x2b }, { 80, 0x2c }, { 88, 0x09 }, { 96, 0x2d }, 117 { 104, 0x0a }, { 112, 0x2e }, { 128, 0x2f }, { 144, 0x0c }, 118 { 160, 0x30 }, { 192, 0x31 }, { 224, 0x32 }, { 240, 0x0f }, 119 { 256, 0x33 }, { 288, 0x10 }, { 320, 0x34 }, { 384, 0x35 }, 120 { 448, 0x36 }, { 480, 0x13 }, { 512, 0x37 }, { 576, 0x14 }, 121 { 640, 0x38 }, { 768, 0x39 }, { 896, 0x3a }, { 960, 0x17 }, 122 { 1024, 0x3b }, { 1152, 0x18 }, { 1280, 0x3c }, { 1536, 0x3d }, 123 { 1792, 0x3e }, { 1920, 0x1b }, { 2048, 0x3f }, { 2304, 0x1c }, 124 { 2560, 0x1d }, { 3072, 0x1e }, { 3840, 0x1f }, {UINT_MAX, 0x1f} 125}; 126 127static struct ofw_compat_data compat_data[] = { 128 {"fsl,imx6q-i2c", 1}, 129 {"fsl,imx-i2c", 1}, 130 {NULL, 0} 131}; 132 133struct i2c_softc { 134 device_t dev; 135 device_t iicbus; 136 struct resource *res; 137 int rid; 138 sbintime_t byte_time_sbt; 139 int rb_pinctl_idx; 140 gpio_pin_t rb_sclpin; 141 gpio_pin_t rb_sdapin; 142}; 143 144static phandle_t i2c_get_node(device_t, device_t); 145static int i2c_probe(device_t); 146static int i2c_attach(device_t); 147 148static int i2c_repeated_start(device_t, u_char, int); 149static int i2c_start(device_t, u_char, int); 150static int i2c_stop(device_t); 151static int i2c_reset(device_t, u_char, u_char, u_char *); 152static int i2c_read(device_t, char *, int, int *, int, int); 153static int i2c_write(device_t, const char *, int, int *, int); 154 155static device_method_t i2c_methods[] = { 156 DEVMETHOD(device_probe, i2c_probe), 157 DEVMETHOD(device_attach, i2c_attach), 158 159 /* OFW methods */ 160 DEVMETHOD(ofw_bus_get_node, i2c_get_node), 161 162 DEVMETHOD(iicbus_callback, iicbus_null_callback), 163 DEVMETHOD(iicbus_repeated_start, i2c_repeated_start), 164 DEVMETHOD(iicbus_start, i2c_start), 165 DEVMETHOD(iicbus_stop, i2c_stop), 166 DEVMETHOD(iicbus_reset, i2c_reset), 167 DEVMETHOD(iicbus_read, i2c_read), 168 DEVMETHOD(iicbus_write, i2c_write), 169 DEVMETHOD(iicbus_transfer, iicbus_transfer_gen), 170 171 DEVMETHOD_END 172}; 173 174static driver_t i2c_driver = { 175 "iichb", 176 i2c_methods, 177 sizeof(struct i2c_softc), 178}; 179static devclass_t i2c_devclass; 180 181DRIVER_MODULE(i2c, simplebus, i2c_driver, i2c_devclass, 0, 0); 182DRIVER_MODULE(iicbus, i2c, iicbus_driver, iicbus_devclass, 0, 0); 183 184static phandle_t 185i2c_get_node(device_t bus, device_t dev) 186{ 187 /* 188 * Share controller node with iicbus device 189 */ 190 return ofw_bus_get_node(bus); 191} 192 193static __inline void 194i2c_write_reg(struct i2c_softc *sc, bus_size_t off, uint8_t val) 195{ 196 197 bus_write_1(sc->res, off, val); 198} 199 200static __inline uint8_t 201i2c_read_reg(struct i2c_softc *sc, bus_size_t off) 202{ 203 204 return (bus_read_1(sc->res, off)); 205} 206 207static __inline void 208i2c_flag_set(struct i2c_softc *sc, bus_size_t off, uint8_t mask) 209{ 210 uint8_t status; 211 212 status = i2c_read_reg(sc, off); 213 status |= mask; 214 i2c_write_reg(sc, off, status); 215} 216 217/* Wait for bus to become busy or not-busy. */ 218static int 219wait_for_busbusy(struct i2c_softc *sc, int wantbusy) 220{ 221 int retry, srb; 222 223 retry = 1000; 224 while (retry --) { 225 srb = i2c_read_reg(sc, I2C_STATUS_REG) & I2CSR_MBB; 226 if ((srb && wantbusy) || (!srb && !wantbusy)) 227 return (IIC_NOERR); 228 DELAY(1); 229 } 230 return (IIC_ETIMEOUT); 231} 232 233/* Wait for transfer to complete, optionally check RXAK. */ 234static int 235wait_for_xfer(struct i2c_softc *sc, int checkack) 236{ 237 int retry, sr; 238 239 /* 240 * Sleep for about the time it takes to transfer a byte (with precision 241 * set to tolerate 5% oversleep). We calculate the approximate byte 242 * transfer time when we set the bus speed divisor. Slaves are allowed 243 * to do clock-stretching so the actual transfer time can be larger, but 244 * this gets the bulk of the waiting out of the way without tying up the 245 * processor the whole time. 246 */ 247 pause_sbt("imxi2c", sc->byte_time_sbt, sc->byte_time_sbt / 20, 0); 248 249 retry = 10000; 250 while (retry --) { 251 sr = i2c_read_reg(sc, I2C_STATUS_REG); 252 if (sr & I2CSR_MIF) { 253 if (sr & I2CSR_MAL) 254 return (IIC_EBUSERR); 255 else if (checkack && (sr & I2CSR_RXAK)) 256 return (IIC_ENOACK); 257 else 258 return (IIC_NOERR); 259 } 260 DELAY(1); 261 } 262 return (IIC_ETIMEOUT); 263} 264 265/* 266 * Implement the error handling shown in the state diagram of the imx6 reference 267 * manual. If there was an error, then: 268 * - Clear master mode (MSTA and MTX). 269 * - Wait for the bus to become free or for a timeout to happen. 270 * - Disable the controller. 271 */ 272static int 273i2c_error_handler(struct i2c_softc *sc, int error) 274{ 275 276 if (error != 0) { 277 i2c_write_reg(sc, I2C_STATUS_REG, 0); 278 i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN); 279 wait_for_busbusy(sc, false); 280 i2c_write_reg(sc, I2C_CONTROL_REG, 0); 281 } 282 return (error); 283} 284 285static int 286i2c_recover_getsda(void *ctx) 287{ 288 bool active; 289 290 gpio_pin_is_active(((struct i2c_softc *)ctx)->rb_sdapin, &active); 291 return (active); 292} 293 294static void 295i2c_recover_setsda(void *ctx, int value) 296{ 297 298 gpio_pin_set_active(((struct i2c_softc *)ctx)->rb_sdapin, value); 299} 300 301static int 302i2c_recover_getscl(void *ctx) 303{ 304 bool active; 305 306 gpio_pin_is_active(((struct i2c_softc *)ctx)->rb_sclpin, &active); 307 return (active); 308 309} 310 311static void 312i2c_recover_setscl(void *ctx, int value) 313{ 314 315 gpio_pin_set_active(((struct i2c_softc *)ctx)->rb_sclpin, value); 316} 317 318static int 319i2c_recover_bus(struct i2c_softc *sc) 320{ 321 struct iicrb_pin_access pins; 322 int err; 323 324 /* 325 * If we have gpio pinmux config, reconfigure the pins to gpio mode, 326 * invoke iic_recover_bus which checks for a hung bus and bitbangs a 327 * recovery sequence if necessary, then configure the pins back to i2c 328 * mode (idx 0). 329 */ 330 if (sc->rb_pinctl_idx == 0) 331 return (0); 332 333 fdt_pinctrl_configure(sc->dev, sc->rb_pinctl_idx); 334 335 pins.ctx = sc; 336 pins.getsda = i2c_recover_getsda; 337 pins.setsda = i2c_recover_setsda; 338 pins.getscl = i2c_recover_getscl; 339 pins.setscl = i2c_recover_setscl; 340 err = iic_recover_bus(&pins); 341 342 fdt_pinctrl_configure(sc->dev, 0); 343 344 return (err); 345} 346 347static int 348i2c_probe(device_t dev) 349{ 350 351 if (!ofw_bus_status_okay(dev)) 352 return (ENXIO); 353 354 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 355 return (ENXIO); 356 357 device_set_desc(dev, "Freescale i.MX I2C"); 358 359 return (BUS_PROBE_DEFAULT); 360} 361 362static int 363i2c_attach(device_t dev) 364{ 365 char wrkstr[16]; 366 struct i2c_softc *sc; 367 phandle_t node; 368 int err, cfgidx; 369 370 sc = device_get_softc(dev); 371 sc->dev = dev; 372 sc->rid = 0; 373 374 sc->res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->rid, 375 RF_ACTIVE); 376 if (sc->res == NULL) { 377 device_printf(dev, "could not allocate resources"); 378 return (ENXIO); 379 } 380 381 sc->iicbus = device_add_child(dev, "iicbus", -1); 382 if (sc->iicbus == NULL) { 383 device_printf(dev, "could not add iicbus child"); 384 return (ENXIO); 385 } 386 387 /* 388 * Set up for bus recovery using gpio pins, if the pinctrl and gpio 389 * properties are present. This is optional. If all the config data is 390 * not in place, we just don't do gpio bitbang bus recovery. 391 */ 392 node = ofw_bus_get_node(sc->dev); 393 394 err = gpio_pin_get_by_ofw_property(dev, node, "scl-gpios", 395 &sc->rb_sclpin); 396 if (err != 0) 397 goto no_recovery; 398 err = gpio_pin_get_by_ofw_property(dev, node, "sda-gpios", 399 &sc->rb_sdapin); 400 if (err != 0) 401 goto no_recovery; 402 403 /* 404 * Preset the gpio pins to output high (idle bus state). The signal 405 * won't actually appear on the pins until the bus recovery code changes 406 * the pinmux config from i2c to gpio. 407 */ 408 gpio_pin_setflags(sc->rb_sclpin, GPIO_PIN_OUTPUT); 409 gpio_pin_setflags(sc->rb_sdapin, GPIO_PIN_OUTPUT); 410 gpio_pin_set_active(sc->rb_sclpin, true); 411 gpio_pin_set_active(sc->rb_sdapin, true); 412 413 /* 414 * Obtain the index of pinctrl node for bus recovery using gpio pins, 415 * then confirm that pinctrl properties exist for that index and for the 416 * default pinctrl-0. If sc->rb_pinctl_idx is non-zero, the reset code 417 * will also do a bus recovery, so setting this value must be last. 418 */ 419 err = ofw_bus_find_string_index(node, "pinctrl-names", "gpio", &cfgidx); 420 if (err == 0) { 421 snprintf(wrkstr, sizeof(wrkstr), "pinctrl-%d", cfgidx); 422 if (OF_hasprop(node, "pinctrl-0") && OF_hasprop(node, wrkstr)) 423 sc->rb_pinctl_idx = cfgidx; 424 } 425 426no_recovery: 427 428 /* We don't do a hardware reset here because iicbus_attach() does it. */ 429 430 bus_generic_attach(dev); 431 return (0); 432} 433 434static int 435i2c_repeated_start(device_t dev, u_char slave, int timeout) 436{ 437 struct i2c_softc *sc; 438 int error; 439 440 sc = device_get_softc(dev); 441 442 if ((i2c_read_reg(sc, I2C_STATUS_REG) & I2CSR_MBB) == 0) { 443 return (IIC_EBUSERR); 444 } 445 446 /* 447 * Set repeated start condition, delay (per reference manual, min 156nS) 448 * before writing slave address, wait for ack after write. 449 */ 450 i2c_flag_set(sc, I2C_CONTROL_REG, I2CCR_RSTA); 451 DELAY(1); 452 i2c_write_reg(sc, I2C_STATUS_REG, 0x0); 453 i2c_write_reg(sc, I2C_DATA_REG, slave); 454 error = wait_for_xfer(sc, true); 455 return (i2c_error_handler(sc, error)); 456} 457 458static int 459i2c_start_ll(device_t dev, u_char slave, int timeout) 460{ 461 struct i2c_softc *sc; 462 int error; 463 464 sc = device_get_softc(dev); 465 466 i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN); 467 DELAY(10); /* Delay for controller to sample bus state. */ 468 if (i2c_read_reg(sc, I2C_STATUS_REG) & I2CSR_MBB) { 469 return (i2c_error_handler(sc, IIC_EBUSERR)); 470 } 471 i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN | I2CCR_MSTA | I2CCR_MTX); 472 if ((error = wait_for_busbusy(sc, true)) != IIC_NOERR) 473 return (i2c_error_handler(sc, error)); 474 i2c_write_reg(sc, I2C_STATUS_REG, 0); 475 i2c_write_reg(sc, I2C_DATA_REG, slave); 476 error = wait_for_xfer(sc, true); 477 return (i2c_error_handler(sc, error)); 478} 479 480static int 481i2c_start(device_t dev, u_char slave, int timeout) 482{ 483 struct i2c_softc *sc; 484 int error; 485 486 sc = device_get_softc(dev); 487 488 /* 489 * Invoke the low-level code to put the bus into master mode and address 490 * the given slave. If that fails, idle the controller and attempt a 491 * bus recovery, and then try again one time. Signaling a start and 492 * addressing the slave is the only operation that a low-level driver 493 * can safely retry without any help from the upper layers that know 494 * more about the slave device. 495 */ 496 if ((error = i2c_start_ll(dev, slave, timeout)) != 0) { 497 i2c_write_reg(sc, I2C_CONTROL_REG, 0x0); 498 if ((error = i2c_recover_bus(sc)) != 0) 499 return (error); 500 error = i2c_start_ll(dev, slave, timeout); 501 } 502 return (error); 503} 504 505static int 506i2c_stop(device_t dev) 507{ 508 struct i2c_softc *sc; 509 510 sc = device_get_softc(dev); 511 512 i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN); 513 wait_for_busbusy(sc, false); 514 i2c_write_reg(sc, I2C_CONTROL_REG, 0); 515 return (IIC_NOERR); 516} 517 518static int 519i2c_reset(device_t dev, u_char speed, u_char addr, u_char *oldadr) 520{ 521 struct i2c_softc *sc; 522 u_int busfreq, div, i, ipgfreq; 523 524 sc = device_get_softc(dev); 525 526 /* 527 * Look up the divisor that gives the nearest speed that doesn't exceed 528 * the configured value for the bus. 529 */ 530 ipgfreq = imx_ccm_ipg_hz(); 531 busfreq = IICBUS_GET_FREQUENCY(sc->iicbus, speed); 532 div = howmany(ipgfreq, busfreq); 533 for (i = 0; i < nitems(clkdiv_table); i++) { 534 if (clkdiv_table[i].divisor >= div) 535 break; 536 } 537 538 /* 539 * Calculate roughly how long it will take to transfer a byte (which 540 * requires 9 clock cycles) at the new bus speed. This value is used to 541 * pause() while waiting for transfer-complete. With a 66MHz IPG clock 542 * and the actual i2c bus speeds that leads to, for nominal 100KHz and 543 * 400KHz bus speeds the transfer times are roughly 104uS and 22uS. 544 */ 545 busfreq = ipgfreq / clkdiv_table[i].divisor; 546 sc->byte_time_sbt = SBT_1US * (9000000 / busfreq); 547 548 /* 549 * Disable the controller (do the reset), and set the new clock divisor. 550 */ 551 i2c_write_reg(sc, I2C_STATUS_REG, 0x0); 552 i2c_write_reg(sc, I2C_CONTROL_REG, 0x0); 553 i2c_write_reg(sc, I2C_FDR_REG, (uint8_t)clkdiv_table[i].regcode); 554 555 /* 556 * Now that the controller is idle, perform bus recovery. If the bus 557 * isn't hung, this a fairly fast no-op. 558 */ 559 return (i2c_recover_bus(sc)); 560} 561 562static int 563i2c_read(device_t dev, char *buf, int len, int *read, int last, int delay) 564{ 565 struct i2c_softc *sc; 566 int error, reg; 567 568 sc = device_get_softc(dev); 569 *read = 0; 570 571 if (len) { 572 if (len == 1) 573 i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN | 574 I2CCR_MSTA | I2CCR_TXAK); 575 else 576 i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN | 577 I2CCR_MSTA); 578 /* Dummy read to prime the receiver. */ 579 i2c_write_reg(sc, I2C_STATUS_REG, 0x0); 580 i2c_read_reg(sc, I2C_DATA_REG); 581 } 582 583 error = 0; 584 *read = 0; 585 while (*read < len) { 586 if ((error = wait_for_xfer(sc, false)) != IIC_NOERR) 587 break; 588 i2c_write_reg(sc, I2C_STATUS_REG, 0x0); 589 if (last) { 590 if (*read == len - 2) { 591 /* NO ACK on last byte */ 592 i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN | 593 I2CCR_MSTA | I2CCR_TXAK); 594 } else if (*read == len - 1) { 595 /* Transfer done, signal stop. */ 596 i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN | 597 I2CCR_TXAK); 598 wait_for_busbusy(sc, false); 599 } 600 } 601 reg = i2c_read_reg(sc, I2C_DATA_REG); 602 *buf++ = reg; 603 (*read)++; 604 } 605 606 return (i2c_error_handler(sc, error)); 607} 608 609static int 610i2c_write(device_t dev, const char *buf, int len, int *sent, int timeout) 611{ 612 struct i2c_softc *sc; 613 int error; 614 615 sc = device_get_softc(dev); 616 617 error = 0; 618 *sent = 0; 619 while (*sent < len) { 620 i2c_write_reg(sc, I2C_STATUS_REG, 0x0); 621 i2c_write_reg(sc, I2C_DATA_REG, *buf++); 622 if ((error = wait_for_xfer(sc, true)) != IIC_NOERR) 623 break; 624 (*sent)++; 625 } 626 627 return (i2c_error_handler(sc, error)); 628} 629