imx_i2c.c revision 268977
1/*- 2 * Copyright (C) 2008-2009 Semihalf, Michal Hajduk 3 * Copyright (c) 2012, 2013 The FreeBSD Foundation 4 * All rights reserved. 5 * 6 * Portions of this software were developed by Oleksandr Rybalko 7 * under sponsorship from the FreeBSD Foundation. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31#include <sys/cdefs.h> 32__FBSDID("$FreeBSD: head/sys/arm/freescale/imx/imx_i2c.c 268977 2014-07-22 04:39:32Z br $"); 33 34#include <sys/param.h> 35#include <sys/systm.h> 36#include <sys/bus.h> 37#include <sys/kernel.h> 38#include <sys/module.h> 39#include <sys/resource.h> 40 41#include <machine/bus.h> 42#include <machine/resource.h> 43#include <sys/rman.h> 44 45#include <sys/lock.h> 46#include <sys/mutex.h> 47 48#include <dev/iicbus/iiconf.h> 49#include <dev/iicbus/iicbus.h> 50#include "iicbus_if.h" 51 52#include <dev/fdt/fdt_common.h> 53#include <dev/ofw/openfirm.h> 54#include <dev/ofw/ofw_bus.h> 55#include <dev/ofw/ofw_bus_subr.h> 56 57#define I2C_ADDR_REG 0x00 /* I2C slave address register */ 58#define I2C_FDR_REG 0x04 /* I2C frequency divider register */ 59#define I2C_CONTROL_REG 0x08 /* I2C control register */ 60#define I2C_STATUS_REG 0x0C /* I2C status register */ 61#define I2C_DATA_REG 0x10 /* I2C data register */ 62#define I2C_DFSRR_REG 0x14 /* I2C Digital Filter Sampling rate */ 63 64#define I2CCR_MEN (1 << 7) /* Module enable */ 65#define I2CCR_MSTA (1 << 5) /* Master/slave mode */ 66#define I2CCR_MTX (1 << 4) /* Transmit/receive mode */ 67#define I2CCR_TXAK (1 << 3) /* Transfer acknowledge */ 68#define I2CCR_RSTA (1 << 2) /* Repeated START */ 69 70#define I2CSR_MCF (1 << 7) /* Data transfer */ 71#define I2CSR_MASS (1 << 6) /* Addressed as a slave */ 72#define I2CSR_MBB (1 << 5) /* Bus busy */ 73#define I2CSR_MAL (1 << 4) /* Arbitration lost */ 74#define I2CSR_SRW (1 << 2) /* Slave read/write */ 75#define I2CSR_MIF (1 << 1) /* Module interrupt */ 76#define I2CSR_RXAK (1 << 0) /* Received acknowledge */ 77 78#define I2C_BAUD_RATE_FAST 0x31 79#define I2C_BAUD_RATE_DEF 0x3F 80#define I2C_DFSSR_DIV 0x10 81 82#ifdef DEBUG 83#define debugf(fmt, args...) do { printf("%s(): ", __func__); \ 84 printf(fmt,##args); } while (0) 85#else 86#define debugf(fmt, args...) 87#endif 88 89static struct ofw_compat_data compat_data[] = { 90 {"fsl,imx6q-i2c", 1}, 91 {"fsl,imx-i2c", 1}, 92 {NULL, 0} 93}; 94 95struct i2c_softc { 96 device_t dev; 97 device_t iicbus; 98 struct resource *res; 99 struct mtx mutex; 100 int rid; 101 bus_space_handle_t bsh; 102 bus_space_tag_t bst; 103}; 104 105static phandle_t i2c_get_node(device_t, device_t); 106static int i2c_probe(device_t); 107static int i2c_attach(device_t); 108 109static int i2c_repeated_start(device_t, u_char, int); 110static int i2c_start(device_t, u_char, int); 111static int i2c_stop(device_t); 112static int i2c_reset(device_t, u_char, u_char, u_char *); 113static int i2c_read(device_t, char *, int, int *, int, int); 114static int i2c_write(device_t, const char *, int, int *, int); 115 116static device_method_t i2c_methods[] = { 117 DEVMETHOD(device_probe, i2c_probe), 118 DEVMETHOD(device_attach, i2c_attach), 119 120 /* OFW methods */ 121 DEVMETHOD(ofw_bus_get_node, i2c_get_node), 122 123 DEVMETHOD(iicbus_callback, iicbus_null_callback), 124 DEVMETHOD(iicbus_repeated_start, i2c_repeated_start), 125 DEVMETHOD(iicbus_start, i2c_start), 126 DEVMETHOD(iicbus_stop, i2c_stop), 127 DEVMETHOD(iicbus_reset, i2c_reset), 128 DEVMETHOD(iicbus_read, i2c_read), 129 DEVMETHOD(iicbus_write, i2c_write), 130 DEVMETHOD(iicbus_transfer, iicbus_transfer_gen), 131 132 { 0, 0 } 133}; 134 135static driver_t i2c_driver = { 136 "iichb", 137 i2c_methods, 138 sizeof(struct i2c_softc), 139}; 140static devclass_t i2c_devclass; 141 142DRIVER_MODULE(i2c, simplebus, i2c_driver, i2c_devclass, 0, 0); 143DRIVER_MODULE(iicbus, i2c, iicbus_driver, iicbus_devclass, 0, 0); 144 145static phandle_t 146i2c_get_node(device_t bus, device_t dev) 147{ 148 /* 149 * Share controller node with iicbus device 150 */ 151 return ofw_bus_get_node(bus); 152} 153 154static __inline void 155i2c_write_reg(struct i2c_softc *sc, bus_size_t off, uint8_t val) 156{ 157 158 bus_space_write_1(sc->bst, sc->bsh, off, val); 159} 160 161static __inline uint8_t 162i2c_read_reg(struct i2c_softc *sc, bus_size_t off) 163{ 164 165 return (bus_space_read_1(sc->bst, sc->bsh, off)); 166} 167 168static __inline void 169i2c_flag_set(struct i2c_softc *sc, bus_size_t off, uint8_t mask) 170{ 171 uint8_t status; 172 173 status = i2c_read_reg(sc, off); 174 status |= mask; 175 i2c_write_reg(sc, off, status); 176} 177 178/* Wait for transfer interrupt flag */ 179static int 180wait_for_iif(struct i2c_softc *sc) 181{ 182 int retry; 183 184 retry = 1000; 185 while (retry --) { 186 if (i2c_read_reg(sc, I2C_STATUS_REG) & I2CSR_MIF) 187 return (IIC_NOERR); 188 DELAY(10); 189 } 190 191 return (IIC_ETIMEOUT); 192} 193 194/* Wait for free bus */ 195static int 196wait_for_nibb(struct i2c_softc *sc) 197{ 198 int retry; 199 200 retry = 1000; 201 while (retry --) { 202 if ((i2c_read_reg(sc, I2C_STATUS_REG) & I2CSR_MBB) == 0) 203 return (IIC_NOERR); 204 DELAY(10); 205 } 206 207 return (IIC_ETIMEOUT); 208} 209 210/* Wait for transfer complete+interrupt flag */ 211static int 212wait_for_icf(struct i2c_softc *sc) 213{ 214 int retry; 215 216 retry = 1000; 217 while (retry --) { 218 219 if ((i2c_read_reg(sc, I2C_STATUS_REG) & 220 (I2CSR_MCF|I2CSR_MIF)) == (I2CSR_MCF|I2CSR_MIF)) 221 return (IIC_NOERR); 222 DELAY(10); 223 } 224 225 return (IIC_ETIMEOUT); 226} 227 228static int 229i2c_probe(device_t dev) 230{ 231 struct i2c_softc *sc; 232 233 if (!ofw_bus_status_okay(dev)) 234 return (ENXIO); 235 236 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 237 return (ENXIO); 238 239 sc = device_get_softc(dev); 240 sc->rid = 0; 241 242 sc->res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->rid, 243 RF_ACTIVE); 244 if (sc->res == NULL) { 245 device_printf(dev, "could not allocate resources\n"); 246 return (ENXIO); 247 } 248 249 sc->bst = rman_get_bustag(sc->res); 250 sc->bsh = rman_get_bushandle(sc->res); 251 252 /* Enable I2C */ 253 i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN); 254 bus_release_resource(dev, SYS_RES_MEMORY, sc->rid, sc->res); 255 device_set_desc(dev, "Freescale i.MX I2C bus controller"); 256 257 return (BUS_PROBE_DEFAULT); 258} 259 260static int 261i2c_attach(device_t dev) 262{ 263 struct i2c_softc *sc; 264 265 sc = device_get_softc(dev); 266 sc->dev = dev; 267 sc->rid = 0; 268 269 mtx_init(&sc->mutex, device_get_nameunit(dev), "I2C", MTX_DEF); 270 271 sc->res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->rid, 272 RF_ACTIVE); 273 if (sc->res == NULL) { 274 device_printf(dev, "could not allocate resources"); 275 mtx_destroy(&sc->mutex); 276 return (ENXIO); 277 } 278 279 sc->bst = rman_get_bustag(sc->res); 280 sc->bsh = rman_get_bushandle(sc->res); 281 282 sc->iicbus = device_add_child(dev, "iicbus", -1); 283 if (sc->iicbus == NULL) { 284 device_printf(dev, "could not add iicbus child"); 285 mtx_destroy(&sc->mutex); 286 return (ENXIO); 287 } 288 289 bus_generic_attach(dev); 290 return (IIC_NOERR); 291} 292 293static int 294i2c_repeated_start(device_t dev, u_char slave, int timeout) 295{ 296 struct i2c_softc *sc; 297 int error; 298 299 sc = device_get_softc(dev); 300 301 mtx_lock(&sc->mutex); 302 303 i2c_write_reg(sc, I2C_ADDR_REG, slave); 304 if ((i2c_read_reg(sc, I2C_STATUS_REG) & I2CSR_MBB) == 0) { 305 mtx_unlock(&sc->mutex); 306 return (IIC_EBUSBSY); 307 } 308 309 /* Set repeated start condition */ 310 DELAY(10); 311 i2c_flag_set(sc, I2C_CONTROL_REG, I2CCR_RSTA); 312 DELAY(10); 313 /* Clear status */ 314 i2c_write_reg(sc, I2C_STATUS_REG, 0x0); 315 /* Write target address - LSB is R/W bit */ 316 i2c_write_reg(sc, I2C_DATA_REG, slave); 317 318 error = wait_for_iif(sc); 319 320 /* Clear status */ 321 i2c_write_reg(sc, I2C_STATUS_REG, 0x0); 322 323 mtx_unlock(&sc->mutex); 324 325 if (error) 326 return (error); 327 328 return (IIC_NOERR); 329} 330 331static int 332i2c_start(device_t dev, u_char slave, int timeout) 333{ 334 struct i2c_softc *sc; 335 int error; 336 337 sc = device_get_softc(dev); 338 339 mtx_lock(&sc->mutex); 340 i2c_write_reg(sc, I2C_ADDR_REG, slave); 341 if (i2c_read_reg(sc, I2C_STATUS_REG) & I2CSR_MBB) { 342 mtx_unlock(&sc->mutex); 343 return (IIC_EBUSBSY); 344 } 345 346 /* Set start condition */ 347 i2c_write_reg(sc, I2C_CONTROL_REG, 348 I2CCR_MEN | I2CCR_MSTA | I2CCR_TXAK); 349 DELAY(100); 350 i2c_write_reg(sc, I2C_CONTROL_REG, 351 I2CCR_MEN | I2CCR_MSTA | I2CCR_MTX | I2CCR_TXAK); 352 /* Clear status */ 353 i2c_write_reg(sc, I2C_STATUS_REG, 0x0); 354 /* Write target address - LSB is R/W bit */ 355 i2c_write_reg(sc, I2C_DATA_REG, slave); 356 357 error = wait_for_iif(sc); 358 359 mtx_unlock(&sc->mutex); 360 if (error) 361 return (error); 362 363 return (IIC_NOERR); 364} 365 366 367static int 368i2c_stop(device_t dev) 369{ 370 struct i2c_softc *sc; 371 372 sc = device_get_softc(dev); 373 mtx_lock(&sc->mutex); 374 i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN | I2CCR_TXAK); 375 DELAY(100); 376 /* Reset controller if bus still busy after STOP */ 377 if (wait_for_nibb(sc) == IIC_ETIMEOUT) { 378 i2c_write_reg(sc, I2C_CONTROL_REG, 0); 379 DELAY(1000); 380 i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN | I2CCR_TXAK); 381 382 i2c_write_reg(sc, I2C_STATUS_REG, 0x0); 383 } 384 mtx_unlock(&sc->mutex); 385 386 return (IIC_NOERR); 387} 388 389static int 390i2c_reset(device_t dev, u_char speed, u_char addr, u_char *oldadr) 391{ 392 struct i2c_softc *sc; 393 uint8_t baud_rate; 394 395 sc = device_get_softc(dev); 396 397 switch (speed) { 398 case IIC_FAST: 399 baud_rate = I2C_BAUD_RATE_FAST; 400 break; 401 case IIC_SLOW: 402 case IIC_UNKNOWN: 403 case IIC_FASTEST: 404 default: 405 baud_rate = I2C_BAUD_RATE_DEF; 406 break; 407 } 408 409 mtx_lock(&sc->mutex); 410 i2c_write_reg(sc, I2C_CONTROL_REG, 0x0); 411 i2c_write_reg(sc, I2C_STATUS_REG, 0x0); 412 DELAY(1000); 413 414 i2c_write_reg(sc, I2C_FDR_REG, 20); 415 i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN); 416 DELAY(1000); 417 i2c_write_reg(sc, I2C_STATUS_REG, 0x0); 418 mtx_unlock(&sc->mutex); 419 420 return (IIC_NOERR); 421} 422 423static int 424i2c_read(device_t dev, char *buf, int len, int *read, int last, int delay) 425{ 426 struct i2c_softc *sc; 427 int error, reg; 428 429 sc = device_get_softc(dev); 430 *read = 0; 431 432 mtx_lock(&sc->mutex); 433 434 if (len) { 435 if (len == 1) 436 i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN | 437 I2CCR_MSTA | I2CCR_TXAK); 438 439 else 440 i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN | 441 I2CCR_MSTA); 442 443 /* dummy read */ 444 i2c_read_reg(sc, I2C_DATA_REG); 445 DELAY(1000); 446 } 447 448 while (*read < len) { 449 error = wait_for_icf(sc); 450 if (error) { 451 mtx_unlock(&sc->mutex); 452 return (error); 453 } 454 i2c_write_reg(sc, I2C_STATUS_REG, 0x0); 455 if ((*read == len - 2) && last) { 456 /* NO ACK on last byte */ 457 i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN | 458 I2CCR_MSTA | I2CCR_TXAK); 459 } 460 461 if ((*read == len - 1) && last) { 462 /* Transfer done, remove master bit */ 463 i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN | 464 I2CCR_TXAK); 465 } 466 467 reg = i2c_read_reg(sc, I2C_DATA_REG); 468 *buf++ = reg; 469 (*read)++; 470 } 471 mtx_unlock(&sc->mutex); 472 473 return (IIC_NOERR); 474} 475 476static int 477i2c_write(device_t dev, const char *buf, int len, int *sent, int timeout) 478{ 479 struct i2c_softc *sc; 480 int error; 481 482 sc = device_get_softc(dev); 483 *sent = 0; 484 485 mtx_lock(&sc->mutex); 486 while (*sent < len) { 487 i2c_write_reg(sc, I2C_STATUS_REG, 0x0); 488 i2c_write_reg(sc, I2C_DATA_REG, *buf++); 489 490 error = wait_for_iif(sc); 491 if (error) { 492 mtx_unlock(&sc->mutex); 493 return (error); 494 } 495 496 (*sent)++; 497 } 498 mtx_unlock(&sc->mutex); 499 500 return (IIC_NOERR); 501} 502