imx_gpio.c revision 324755
1/*- 2 * Copyright (c) 2012, 2013 The FreeBSD Foundation 3 * All rights reserved. 4 * 5 * This software was developed by Oleksandr Rybalko under sponsorship 6 * from the FreeBSD Foundation. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30/* 31 * Freescale i.MX515 GPIO driver. 32 */ 33 34#include <sys/cdefs.h> 35__FBSDID("$FreeBSD: stable/11/sys/arm/freescale/imx/imx_gpio.c 324755 2017-10-19 16:07:57Z ian $"); 36 37#include "opt_platform.h" 38 39#include <sys/param.h> 40#include <sys/systm.h> 41#include <sys/bus.h> 42 43#include <sys/kernel.h> 44#include <sys/module.h> 45#include <sys/rman.h> 46#include <sys/lock.h> 47#include <sys/mutex.h> 48#include <sys/gpio.h> 49#include <sys/proc.h> 50 51#include <machine/bus.h> 52#include <machine/intr.h> 53#include <machine/resource.h> 54 55#include <dev/fdt/fdt_common.h> 56#include <dev/gpio/gpiobusvar.h> 57#include <dev/ofw/openfirm.h> 58#include <dev/ofw/ofw_bus.h> 59#include <dev/ofw/ofw_bus_subr.h> 60 61#include "gpio_if.h" 62 63#ifdef INTRNG 64#include "pic_if.h" 65#endif 66 67#define WRITE4(_sc, _r, _v) \ 68 bus_space_write_4((_sc)->sc_iot, (_sc)->sc_ioh, (_r), (_v)) 69#define READ4(_sc, _r) \ 70 bus_space_read_4((_sc)->sc_iot, (_sc)->sc_ioh, (_r)) 71#define SET4(_sc, _r, _m) \ 72 WRITE4((_sc), (_r), READ4((_sc), (_r)) | (_m)) 73#define CLEAR4(_sc, _r, _m) \ 74 WRITE4((_sc), (_r), READ4((_sc), (_r)) & ~(_m)) 75 76/* Registers definition for Freescale i.MX515 GPIO controller */ 77 78#define IMX_GPIO_DR_REG 0x000 /* Pin Data */ 79#define IMX_GPIO_OE_REG 0x004 /* Set Pin Output */ 80#define IMX_GPIO_PSR_REG 0x008 /* Pad Status */ 81#define IMX_GPIO_ICR1_REG 0x00C /* Interrupt Configuration */ 82#define IMX_GPIO_ICR2_REG 0x010 /* Interrupt Configuration */ 83#define GPIO_ICR_COND_LOW 0 84#define GPIO_ICR_COND_HIGH 1 85#define GPIO_ICR_COND_RISE 2 86#define GPIO_ICR_COND_FALL 3 87#define GPIO_ICR_COND_MASK 0x3 88#define IMX_GPIO_IMR_REG 0x014 /* Interrupt Mask Register */ 89#define IMX_GPIO_ISR_REG 0x018 /* Interrupt Status Register */ 90#define IMX_GPIO_EDGE_REG 0x01C /* Edge Detect Register */ 91 92#ifdef INTRNG 93#define DEFAULT_CAPS (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | \ 94 GPIO_INTR_LEVEL_LOW | GPIO_INTR_LEVEL_HIGH | GPIO_INTR_EDGE_RISING | \ 95 GPIO_INTR_EDGE_FALLING | GPIO_INTR_EDGE_BOTH) 96#else 97#define DEFAULT_CAPS (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT) 98#endif 99 100#define NGPIO 32 101 102#ifdef INTRNG 103struct gpio_irqsrc { 104 struct intr_irqsrc gi_isrc; 105 u_int gi_irq; 106 uint32_t gi_mode; 107}; 108#endif 109 110struct imx51_gpio_softc { 111 device_t dev; 112 device_t sc_busdev; 113 struct mtx sc_mtx; 114 struct resource *sc_res[3]; /* 1 x mem, 2 x IRQ */ 115 void *gpio_ih[2]; 116 bus_space_tag_t sc_iot; 117 bus_space_handle_t sc_ioh; 118 int gpio_npins; 119 struct gpio_pin gpio_pins[NGPIO]; 120#ifdef INTRNG 121 struct gpio_irqsrc gpio_pic_irqsrc[NGPIO]; 122#endif 123}; 124 125static struct ofw_compat_data compat_data[] = { 126 {"fsl,imx6q-gpio", 1}, 127 {"fsl,imx53-gpio", 1}, 128 {"fsl,imx51-gpio", 1}, 129 {NULL, 0} 130}; 131 132static struct resource_spec imx_gpio_spec[] = { 133 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 134 { SYS_RES_IRQ, 0, RF_ACTIVE }, 135 { SYS_RES_IRQ, 1, RF_ACTIVE }, 136 { -1, 0 } 137}; 138 139/* 140 * Helpers 141 */ 142static void imx51_gpio_pin_configure(struct imx51_gpio_softc *, 143 struct gpio_pin *, uint32_t); 144 145/* 146 * Driver stuff 147 */ 148static int imx51_gpio_probe(device_t); 149static int imx51_gpio_attach(device_t); 150static int imx51_gpio_detach(device_t); 151 152/* 153 * GPIO interface 154 */ 155static device_t imx51_gpio_get_bus(device_t); 156static int imx51_gpio_pin_max(device_t, int *); 157static int imx51_gpio_pin_getcaps(device_t, uint32_t, uint32_t *); 158static int imx51_gpio_pin_getflags(device_t, uint32_t, uint32_t *); 159static int imx51_gpio_pin_getname(device_t, uint32_t, char *); 160static int imx51_gpio_pin_setflags(device_t, uint32_t, uint32_t); 161static int imx51_gpio_pin_set(device_t, uint32_t, unsigned int); 162static int imx51_gpio_pin_get(device_t, uint32_t, unsigned int *); 163static int imx51_gpio_pin_toggle(device_t, uint32_t pin); 164 165#ifdef INTRNG 166static int 167gpio_pic_map_fdt(struct imx51_gpio_softc *sc, struct intr_map_data_fdt *daf, 168 u_int *irqp, uint32_t *modep) 169{ 170 u_int irq; 171 uint32_t mode; 172 173 /* 174 * From devicetree/bindings/gpio/fsl-imx-gpio.txt: 175 * #interrupt-cells: 2. The first cell is the GPIO number. The second 176 * cell bits[3:0] is used to specify trigger type and level flags: 177 * 1 = low-to-high edge triggered. 178 * 2 = high-to-low edge triggered. 179 * 4 = active high level-sensitive. 180 * 8 = active low level-sensitive. 181 * We can do any single one of these modes, and also edge low+high 182 * (i.e., trigger on both edges); other combinations are not supported. 183 */ 184 185 if (daf->ncells != 2) { 186 device_printf(sc->dev, "Invalid #interrupt-cells\n"); 187 return (EINVAL); 188 } 189 190 irq = daf->cells[0]; 191 if (irq >= sc->gpio_npins) { 192 device_printf(sc->dev, "Invalid interrupt number %u\n", irq); 193 return (EINVAL); 194 } 195 switch (daf->cells[1]) { 196 case 1: 197 mode = GPIO_INTR_EDGE_RISING; 198 break; 199 case 2: 200 mode = GPIO_INTR_EDGE_FALLING; 201 break; 202 case 3: 203 mode = GPIO_INTR_EDGE_BOTH; 204 break; 205 case 4: 206 mode = GPIO_INTR_LEVEL_HIGH; 207 break; 208 case 8: 209 mode = GPIO_INTR_LEVEL_LOW; 210 break; 211 default: 212 device_printf(sc->dev, "Unsupported interrupt mode 0x%2x\n", 213 daf->cells[1]); 214 return (ENOTSUP); 215 } 216 *irqp = irq; 217 if (modep != NULL) 218 *modep = mode; 219 return (0); 220} 221 222static int 223gpio_pic_map_gpio(struct imx51_gpio_softc *sc, struct intr_map_data_gpio *dag, 224 u_int *irqp, uint32_t *modep) 225{ 226 u_int irq; 227 228 irq = dag->gpio_pin_num; 229 if (irq >= sc->gpio_npins) { 230 device_printf(sc->dev, "Invalid interrupt number %u\n", irq); 231 return (EINVAL); 232 } 233 234 switch (dag->gpio_intr_mode) { 235 case GPIO_INTR_LEVEL_LOW: 236 case GPIO_INTR_LEVEL_HIGH: 237 case GPIO_INTR_EDGE_RISING: 238 case GPIO_INTR_EDGE_FALLING: 239 case GPIO_INTR_EDGE_BOTH: 240 break; 241 default: 242 device_printf(sc->dev, "Unsupported interrupt mode 0x%8x\n", 243 dag->gpio_intr_mode); 244 return (EINVAL); 245 } 246 247 *irqp = irq; 248 if (modep != NULL) 249 *modep = dag->gpio_intr_mode; 250 return (0); 251} 252 253static int 254gpio_pic_map(struct imx51_gpio_softc *sc, struct intr_map_data *data, 255 u_int *irqp, uint32_t *modep) 256{ 257 258 switch (data->type) { 259 case INTR_MAP_DATA_FDT: 260 return (gpio_pic_map_fdt(sc, (struct intr_map_data_fdt *)data, 261 irqp, modep)); 262 case INTR_MAP_DATA_GPIO: 263 return (gpio_pic_map_gpio(sc, (struct intr_map_data_gpio *)data, 264 irqp, modep)); 265 default: 266 return (ENOTSUP); 267 } 268} 269 270static int 271gpio_pic_map_intr(device_t dev, struct intr_map_data *data, 272 struct intr_irqsrc **isrcp) 273{ 274 int error; 275 u_int irq; 276 struct imx51_gpio_softc *sc; 277 278 sc = device_get_softc(dev); 279 error = gpio_pic_map(sc, data, &irq, NULL); 280 if (error == 0) 281 *isrcp = &sc->gpio_pic_irqsrc[irq].gi_isrc; 282 return (error); 283} 284 285static int 286gpio_pic_teardown_intr(device_t dev, struct intr_irqsrc *isrc, 287 struct resource *res, struct intr_map_data *data) 288{ 289 struct imx51_gpio_softc *sc; 290 struct gpio_irqsrc *gi; 291 292 sc = device_get_softc(dev); 293 if (isrc->isrc_handlers == 0) { 294 gi = (struct gpio_irqsrc *)isrc; 295 gi->gi_mode = GPIO_INTR_CONFORM; 296 297 // XXX Not sure this is necessary 298 mtx_lock_spin(&sc->sc_mtx); 299 CLEAR4(sc, IMX_GPIO_IMR_REG, (1U << gi->gi_irq)); 300 WRITE4(sc, IMX_GPIO_ISR_REG, (1U << gi->gi_irq)); 301 mtx_unlock_spin(&sc->sc_mtx); 302 } 303 return (0); 304} 305 306static int 307gpio_pic_setup_intr(device_t dev, struct intr_irqsrc *isrc, 308 struct resource *res, struct intr_map_data *data) 309{ 310 struct imx51_gpio_softc *sc; 311 struct gpio_irqsrc *gi; 312 int error; 313 u_int icfg, irq, reg, shift, wrk; 314 uint32_t mode; 315 316 if (data == NULL) 317 return (ENOTSUP); 318 319 sc = device_get_softc(dev); 320 gi = (struct gpio_irqsrc *)isrc; 321 322 /* Get config for interrupt. */ 323 error = gpio_pic_map(sc, data, &irq, &mode); 324 if (error != 0) 325 return (error); 326 if (gi->gi_irq != irq) 327 return (EINVAL); 328 329 /* Compare config if this is not first setup. */ 330 if (isrc->isrc_handlers != 0) 331 return (gi->gi_mode == mode ? 0 : EINVAL); 332 gi->gi_mode = mode; 333 334 /* 335 * To interrupt on both edges we have to use the EDGE register. The 336 * manual says it only exists for backwards compatibilty with older imx 337 * chips, but it's also the only way to configure interrupting on both 338 * edges. If the EDGE bit is on, the corresponding ICRn bit is ignored. 339 */ 340 mtx_lock_spin(&sc->sc_mtx); 341 if (mode == GPIO_INTR_EDGE_BOTH) { 342 SET4(sc, IMX_GPIO_EDGE_REG, (1u << irq)); 343 } else { 344 CLEAR4(sc, IMX_GPIO_EDGE_REG, (1u << irq)); 345 switch (mode) { 346 default: 347 /* silence warnings; default can't actually happen. */ 348 /* FALLTHROUGH */ 349 case GPIO_INTR_LEVEL_LOW: 350 icfg = GPIO_ICR_COND_LOW; 351 break; 352 case GPIO_INTR_LEVEL_HIGH: 353 icfg = GPIO_ICR_COND_HIGH; 354 break; 355 case GPIO_INTR_EDGE_RISING: 356 icfg = GPIO_ICR_COND_RISE; 357 break; 358 case GPIO_INTR_EDGE_FALLING: 359 icfg = GPIO_ICR_COND_FALL; 360 break; 361 } 362 if (irq < 16) { 363 reg = IMX_GPIO_ICR1_REG; 364 shift = 2 * irq; 365 } else { 366 reg = IMX_GPIO_ICR2_REG; 367 shift = 2 * (irq - 16); 368 } 369 wrk = READ4(sc, reg); 370 wrk &= ~(GPIO_ICR_COND_MASK << shift); 371 wrk |= icfg << shift; 372 WRITE4(sc, reg, wrk); 373 } 374 WRITE4(sc, IMX_GPIO_ISR_REG, (1u << irq)); 375 SET4(sc, IMX_GPIO_IMR_REG, (1u << irq)); 376 mtx_unlock_spin(&sc->sc_mtx); 377 378 return (0); 379} 380 381/* 382 * this is mask_intr 383 */ 384static void 385gpio_pic_disable_intr(device_t dev, struct intr_irqsrc *isrc) 386{ 387 struct imx51_gpio_softc *sc; 388 u_int irq; 389 390 sc = device_get_softc(dev); 391 irq = ((struct gpio_irqsrc *)isrc)->gi_irq; 392 393 mtx_lock_spin(&sc->sc_mtx); 394 CLEAR4(sc, IMX_GPIO_IMR_REG, (1U << irq)); 395 mtx_unlock_spin(&sc->sc_mtx); 396} 397 398/* 399 * this is unmask_intr 400 */ 401static void 402gpio_pic_enable_intr(device_t dev, struct intr_irqsrc *isrc) 403{ 404 struct imx51_gpio_softc *sc; 405 u_int irq; 406 407 sc = device_get_softc(dev); 408 irq = ((struct gpio_irqsrc *)isrc)->gi_irq; 409 410 mtx_lock_spin(&sc->sc_mtx); 411 SET4(sc, IMX_GPIO_IMR_REG, (1U << irq)); 412 mtx_unlock_spin(&sc->sc_mtx); 413} 414 415static void 416gpio_pic_post_filter(device_t dev, struct intr_irqsrc *isrc) 417{ 418 struct imx51_gpio_softc *sc; 419 u_int irq; 420 421 sc = device_get_softc(dev); 422 irq = ((struct gpio_irqsrc *)isrc)->gi_irq; 423 424 arm_irq_memory_barrier(0); 425 /* EOI. W1C reg so no r-m-w, no locking needed. */ 426 WRITE4(sc, IMX_GPIO_ISR_REG, (1U << irq)); 427} 428 429static void 430gpio_pic_post_ithread(device_t dev, struct intr_irqsrc *isrc) 431{ 432 struct imx51_gpio_softc *sc; 433 u_int irq; 434 435 sc = device_get_softc(dev); 436 irq = ((struct gpio_irqsrc *)isrc)->gi_irq; 437 438 arm_irq_memory_barrier(0); 439 /* EOI. W1C reg so no r-m-w, no locking needed. */ 440 WRITE4(sc, IMX_GPIO_ISR_REG, (1U << irq)); 441 gpio_pic_enable_intr(dev, isrc); 442} 443 444static void 445gpio_pic_pre_ithread(device_t dev, struct intr_irqsrc *isrc) 446{ 447 gpio_pic_disable_intr(dev, isrc); 448} 449 450static int 451gpio_pic_filter(void *arg) 452{ 453 struct imx51_gpio_softc *sc; 454 struct intr_irqsrc *isrc; 455 uint32_t i, interrupts; 456 457 sc = arg; 458 mtx_lock_spin(&sc->sc_mtx); 459 interrupts = READ4(sc, IMX_GPIO_ISR_REG) & READ4(sc, IMX_GPIO_IMR_REG); 460 mtx_unlock_spin(&sc->sc_mtx); 461 462 for (i = 0; interrupts != 0; i++, interrupts >>= 1) { 463 if ((interrupts & 0x1) == 0) 464 continue; 465 isrc = &sc->gpio_pic_irqsrc[i].gi_isrc; 466 if (intr_isrc_dispatch(isrc, curthread->td_intr_frame) != 0) { 467 gpio_pic_disable_intr(sc->dev, isrc); 468 gpio_pic_post_filter(sc->dev, isrc); 469 device_printf(sc->dev, "Stray irq %u disabled\n", i); 470 } 471 } 472 473 return (FILTER_HANDLED); 474} 475 476/* 477 * Initialize our isrcs and register them with intrng. 478 */ 479static int 480gpio_pic_register_isrcs(struct imx51_gpio_softc *sc) 481{ 482 int error; 483 uint32_t irq; 484 const char *name; 485 486 name = device_get_nameunit(sc->dev); 487 for (irq = 0; irq < NGPIO; irq++) { 488 sc->gpio_pic_irqsrc[irq].gi_irq = irq; 489 sc->gpio_pic_irqsrc[irq].gi_mode = GPIO_INTR_CONFORM; 490 491 error = intr_isrc_register(&sc->gpio_pic_irqsrc[irq].gi_isrc, 492 sc->dev, 0, "%s,%u", name, irq); 493 if (error != 0) { 494 /* XXX call intr_isrc_deregister() */ 495 device_printf(sc->dev, "%s failed", __func__); 496 return (error); 497 } 498 } 499 return (0); 500} 501#endif 502 503/* 504 * 505 */ 506static void 507imx51_gpio_pin_configure(struct imx51_gpio_softc *sc, struct gpio_pin *pin, 508 unsigned int flags) 509{ 510 u_int newflags; 511 512 mtx_lock_spin(&sc->sc_mtx); 513 514 /* 515 * Manage input/output; other flags not supported yet. 516 * 517 * Note that changes to pin->gp_flags must be acccumulated in newflags 518 * and stored with a single writeback to gp_flags at the end, to enable 519 * unlocked reads of that value elsewhere. 520 */ 521 if (flags & (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT)) { 522 newflags = pin->gp_flags & ~(GPIO_PIN_INPUT | GPIO_PIN_OUTPUT); 523 if (flags & GPIO_PIN_OUTPUT) { 524 newflags |= GPIO_PIN_OUTPUT; 525 SET4(sc, IMX_GPIO_OE_REG, (1U << pin->gp_pin)); 526 } else { 527 newflags |= GPIO_PIN_INPUT; 528 CLEAR4(sc, IMX_GPIO_OE_REG, (1U << pin->gp_pin)); 529 } 530 pin->gp_flags = newflags; 531 } 532 533 mtx_unlock_spin(&sc->sc_mtx); 534} 535 536static device_t 537imx51_gpio_get_bus(device_t dev) 538{ 539 struct imx51_gpio_softc *sc; 540 541 sc = device_get_softc(dev); 542 543 return (sc->sc_busdev); 544} 545 546static int 547imx51_gpio_pin_max(device_t dev, int *maxpin) 548{ 549 struct imx51_gpio_softc *sc; 550 551 sc = device_get_softc(dev); 552 *maxpin = sc->gpio_npins - 1; 553 554 return (0); 555} 556 557static int 558imx51_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps) 559{ 560 struct imx51_gpio_softc *sc; 561 562 sc = device_get_softc(dev); 563 564 if (pin >= sc->gpio_npins) 565 return (EINVAL); 566 567 *caps = sc->gpio_pins[pin].gp_caps; 568 569 return (0); 570} 571 572static int 573imx51_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags) 574{ 575 struct imx51_gpio_softc *sc; 576 577 sc = device_get_softc(dev); 578 579 if (pin >= sc->gpio_npins) 580 return (EINVAL); 581 582 *flags = sc->gpio_pins[pin].gp_flags; 583 584 return (0); 585} 586 587static int 588imx51_gpio_pin_getname(device_t dev, uint32_t pin, char *name) 589{ 590 struct imx51_gpio_softc *sc; 591 592 sc = device_get_softc(dev); 593 if (pin >= sc->gpio_npins) 594 return (EINVAL); 595 596 mtx_lock_spin(&sc->sc_mtx); 597 memcpy(name, sc->gpio_pins[pin].gp_name, GPIOMAXNAME); 598 mtx_unlock_spin(&sc->sc_mtx); 599 600 return (0); 601} 602 603static int 604imx51_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags) 605{ 606 struct imx51_gpio_softc *sc; 607 608 sc = device_get_softc(dev); 609 610 if (pin >= sc->gpio_npins) 611 return (EINVAL); 612 613 imx51_gpio_pin_configure(sc, &sc->gpio_pins[pin], flags); 614 615 return (0); 616} 617 618static int 619imx51_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value) 620{ 621 struct imx51_gpio_softc *sc; 622 623 sc = device_get_softc(dev); 624 625 if (pin >= sc->gpio_npins) 626 return (EINVAL); 627 628 mtx_lock_spin(&sc->sc_mtx); 629 if (value) 630 SET4(sc, IMX_GPIO_DR_REG, (1U << pin)); 631 else 632 CLEAR4(sc, IMX_GPIO_DR_REG, (1U << pin)); 633 mtx_unlock_spin(&sc->sc_mtx); 634 635 return (0); 636} 637 638static int 639imx51_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val) 640{ 641 struct imx51_gpio_softc *sc; 642 643 sc = device_get_softc(dev); 644 645 if (pin >= sc->gpio_npins) 646 return (EINVAL); 647 648 *val = (READ4(sc, IMX_GPIO_PSR_REG) >> pin) & 1; 649 650 return (0); 651} 652 653static int 654imx51_gpio_pin_toggle(device_t dev, uint32_t pin) 655{ 656 struct imx51_gpio_softc *sc; 657 658 sc = device_get_softc(dev); 659 660 if (pin >= sc->gpio_npins) 661 return (EINVAL); 662 663 mtx_lock_spin(&sc->sc_mtx); 664 WRITE4(sc, IMX_GPIO_DR_REG, 665 (READ4(sc, IMX_GPIO_DR_REG) ^ (1U << pin))); 666 mtx_unlock_spin(&sc->sc_mtx); 667 668 return (0); 669} 670 671static int 672imx51_gpio_pin_access_32(device_t dev, uint32_t first_pin, uint32_t clear_pins, 673 uint32_t change_pins, uint32_t *orig_pins) 674{ 675 struct imx51_gpio_softc *sc; 676 677 if (first_pin != 0) 678 return (EINVAL); 679 680 sc = device_get_softc(dev); 681 682 if (orig_pins != NULL) 683 *orig_pins = READ4(sc, IMX_GPIO_PSR_REG); 684 685 if ((clear_pins | change_pins) != 0) { 686 mtx_lock_spin(&sc->sc_mtx); 687 WRITE4(sc, IMX_GPIO_DR_REG, 688 (READ4(sc, IMX_GPIO_DR_REG) & ~clear_pins) ^ change_pins); 689 mtx_unlock_spin(&sc->sc_mtx); 690 } 691 692 return (0); 693} 694 695static int 696imx51_gpio_pin_config_32(device_t dev, uint32_t first_pin, uint32_t num_pins, 697 uint32_t *pin_flags) 698{ 699 struct imx51_gpio_softc *sc; 700 u_int i; 701 uint32_t bit, drclr, drset, flags, oeclr, oeset, pads; 702 703 sc = device_get_softc(dev); 704 705 if (first_pin != 0 || num_pins > sc->gpio_npins) 706 return (EINVAL); 707 708 drclr = drset = oeclr = oeset = 0; 709 pads = READ4(sc, IMX_GPIO_PSR_REG); 710 711 for (i = 0; i < num_pins; ++i) { 712 bit = 1u << i; 713 flags = pin_flags[i]; 714 if (flags & GPIO_PIN_INPUT) { 715 oeclr |= bit; 716 } else if (flags & GPIO_PIN_OUTPUT) { 717 oeset |= bit; 718 if (flags & GPIO_PIN_PRESET_LOW) 719 drclr |= bit; 720 else if (flags & GPIO_PIN_PRESET_HIGH) 721 drset |= bit; 722 else /* Drive whatever it's now pulled to. */ 723 drset |= pads & bit; 724 } 725 } 726 727 mtx_lock_spin(&sc->sc_mtx); 728 WRITE4(sc, IMX_GPIO_DR_REG, 729 (READ4(sc, IMX_GPIO_DR_REG) & ~drclr) | drset); 730 WRITE4(sc, IMX_GPIO_OE_REG, 731 (READ4(sc, IMX_GPIO_OE_REG) & ~oeclr) | oeset); 732 mtx_unlock_spin(&sc->sc_mtx); 733 734 return (0); 735} 736 737static int 738imx51_gpio_probe(device_t dev) 739{ 740 741 if (!ofw_bus_status_okay(dev)) 742 return (ENXIO); 743 744 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data != 0) { 745 device_set_desc(dev, "Freescale i.MX GPIO Controller"); 746 return (BUS_PROBE_DEFAULT); 747 } 748 749 return (ENXIO); 750} 751 752static int 753imx51_gpio_attach(device_t dev) 754{ 755 struct imx51_gpio_softc *sc; 756 int i, irq, unit; 757 758 sc = device_get_softc(dev); 759 sc->dev = dev; 760 sc->gpio_npins = NGPIO; 761 762 mtx_init(&sc->sc_mtx, device_get_nameunit(sc->dev), NULL, MTX_SPIN); 763 764 if (bus_alloc_resources(dev, imx_gpio_spec, sc->sc_res)) { 765 device_printf(dev, "could not allocate resources\n"); 766 bus_release_resources(dev, imx_gpio_spec, sc->sc_res); 767 mtx_destroy(&sc->sc_mtx); 768 return (ENXIO); 769 } 770 771 sc->sc_iot = rman_get_bustag(sc->sc_res[0]); 772 sc->sc_ioh = rman_get_bushandle(sc->sc_res[0]); 773 /* 774 * Mask off all interrupts in hardware, then set up interrupt handling. 775 */ 776 WRITE4(sc, IMX_GPIO_IMR_REG, 0); 777 for (irq = 0; irq < 2; irq++) { 778#ifdef INTRNG 779 if ((bus_setup_intr(dev, sc->sc_res[1 + irq], INTR_TYPE_CLK, 780 gpio_pic_filter, NULL, sc, &sc->gpio_ih[irq]))) { 781 device_printf(dev, 782 "WARNING: unable to register interrupt handler\n"); 783 imx51_gpio_detach(dev); 784 return (ENXIO); 785 } 786#endif 787 } 788 789 unit = device_get_unit(dev); 790 for (i = 0; i < sc->gpio_npins; i++) { 791 sc->gpio_pins[i].gp_pin = i; 792 sc->gpio_pins[i].gp_caps = DEFAULT_CAPS; 793 sc->gpio_pins[i].gp_flags = 794 (READ4(sc, IMX_GPIO_OE_REG) & (1U << i)) ? GPIO_PIN_OUTPUT : 795 GPIO_PIN_INPUT; 796 snprintf(sc->gpio_pins[i].gp_name, GPIOMAXNAME, 797 "GPIO%d_IO%02d", unit + 1, i); 798 } 799 800#ifdef INTRNG 801 gpio_pic_register_isrcs(sc); 802 intr_pic_register(dev, OF_xref_from_node(ofw_bus_get_node(dev))); 803#endif 804 sc->sc_busdev = gpiobus_attach_bus(dev); 805 806 if (sc->sc_busdev == NULL) { 807 imx51_gpio_detach(dev); 808 return (ENXIO); 809 } 810 811 return (0); 812} 813 814static int 815imx51_gpio_detach(device_t dev) 816{ 817 int irq; 818 struct imx51_gpio_softc *sc; 819 820 sc = device_get_softc(dev); 821 822 gpiobus_detach_bus(dev); 823 for (irq = 1; irq <= 2; irq++) { 824 if (sc->gpio_ih[irq]) 825 bus_teardown_intr(dev, sc->sc_res[irq], sc->gpio_ih[irq]); 826 } 827 bus_release_resources(dev, imx_gpio_spec, sc->sc_res); 828 mtx_destroy(&sc->sc_mtx); 829 830 return(0); 831} 832 833static device_method_t imx51_gpio_methods[] = { 834 DEVMETHOD(device_probe, imx51_gpio_probe), 835 DEVMETHOD(device_attach, imx51_gpio_attach), 836 DEVMETHOD(device_detach, imx51_gpio_detach), 837 838#ifdef INTRNG 839 /* Interrupt controller interface */ 840 DEVMETHOD(pic_disable_intr, gpio_pic_disable_intr), 841 DEVMETHOD(pic_enable_intr, gpio_pic_enable_intr), 842 DEVMETHOD(pic_map_intr, gpio_pic_map_intr), 843 DEVMETHOD(pic_setup_intr, gpio_pic_setup_intr), 844 DEVMETHOD(pic_teardown_intr, gpio_pic_teardown_intr), 845 DEVMETHOD(pic_post_filter, gpio_pic_post_filter), 846 DEVMETHOD(pic_post_ithread, gpio_pic_post_ithread), 847 DEVMETHOD(pic_pre_ithread, gpio_pic_pre_ithread), 848#endif 849 850 /* GPIO protocol */ 851 DEVMETHOD(gpio_get_bus, imx51_gpio_get_bus), 852 DEVMETHOD(gpio_pin_max, imx51_gpio_pin_max), 853 DEVMETHOD(gpio_pin_getname, imx51_gpio_pin_getname), 854 DEVMETHOD(gpio_pin_getflags, imx51_gpio_pin_getflags), 855 DEVMETHOD(gpio_pin_getcaps, imx51_gpio_pin_getcaps), 856 DEVMETHOD(gpio_pin_setflags, imx51_gpio_pin_setflags), 857 DEVMETHOD(gpio_pin_get, imx51_gpio_pin_get), 858 DEVMETHOD(gpio_pin_set, imx51_gpio_pin_set), 859 DEVMETHOD(gpio_pin_toggle, imx51_gpio_pin_toggle), 860 DEVMETHOD(gpio_pin_access_32, imx51_gpio_pin_access_32), 861 DEVMETHOD(gpio_pin_config_32, imx51_gpio_pin_config_32), 862 {0, 0}, 863}; 864 865static driver_t imx51_gpio_driver = { 866 "gpio", 867 imx51_gpio_methods, 868 sizeof(struct imx51_gpio_softc), 869}; 870static devclass_t imx51_gpio_devclass; 871 872DRIVER_MODULE(imx51_gpio, simplebus, imx51_gpio_driver, imx51_gpio_devclass, 873 0, 0); 874