bcm2835_sdhci.c revision 276985
1/*- 2 * Copyright (c) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 */ 27#include <sys/cdefs.h> 28__FBSDID("$FreeBSD: head/sys/arm/broadcom/bcm2835/bcm2835_sdhci.c 276985 2015-01-11 17:00:24Z ian $"); 29 30#include <sys/param.h> 31#include <sys/systm.h> 32#include <sys/bio.h> 33#include <sys/bus.h> 34#include <sys/conf.h> 35#include <sys/endian.h> 36#include <sys/kernel.h> 37#include <sys/kthread.h> 38#include <sys/lock.h> 39#include <sys/malloc.h> 40#include <sys/module.h> 41#include <sys/mutex.h> 42#include <sys/queue.h> 43#include <sys/resource.h> 44#include <sys/rman.h> 45#include <sys/sysctl.h> 46#include <sys/taskqueue.h> 47#include <sys/time.h> 48#include <sys/timetc.h> 49#include <sys/watchdog.h> 50 51#include <sys/kdb.h> 52 53#include <machine/bus.h> 54#include <machine/cpu.h> 55#include <machine/cpufunc.h> 56#include <machine/resource.h> 57#include <machine/intr.h> 58 59#include <dev/fdt/fdt_common.h> 60#include <dev/ofw/ofw_bus.h> 61#include <dev/ofw/ofw_bus_subr.h> 62 63#include <dev/mmc/bridge.h> 64#include <dev/mmc/mmcreg.h> 65#include <dev/mmc/mmcbrvar.h> 66 67#include <dev/sdhci/sdhci.h> 68#include "sdhci_if.h" 69 70#include "bcm2835_dma.h" 71#include "bcm2835_vcbus.h" 72 73#define BCM2835_DEFAULT_SDHCI_FREQ 50 74 75#define BCM_SDHCI_BUFFER_SIZE 512 76 77#ifdef DEBUG 78#define dprintf(fmt, args...) do { printf("%s(): ", __func__); \ 79 printf(fmt,##args); } while (0) 80#else 81#define dprintf(fmt, args...) 82#endif 83 84/* 85 * Arasan HC seems to have problem with Data CRC on lower frequencies. 86 * Use this tunable to cap initialization sequence frequency at higher 87 * value. Default is standard 400kHz. 88 * HS mode brings too many problems for most of cards, so disable HS mode 89 * until a better fix comes up. 90 * HS mode still can be enabled with the tunable. 91 */ 92static int bcm2835_sdhci_min_freq = 400000; 93static int bcm2835_sdhci_hs = 0; 94static int bcm2835_sdhci_pio_mode = 0; 95 96TUNABLE_INT("hw.bcm2835.sdhci.min_freq", &bcm2835_sdhci_min_freq); 97TUNABLE_INT("hw.bcm2835.sdhci.hs", &bcm2835_sdhci_hs); 98TUNABLE_INT("hw.bcm2835.sdhci.pio_mode", &bcm2835_sdhci_pio_mode); 99 100struct bcm_sdhci_dmamap_arg { 101 bus_addr_t sc_dma_busaddr; 102}; 103 104struct bcm_sdhci_softc { 105 device_t sc_dev; 106 struct mtx sc_mtx; 107 struct resource * sc_mem_res; 108 struct resource * sc_irq_res; 109 bus_space_tag_t sc_bst; 110 bus_space_handle_t sc_bsh; 111 void * sc_intrhand; 112 struct mmc_request * sc_req; 113 struct mmc_data * sc_data; 114 uint32_t sc_flags; 115#define LPC_SD_FLAGS_IGNORECRC (1 << 0) 116 int sc_xfer_direction; 117#define DIRECTION_READ 0 118#define DIRECTION_WRITE 1 119 int sc_xfer_done; 120 int sc_bus_busy; 121 struct sdhci_slot sc_slot; 122 int sc_dma_inuse; 123 int sc_dma_ch; 124 bus_dma_tag_t sc_dma_tag; 125 bus_dmamap_t sc_dma_map; 126 vm_paddr_t sc_sdhci_buffer_phys; 127 uint32_t cmd_and_mode; 128}; 129 130static int bcm_sdhci_probe(device_t); 131static int bcm_sdhci_attach(device_t); 132static int bcm_sdhci_detach(device_t); 133static void bcm_sdhci_intr(void *); 134 135static int bcm_sdhci_get_ro(device_t, device_t); 136static void bcm_sdhci_dma_intr(int ch, void *arg); 137 138#define bcm_sdhci_lock(_sc) \ 139 mtx_lock(&_sc->sc_mtx); 140#define bcm_sdhci_unlock(_sc) \ 141 mtx_unlock(&_sc->sc_mtx); 142 143static void 144bcm_dmamap_cb(void *arg, bus_dma_segment_t *segs, 145 int nseg, int err) 146{ 147 bus_addr_t *addr; 148 149 if (err) 150 return; 151 152 addr = (bus_addr_t*)arg; 153 *addr = segs[0].ds_addr; 154} 155 156static int 157bcm_sdhci_probe(device_t dev) 158{ 159 160 if (!ofw_bus_status_okay(dev)) 161 return (ENXIO); 162 163 if (!ofw_bus_is_compatible(dev, "broadcom,bcm2835-sdhci")) 164 return (ENXIO); 165 166 device_set_desc(dev, "Broadcom 2708 SDHCI controller"); 167 return (BUS_PROBE_DEFAULT); 168} 169 170static int 171bcm_sdhci_attach(device_t dev) 172{ 173 struct bcm_sdhci_softc *sc = device_get_softc(dev); 174 int rid, err; 175 phandle_t node; 176 pcell_t cell; 177 int default_freq; 178 179 sc->sc_dev = dev; 180 sc->sc_req = NULL; 181 err = 0; 182 183 default_freq = BCM2835_DEFAULT_SDHCI_FREQ; 184 node = ofw_bus_get_node(sc->sc_dev); 185 if ((OF_getprop(node, "clock-frequency", &cell, sizeof(cell))) > 0) 186 default_freq = (int)fdt32_to_cpu(cell)/1000000; 187 188 dprintf("SDHCI frequency: %dMHz\n", default_freq); 189 190 mtx_init(&sc->sc_mtx, "bcm sdhci", "sdhci", MTX_DEF); 191 192 rid = 0; 193 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 194 RF_ACTIVE); 195 if (!sc->sc_mem_res) { 196 device_printf(dev, "cannot allocate memory window\n"); 197 err = ENXIO; 198 goto fail; 199 } 200 201 sc->sc_bst = rman_get_bustag(sc->sc_mem_res); 202 sc->sc_bsh = rman_get_bushandle(sc->sc_mem_res); 203 204 rid = 0; 205 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 206 RF_ACTIVE); 207 if (!sc->sc_irq_res) { 208 device_printf(dev, "cannot allocate interrupt\n"); 209 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); 210 err = ENXIO; 211 goto fail; 212 } 213 214 if (bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_BIO | INTR_MPSAFE, 215 NULL, bcm_sdhci_intr, sc, &sc->sc_intrhand)) 216 { 217 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); 218 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res); 219 device_printf(dev, "cannot setup interrupt handler\n"); 220 err = ENXIO; 221 goto fail; 222 } 223 224 if (!bcm2835_sdhci_pio_mode) 225 sc->sc_slot.opt = SDHCI_PLATFORM_TRANSFER; 226 227 sc->sc_slot.caps = SDHCI_CAN_VDD_330 | SDHCI_CAN_VDD_180; 228 if (bcm2835_sdhci_hs) 229 sc->sc_slot.caps |= SDHCI_CAN_DO_HISPD; 230 sc->sc_slot.caps |= (default_freq << SDHCI_CLOCK_BASE_SHIFT); 231 sc->sc_slot.quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK 232 | SDHCI_QUIRK_BROKEN_TIMEOUT_VAL 233 | SDHCI_QUIRK_MISSING_CAPS; 234 235 sdhci_init_slot(dev, &sc->sc_slot, 0); 236 237 sc->sc_dma_ch = bcm_dma_allocate(BCM_DMA_CH_FAST1); 238 if (sc->sc_dma_ch == BCM_DMA_CH_INVALID) 239 sc->sc_dma_ch = bcm_dma_allocate(BCM_DMA_CH_FAST2); 240 if (sc->sc_dma_ch == BCM_DMA_CH_INVALID) 241 sc->sc_dma_ch = bcm_dma_allocate(BCM_DMA_CH_ANY); 242 if (sc->sc_dma_ch == BCM_DMA_CH_INVALID) 243 goto fail; 244 245 bcm_dma_setup_intr(sc->sc_dma_ch, bcm_sdhci_dma_intr, sc); 246 247 /* Allocate bus_dma resources. */ 248 err = bus_dma_tag_create(bus_get_dma_tag(dev), 249 1, 0, BUS_SPACE_MAXADDR_32BIT, 250 BUS_SPACE_MAXADDR, NULL, NULL, 251 BCM_SDHCI_BUFFER_SIZE, 1, BCM_SDHCI_BUFFER_SIZE, 252 BUS_DMA_ALLOCNOW, NULL, NULL, 253 &sc->sc_dma_tag); 254 255 if (err) { 256 device_printf(dev, "failed allocate DMA tag"); 257 goto fail; 258 } 259 260 err = bus_dmamap_create(sc->sc_dma_tag, 0, &sc->sc_dma_map); 261 if (err) { 262 device_printf(dev, "bus_dmamap_create failed\n"); 263 goto fail; 264 } 265 266 sc->sc_sdhci_buffer_phys = BUS_SPACE_PHYSADDR(sc->sc_mem_res, 267 SDHCI_BUFFER); 268 269 bus_generic_probe(dev); 270 bus_generic_attach(dev); 271 272 sdhci_start_slot(&sc->sc_slot); 273 274 return (0); 275 276fail: 277 if (sc->sc_intrhand) 278 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_intrhand); 279 if (sc->sc_irq_res) 280 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res); 281 if (sc->sc_mem_res) 282 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); 283 284 return (err); 285} 286 287static int 288bcm_sdhci_detach(device_t dev) 289{ 290 291 return (EBUSY); 292} 293 294static void 295bcm_sdhci_intr(void *arg) 296{ 297 struct bcm_sdhci_softc *sc = arg; 298 299 sdhci_generic_intr(&sc->sc_slot); 300} 301 302static int 303bcm_sdhci_get_ro(device_t bus, device_t child) 304{ 305 306 return (0); 307} 308 309static inline uint32_t 310RD4(struct bcm_sdhci_softc *sc, bus_size_t off) 311{ 312 uint32_t val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, off); 313 return val; 314} 315 316static inline void 317WR4(struct bcm_sdhci_softc *sc, bus_size_t off, uint32_t val) 318{ 319 320 bus_space_write_4(sc->sc_bst, sc->sc_bsh, off, val); 321 /* 322 * The Arasan HC has a bug where it may lose the content of 323 * consecutive writes to registers that are within two SD-card 324 * clock cycles of each other (a clock domain crossing problem). 325 */ 326 if (sc->sc_slot.clock > 0) 327 DELAY(((2 * 1000000) / sc->sc_slot.clock) + 1); 328} 329 330static uint8_t 331bcm_sdhci_read_1(device_t dev, struct sdhci_slot *slot, bus_size_t off) 332{ 333 struct bcm_sdhci_softc *sc = device_get_softc(dev); 334 uint32_t val = RD4(sc, off & ~3); 335 336 return ((val >> (off & 3)*8) & 0xff); 337} 338 339static uint16_t 340bcm_sdhci_read_2(device_t dev, struct sdhci_slot *slot, bus_size_t off) 341{ 342 struct bcm_sdhci_softc *sc = device_get_softc(dev); 343 uint32_t val = RD4(sc, off & ~3); 344 345 /* 346 * Standard 32-bit handling of command and transfer mode. 347 */ 348 if (off == SDHCI_TRANSFER_MODE) { 349 return (sc->cmd_and_mode >> 16); 350 } else if (off == SDHCI_COMMAND_FLAGS) { 351 return (sc->cmd_and_mode & 0x0000ffff); 352 } 353 return ((val >> (off & 3)*8) & 0xffff); 354} 355 356static uint32_t 357bcm_sdhci_read_4(device_t dev, struct sdhci_slot *slot, bus_size_t off) 358{ 359 struct bcm_sdhci_softc *sc = device_get_softc(dev); 360 361 return RD4(sc, off); 362} 363 364static void 365bcm_sdhci_read_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, 366 uint32_t *data, bus_size_t count) 367{ 368 struct bcm_sdhci_softc *sc = device_get_softc(dev); 369 370 bus_space_read_multi_4(sc->sc_bst, sc->sc_bsh, off, data, count); 371} 372 373static void 374bcm_sdhci_write_1(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint8_t val) 375{ 376 struct bcm_sdhci_softc *sc = device_get_softc(dev); 377 uint32_t val32 = RD4(sc, off & ~3); 378 val32 &= ~(0xff << (off & 3)*8); 379 val32 |= (val << (off & 3)*8); 380 WR4(sc, off & ~3, val32); 381} 382 383static void 384bcm_sdhci_write_2(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint16_t val) 385{ 386 struct bcm_sdhci_softc *sc = device_get_softc(dev); 387 uint32_t val32; 388 if (off == SDHCI_COMMAND_FLAGS) 389 val32 = sc->cmd_and_mode; 390 else 391 val32 = RD4(sc, off & ~3); 392 val32 &= ~(0xffff << (off & 3)*8); 393 val32 |= (val << (off & 3)*8); 394 if (off == SDHCI_TRANSFER_MODE) 395 sc->cmd_and_mode = val32; 396 else 397 WR4(sc, off & ~3, val32); 398} 399 400static void 401bcm_sdhci_write_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint32_t val) 402{ 403 struct bcm_sdhci_softc *sc = device_get_softc(dev); 404 WR4(sc, off, val); 405} 406 407static void 408bcm_sdhci_write_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, 409 uint32_t *data, bus_size_t count) 410{ 411 struct bcm_sdhci_softc *sc = device_get_softc(dev); 412 413 bus_space_write_multi_4(sc->sc_bst, sc->sc_bsh, off, data, count); 414} 415 416static uint32_t 417bcm_sdhci_min_freq(device_t dev, struct sdhci_slot *slot) 418{ 419 420 return bcm2835_sdhci_min_freq; 421} 422 423static void 424bcm_sdhci_dma_intr(int ch, void *arg) 425{ 426 struct bcm_sdhci_softc *sc = (struct bcm_sdhci_softc *)arg; 427 struct sdhci_slot *slot = &sc->sc_slot; 428 uint32_t reg, mask; 429 bus_addr_t pmem; 430 vm_paddr_t pdst, psrc; 431 size_t len; 432 int left, sync_op; 433 434 mtx_lock(&slot->mtx); 435 436 len = bcm_dma_length(sc->sc_dma_ch); 437 if (slot->curcmd->data->flags & MMC_DATA_READ) { 438 sync_op = BUS_DMASYNC_POSTREAD; 439 mask = SDHCI_INT_DATA_AVAIL; 440 } else { 441 sync_op = BUS_DMASYNC_POSTWRITE; 442 mask = SDHCI_INT_SPACE_AVAIL; 443 } 444 bus_dmamap_sync(sc->sc_dma_tag, sc->sc_dma_map, sync_op); 445 bus_dmamap_unload(sc->sc_dma_tag, sc->sc_dma_map); 446 447 slot->offset += len; 448 sc->sc_dma_inuse = 0; 449 450 left = min(BCM_SDHCI_BUFFER_SIZE, 451 slot->curcmd->data->len - slot->offset); 452 453 /* DATA END? */ 454 reg = bcm_sdhci_read_4(slot->bus, slot, SDHCI_INT_STATUS); 455 456 if (reg & SDHCI_INT_DATA_END) { 457 /* ACK for all outstanding interrupts */ 458 bcm_sdhci_write_4(slot->bus, slot, SDHCI_INT_STATUS, reg); 459 460 /* enable INT */ 461 slot->intmask |= SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL 462 | SDHCI_INT_DATA_END; 463 bcm_sdhci_write_4(slot->bus, slot, SDHCI_SIGNAL_ENABLE, 464 slot->intmask); 465 466 /* finish this data */ 467 sdhci_finish_data(slot); 468 } 469 else { 470 /* already available? */ 471 if (reg & mask) { 472 sc->sc_dma_inuse = 1; 473 474 /* ACK for DATA_AVAIL or SPACE_AVAIL */ 475 bcm_sdhci_write_4(slot->bus, slot, 476 SDHCI_INT_STATUS, mask); 477 478 /* continue next DMA transfer */ 479 bus_dmamap_load(sc->sc_dma_tag, sc->sc_dma_map, 480 (uint8_t *)slot->curcmd->data->data + 481 slot->offset, left, bcm_dmamap_cb, &pmem, 0); 482 if (slot->curcmd->data->flags & MMC_DATA_READ) { 483 psrc = sc->sc_sdhci_buffer_phys; 484 pdst = pmem; 485 sync_op = BUS_DMASYNC_PREREAD; 486 } else { 487 psrc = pmem; 488 pdst = sc->sc_sdhci_buffer_phys; 489 sync_op = BUS_DMASYNC_PREWRITE; 490 } 491 bus_dmamap_sync(sc->sc_dma_tag, sc->sc_dma_map, sync_op); 492 if (bcm_dma_start(sc->sc_dma_ch, psrc, pdst, left)) { 493 /* XXX stop xfer, other error recovery? */ 494 device_printf(sc->sc_dev, "failed DMA start\n"); 495 } 496 } else { 497 /* wait for next data by INT */ 498 499 /* enable INT */ 500 slot->intmask |= SDHCI_INT_DATA_AVAIL | 501 SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_END; 502 bcm_sdhci_write_4(slot->bus, slot, SDHCI_SIGNAL_ENABLE, 503 slot->intmask); 504 } 505 } 506 507 mtx_unlock(&slot->mtx); 508} 509 510static void 511bcm_sdhci_read_dma(struct sdhci_slot *slot) 512{ 513 struct bcm_sdhci_softc *sc = device_get_softc(slot->bus); 514 size_t left; 515 bus_addr_t paddr; 516 517 if (sc->sc_dma_inuse) { 518 device_printf(sc->sc_dev, "DMA in use\n"); 519 return; 520 } 521 522 sc->sc_dma_inuse = 1; 523 524 left = min(BCM_SDHCI_BUFFER_SIZE, 525 slot->curcmd->data->len - slot->offset); 526 527 KASSERT((left & 3) == 0, 528 ("%s: len = %d, not word-aligned", __func__, left)); 529 530 bcm_dma_setup_src(sc->sc_dma_ch, BCM_DMA_DREQ_EMMC, 531 BCM_DMA_SAME_ADDR, BCM_DMA_32BIT); 532 bcm_dma_setup_dst(sc->sc_dma_ch, BCM_DMA_DREQ_NONE, 533 BCM_DMA_INC_ADDR, 534 (left & 0xf) ? BCM_DMA_32BIT : BCM_DMA_128BIT); 535 536 bus_dmamap_load(sc->sc_dma_tag, sc->sc_dma_map, 537 (uint8_t *)slot->curcmd->data->data + slot->offset, left, 538 bcm_dmamap_cb, &paddr, 0); 539 540 bus_dmamap_sync(sc->sc_dma_tag, sc->sc_dma_map, 541 BUS_DMASYNC_PREREAD); 542 543 /* DMA start */ 544 if (bcm_dma_start(sc->sc_dma_ch, sc->sc_sdhci_buffer_phys, 545 paddr, left) != 0) 546 device_printf(sc->sc_dev, "failed DMA start\n"); 547} 548 549static void 550bcm_sdhci_write_dma(struct sdhci_slot *slot) 551{ 552 struct bcm_sdhci_softc *sc = device_get_softc(slot->bus); 553 size_t left; 554 bus_addr_t paddr; 555 556 if (sc->sc_dma_inuse) { 557 device_printf(sc->sc_dev, "DMA in use\n"); 558 return; 559 } 560 561 sc->sc_dma_inuse = 1; 562 563 left = min(BCM_SDHCI_BUFFER_SIZE, 564 slot->curcmd->data->len - slot->offset); 565 566 KASSERT((left & 3) == 0, 567 ("%s: len = %d, not word-aligned", __func__, left)); 568 569 bus_dmamap_load(sc->sc_dma_tag, sc->sc_dma_map, 570 (uint8_t *)slot->curcmd->data->data + slot->offset, left, 571 bcm_dmamap_cb, &paddr, 0); 572 573 bcm_dma_setup_src(sc->sc_dma_ch, BCM_DMA_DREQ_NONE, 574 BCM_DMA_INC_ADDR, 575 (left & 0xf) ? BCM_DMA_32BIT : BCM_DMA_128BIT); 576 bcm_dma_setup_dst(sc->sc_dma_ch, BCM_DMA_DREQ_EMMC, 577 BCM_DMA_SAME_ADDR, BCM_DMA_32BIT); 578 579 bus_dmamap_sync(sc->sc_dma_tag, sc->sc_dma_map, 580 BUS_DMASYNC_PREWRITE); 581 582 /* DMA start */ 583 if (bcm_dma_start(sc->sc_dma_ch, paddr, 584 sc->sc_sdhci_buffer_phys, left) != 0) 585 device_printf(sc->sc_dev, "failed DMA start\n"); 586} 587 588static int 589bcm_sdhci_will_handle_transfer(device_t dev, struct sdhci_slot *slot) 590{ 591 size_t left; 592 593 /* 594 * Do not use DMA for transfers less than block size or with a length 595 * that is not a multiple of four. 596 */ 597 left = min(BCM_DMA_BLOCK_SIZE, 598 slot->curcmd->data->len - slot->offset); 599 if (left < BCM_DMA_BLOCK_SIZE) 600 return (0); 601 if (left & 0x03) 602 return (0); 603 604 return (1); 605} 606 607static void 608bcm_sdhci_start_transfer(device_t dev, struct sdhci_slot *slot, 609 uint32_t *intmask) 610{ 611 612 /* Disable INT */ 613 slot->intmask &= ~(SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_END); 614 bcm_sdhci_write_4(dev, slot, SDHCI_SIGNAL_ENABLE, slot->intmask); 615 616 /* DMA transfer FIFO 1KB */ 617 if (slot->curcmd->data->flags & MMC_DATA_READ) 618 bcm_sdhci_read_dma(slot); 619 else 620 bcm_sdhci_write_dma(slot); 621} 622 623static void 624bcm_sdhci_finish_transfer(device_t dev, struct sdhci_slot *slot) 625{ 626 627 sdhci_finish_data(slot); 628} 629 630static device_method_t bcm_sdhci_methods[] = { 631 /* Device interface */ 632 DEVMETHOD(device_probe, bcm_sdhci_probe), 633 DEVMETHOD(device_attach, bcm_sdhci_attach), 634 DEVMETHOD(device_detach, bcm_sdhci_detach), 635 636 /* Bus interface */ 637 DEVMETHOD(bus_read_ivar, sdhci_generic_read_ivar), 638 DEVMETHOD(bus_write_ivar, sdhci_generic_write_ivar), 639 DEVMETHOD(bus_print_child, bus_generic_print_child), 640 641 /* MMC bridge interface */ 642 DEVMETHOD(mmcbr_update_ios, sdhci_generic_update_ios), 643 DEVMETHOD(mmcbr_request, sdhci_generic_request), 644 DEVMETHOD(mmcbr_get_ro, bcm_sdhci_get_ro), 645 DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host), 646 DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host), 647 648 DEVMETHOD(sdhci_min_freq, bcm_sdhci_min_freq), 649 /* Platform transfer methods */ 650 DEVMETHOD(sdhci_platform_will_handle, bcm_sdhci_will_handle_transfer), 651 DEVMETHOD(sdhci_platform_start_transfer, bcm_sdhci_start_transfer), 652 DEVMETHOD(sdhci_platform_finish_transfer, bcm_sdhci_finish_transfer), 653 /* SDHCI registers accessors */ 654 DEVMETHOD(sdhci_read_1, bcm_sdhci_read_1), 655 DEVMETHOD(sdhci_read_2, bcm_sdhci_read_2), 656 DEVMETHOD(sdhci_read_4, bcm_sdhci_read_4), 657 DEVMETHOD(sdhci_read_multi_4, bcm_sdhci_read_multi_4), 658 DEVMETHOD(sdhci_write_1, bcm_sdhci_write_1), 659 DEVMETHOD(sdhci_write_2, bcm_sdhci_write_2), 660 DEVMETHOD(sdhci_write_4, bcm_sdhci_write_4), 661 DEVMETHOD(sdhci_write_multi_4, bcm_sdhci_write_multi_4), 662 663 { 0, 0 } 664}; 665 666static devclass_t bcm_sdhci_devclass; 667 668static driver_t bcm_sdhci_driver = { 669 "sdhci_bcm", 670 bcm_sdhci_methods, 671 sizeof(struct bcm_sdhci_softc), 672}; 673 674DRIVER_MODULE(sdhci_bcm, simplebus, bcm_sdhci_driver, bcm_sdhci_devclass, 0, 0); 675MODULE_DEPEND(sdhci_bcm, sdhci, 1, 1, 1); 676