bcm2835_sdhci.c revision 273264
1/*- 2 * Copyright (c) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 */ 27#include <sys/cdefs.h> 28__FBSDID("$FreeBSD: head/sys/arm/broadcom/bcm2835/bcm2835_sdhci.c 273264 2014-10-18 19:01:07Z loos $"); 29 30#include <sys/param.h> 31#include <sys/systm.h> 32#include <sys/bio.h> 33#include <sys/bus.h> 34#include <sys/conf.h> 35#include <sys/endian.h> 36#include <sys/kernel.h> 37#include <sys/kthread.h> 38#include <sys/lock.h> 39#include <sys/malloc.h> 40#include <sys/module.h> 41#include <sys/mutex.h> 42#include <sys/queue.h> 43#include <sys/resource.h> 44#include <sys/rman.h> 45#include <sys/sysctl.h> 46#include <sys/taskqueue.h> 47#include <sys/time.h> 48#include <sys/timetc.h> 49#include <sys/watchdog.h> 50 51#include <sys/kdb.h> 52 53#include <machine/bus.h> 54#include <machine/cpu.h> 55#include <machine/cpufunc.h> 56#include <machine/resource.h> 57#include <machine/intr.h> 58 59#include <dev/fdt/fdt_common.h> 60#include <dev/ofw/ofw_bus.h> 61#include <dev/ofw/ofw_bus_subr.h> 62 63#include <dev/mmc/bridge.h> 64#include <dev/mmc/mmcreg.h> 65#include <dev/mmc/mmcbrvar.h> 66 67#include <dev/sdhci/sdhci.h> 68#include "sdhci_if.h" 69 70#include "bcm2835_dma.h" 71#include "bcm2835_vcbus.h" 72 73#define BCM2835_DEFAULT_SDHCI_FREQ 50 74 75#define BCM_SDHCI_BUFFER_SIZE 512 76 77#ifdef DEBUG 78#define dprintf(fmt, args...) do { printf("%s(): ", __func__); \ 79 printf(fmt,##args); } while (0) 80#else 81#define dprintf(fmt, args...) 82#endif 83 84/* 85 * Arasan HC seems to have problem with Data CRC on lower frequencies. 86 * Use this tunable to cap initialization sequence frequency at higher 87 * value. Default is standard 400kHz 88 */ 89static int bcm2835_sdhci_min_freq = 400000; 90static int bcm2835_sdhci_hs = 1; 91static int bcm2835_sdhci_pio_mode = 0; 92 93TUNABLE_INT("hw.bcm2835.sdhci.min_freq", &bcm2835_sdhci_min_freq); 94TUNABLE_INT("hw.bcm2835.sdhci.hs", &bcm2835_sdhci_hs); 95TUNABLE_INT("hw.bcm2835.sdhci.pio_mode", &bcm2835_sdhci_pio_mode); 96 97struct bcm_sdhci_dmamap_arg { 98 bus_addr_t sc_dma_busaddr; 99}; 100 101struct bcm_sdhci_softc { 102 device_t sc_dev; 103 struct mtx sc_mtx; 104 struct resource * sc_mem_res; 105 struct resource * sc_irq_res; 106 bus_space_tag_t sc_bst; 107 bus_space_handle_t sc_bsh; 108 void * sc_intrhand; 109 struct mmc_request * sc_req; 110 struct mmc_data * sc_data; 111 uint32_t sc_flags; 112#define LPC_SD_FLAGS_IGNORECRC (1 << 0) 113 int sc_xfer_direction; 114#define DIRECTION_READ 0 115#define DIRECTION_WRITE 1 116 int sc_xfer_done; 117 int sc_bus_busy; 118 struct sdhci_slot sc_slot; 119 int sc_dma_inuse; 120 int sc_dma_ch; 121 bus_dma_tag_t sc_dma_tag; 122 bus_dmamap_t sc_dma_map; 123 vm_paddr_t sc_sdhci_buffer_phys; 124}; 125 126static int bcm_sdhci_probe(device_t); 127static int bcm_sdhci_attach(device_t); 128static int bcm_sdhci_detach(device_t); 129static void bcm_sdhci_intr(void *); 130 131static int bcm_sdhci_get_ro(device_t, device_t); 132static void bcm_sdhci_dma_intr(int ch, void *arg); 133 134#define bcm_sdhci_lock(_sc) \ 135 mtx_lock(&_sc->sc_mtx); 136#define bcm_sdhci_unlock(_sc) \ 137 mtx_unlock(&_sc->sc_mtx); 138 139static void 140bcm_dmamap_cb(void *arg, bus_dma_segment_t *segs, 141 int nseg, int err) 142{ 143 bus_addr_t *addr; 144 145 if (err) 146 return; 147 148 addr = (bus_addr_t*)arg; 149 *addr = segs[0].ds_addr; 150} 151 152static int 153bcm_sdhci_probe(device_t dev) 154{ 155 156 if (!ofw_bus_status_okay(dev)) 157 return (ENXIO); 158 159 if (!ofw_bus_is_compatible(dev, "broadcom,bcm2835-sdhci")) 160 return (ENXIO); 161 162 device_set_desc(dev, "Broadcom 2708 SDHCI controller"); 163 return (BUS_PROBE_DEFAULT); 164} 165 166static int 167bcm_sdhci_attach(device_t dev) 168{ 169 struct bcm_sdhci_softc *sc = device_get_softc(dev); 170 int rid, err; 171 phandle_t node; 172 pcell_t cell; 173 int default_freq; 174 175 sc->sc_dev = dev; 176 sc->sc_req = NULL; 177 err = 0; 178 179 default_freq = BCM2835_DEFAULT_SDHCI_FREQ; 180 node = ofw_bus_get_node(sc->sc_dev); 181 if ((OF_getprop(node, "clock-frequency", &cell, sizeof(cell))) > 0) 182 default_freq = (int)fdt32_to_cpu(cell)/1000000; 183 184 dprintf("SDHCI frequency: %dMHz\n", default_freq); 185 186 mtx_init(&sc->sc_mtx, "bcm sdhci", "sdhci", MTX_DEF); 187 188 rid = 0; 189 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 190 RF_ACTIVE); 191 if (!sc->sc_mem_res) { 192 device_printf(dev, "cannot allocate memory window\n"); 193 err = ENXIO; 194 goto fail; 195 } 196 197 sc->sc_bst = rman_get_bustag(sc->sc_mem_res); 198 sc->sc_bsh = rman_get_bushandle(sc->sc_mem_res); 199 200 rid = 0; 201 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 202 RF_ACTIVE); 203 if (!sc->sc_irq_res) { 204 device_printf(dev, "cannot allocate interrupt\n"); 205 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); 206 err = ENXIO; 207 goto fail; 208 } 209 210 if (bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_BIO | INTR_MPSAFE, 211 NULL, bcm_sdhci_intr, sc, &sc->sc_intrhand)) 212 { 213 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); 214 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res); 215 device_printf(dev, "cannot setup interrupt handler\n"); 216 err = ENXIO; 217 goto fail; 218 } 219 220 if (!bcm2835_sdhci_pio_mode) 221 sc->sc_slot.opt = SDHCI_PLATFORM_TRANSFER; 222 223 sc->sc_slot.caps = SDHCI_CAN_VDD_330 | SDHCI_CAN_VDD_180; 224 if (bcm2835_sdhci_hs) 225 sc->sc_slot.caps |= SDHCI_CAN_DO_HISPD; 226 sc->sc_slot.caps |= (default_freq << SDHCI_CLOCK_BASE_SHIFT); 227 sc->sc_slot.quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK 228 | SDHCI_QUIRK_BROKEN_TIMEOUT_VAL 229 | SDHCI_QUIRK_MISSING_CAPS; 230 231 sdhci_init_slot(dev, &sc->sc_slot, 0); 232 233 sc->sc_dma_ch = bcm_dma_allocate(BCM_DMA_CH_FAST1); 234 if (sc->sc_dma_ch == BCM_DMA_CH_INVALID) 235 sc->sc_dma_ch = bcm_dma_allocate(BCM_DMA_CH_FAST2); 236 if (sc->sc_dma_ch == BCM_DMA_CH_INVALID) 237 sc->sc_dma_ch = bcm_dma_allocate(BCM_DMA_CH_ANY); 238 if (sc->sc_dma_ch == BCM_DMA_CH_INVALID) 239 goto fail; 240 241 bcm_dma_setup_intr(sc->sc_dma_ch, bcm_sdhci_dma_intr, sc); 242 243 /* Allocate bus_dma resources. */ 244 err = bus_dma_tag_create(bus_get_dma_tag(dev), 245 1, 0, BUS_SPACE_MAXADDR_32BIT, 246 BUS_SPACE_MAXADDR, NULL, NULL, 247 BCM_SDHCI_BUFFER_SIZE, 1, BCM_SDHCI_BUFFER_SIZE, 248 BUS_DMA_ALLOCNOW, NULL, NULL, 249 &sc->sc_dma_tag); 250 251 if (err) { 252 device_printf(dev, "failed allocate DMA tag"); 253 goto fail; 254 } 255 256 err = bus_dmamap_create(sc->sc_dma_tag, 0, &sc->sc_dma_map); 257 if (err) { 258 device_printf(dev, "bus_dmamap_create failed\n"); 259 goto fail; 260 } 261 262 sc->sc_sdhci_buffer_phys = BUS_SPACE_PHYSADDR(sc->sc_mem_res, 263 SDHCI_BUFFER); 264 265 bus_generic_probe(dev); 266 bus_generic_attach(dev); 267 268 sdhci_start_slot(&sc->sc_slot); 269 270 return (0); 271 272fail: 273 if (sc->sc_intrhand) 274 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_intrhand); 275 if (sc->sc_irq_res) 276 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res); 277 if (sc->sc_mem_res) 278 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); 279 280 return (err); 281} 282 283static int 284bcm_sdhci_detach(device_t dev) 285{ 286 287 return (EBUSY); 288} 289 290static void 291bcm_sdhci_intr(void *arg) 292{ 293 struct bcm_sdhci_softc *sc = arg; 294 295 sdhci_generic_intr(&sc->sc_slot); 296} 297 298static int 299bcm_sdhci_get_ro(device_t bus, device_t child) 300{ 301 302 return (0); 303} 304 305static inline uint32_t 306RD4(struct bcm_sdhci_softc *sc, bus_size_t off) 307{ 308 uint32_t val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, off); 309 return val; 310} 311 312static inline void 313WR4(struct bcm_sdhci_softc *sc, bus_size_t off, uint32_t val) 314{ 315 316 bus_space_write_4(sc->sc_bst, sc->sc_bsh, off, val); 317 /* 318 * The Arasan HC has a bug where it may lose the content of 319 * consecutive writes to registers that are within two SD-card 320 * clock cycles of each other (a clock domain crossing problem). 321 */ 322 if (sc->sc_slot.clock > 0) 323 DELAY(((2 * 1000000) / sc->sc_slot.clock) + 1); 324} 325 326static uint8_t 327bcm_sdhci_read_1(device_t dev, struct sdhci_slot *slot, bus_size_t off) 328{ 329 struct bcm_sdhci_softc *sc = device_get_softc(dev); 330 uint32_t val = RD4(sc, off & ~3); 331 332 return ((val >> (off & 3)*8) & 0xff); 333} 334 335static uint16_t 336bcm_sdhci_read_2(device_t dev, struct sdhci_slot *slot, bus_size_t off) 337{ 338 struct bcm_sdhci_softc *sc = device_get_softc(dev); 339 uint32_t val = RD4(sc, off & ~3); 340 341 return ((val >> (off & 3)*8) & 0xffff); 342} 343 344static uint32_t 345bcm_sdhci_read_4(device_t dev, struct sdhci_slot *slot, bus_size_t off) 346{ 347 struct bcm_sdhci_softc *sc = device_get_softc(dev); 348 349 return RD4(sc, off); 350} 351 352static void 353bcm_sdhci_read_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, 354 uint32_t *data, bus_size_t count) 355{ 356 struct bcm_sdhci_softc *sc = device_get_softc(dev); 357 358 bus_space_read_multi_4(sc->sc_bst, sc->sc_bsh, off, data, count); 359} 360 361static void 362bcm_sdhci_write_1(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint8_t val) 363{ 364 struct bcm_sdhci_softc *sc = device_get_softc(dev); 365 uint32_t val32 = RD4(sc, off & ~3); 366 val32 &= ~(0xff << (off & 3)*8); 367 val32 |= (val << (off & 3)*8); 368 WR4(sc, off & ~3, val32); 369} 370 371static void 372bcm_sdhci_write_2(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint16_t val) 373{ 374 struct bcm_sdhci_softc *sc = device_get_softc(dev); 375 static uint32_t cmd_and_trandfer_mode; 376 uint32_t val32; 377 if (off == SDHCI_COMMAND_FLAGS) 378 val32 = cmd_and_trandfer_mode; 379 else 380 val32 = RD4(sc, off & ~3); 381 val32 &= ~(0xffff << (off & 3)*8); 382 val32 |= (val << (off & 3)*8); 383 if (off == SDHCI_TRANSFER_MODE) 384 cmd_and_trandfer_mode = val32; 385 else 386 WR4(sc, off & ~3, val32); 387} 388 389static void 390bcm_sdhci_write_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint32_t val) 391{ 392 struct bcm_sdhci_softc *sc = device_get_softc(dev); 393 WR4(sc, off, val); 394} 395 396static void 397bcm_sdhci_write_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, 398 uint32_t *data, bus_size_t count) 399{ 400 struct bcm_sdhci_softc *sc = device_get_softc(dev); 401 402 bus_space_write_multi_4(sc->sc_bst, sc->sc_bsh, off, data, count); 403} 404 405static uint32_t 406bcm_sdhci_min_freq(device_t dev, struct sdhci_slot *slot) 407{ 408 409 return bcm2835_sdhci_min_freq; 410} 411 412static void 413bcm_sdhci_dma_intr(int ch, void *arg) 414{ 415 struct bcm_sdhci_softc *sc = (struct bcm_sdhci_softc *)arg; 416 struct sdhci_slot *slot = &sc->sc_slot; 417 uint32_t reg, mask; 418 bus_addr_t pmem; 419 vm_paddr_t pdst, psrc; 420 size_t len; 421 int left, sync_op; 422 423 mtx_lock(&slot->mtx); 424 425 len = bcm_dma_length(sc->sc_dma_ch); 426 if (slot->curcmd->data->flags & MMC_DATA_READ) { 427 sync_op = BUS_DMASYNC_POSTREAD; 428 mask = SDHCI_INT_DATA_AVAIL; 429 } else { 430 sync_op = BUS_DMASYNC_POSTWRITE; 431 mask = SDHCI_INT_SPACE_AVAIL; 432 } 433 bus_dmamap_sync(sc->sc_dma_tag, sc->sc_dma_map, sync_op); 434 bus_dmamap_unload(sc->sc_dma_tag, sc->sc_dma_map); 435 436 slot->offset += len; 437 sc->sc_dma_inuse = 0; 438 439 left = min(BCM_SDHCI_BUFFER_SIZE, 440 slot->curcmd->data->len - slot->offset); 441 442 /* DATA END? */ 443 reg = bcm_sdhci_read_4(slot->bus, slot, SDHCI_INT_STATUS); 444 445 if (reg & SDHCI_INT_DATA_END) { 446 /* ACK for all outstanding interrupts */ 447 bcm_sdhci_write_4(slot->bus, slot, SDHCI_INT_STATUS, reg); 448 449 /* enable INT */ 450 slot->intmask |= SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL 451 | SDHCI_INT_DATA_END; 452 bcm_sdhci_write_4(slot->bus, slot, SDHCI_SIGNAL_ENABLE, 453 slot->intmask); 454 455 /* finish this data */ 456 sdhci_finish_data(slot); 457 } 458 else { 459 /* already available? */ 460 if (reg & mask) { 461 sc->sc_dma_inuse = 1; 462 463 /* ACK for DATA_AVAIL or SPACE_AVAIL */ 464 bcm_sdhci_write_4(slot->bus, slot, 465 SDHCI_INT_STATUS, mask); 466 467 /* continue next DMA transfer */ 468 bus_dmamap_load(sc->sc_dma_tag, sc->sc_dma_map, 469 (uint8_t *)slot->curcmd->data->data + 470 slot->offset, left, bcm_dmamap_cb, &pmem, 0); 471 if (slot->curcmd->data->flags & MMC_DATA_READ) { 472 psrc = sc->sc_sdhci_buffer_phys; 473 pdst = pmem; 474 sync_op = BUS_DMASYNC_PREREAD; 475 } else { 476 psrc = pmem; 477 pdst = sc->sc_sdhci_buffer_phys; 478 sync_op = BUS_DMASYNC_PREWRITE; 479 } 480 bus_dmamap_sync(sc->sc_dma_tag, sc->sc_dma_map, sync_op); 481 if (bcm_dma_start(sc->sc_dma_ch, psrc, pdst, left)) { 482 /* XXX stop xfer, other error recovery? */ 483 device_printf(sc->sc_dev, "failed DMA start\n"); 484 } 485 } else { 486 /* wait for next data by INT */ 487 488 /* enable INT */ 489 slot->intmask |= SDHCI_INT_DATA_AVAIL | 490 SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_END; 491 bcm_sdhci_write_4(slot->bus, slot, SDHCI_SIGNAL_ENABLE, 492 slot->intmask); 493 } 494 } 495 496 mtx_unlock(&slot->mtx); 497} 498 499static void 500bcm_sdhci_read_dma(struct sdhci_slot *slot) 501{ 502 struct bcm_sdhci_softc *sc = device_get_softc(slot->bus); 503 size_t left; 504 bus_addr_t paddr; 505 506 if (sc->sc_dma_inuse) { 507 device_printf(sc->sc_dev, "DMA in use\n"); 508 return; 509 } 510 511 sc->sc_dma_inuse = 1; 512 513 left = min(BCM_SDHCI_BUFFER_SIZE, 514 slot->curcmd->data->len - slot->offset); 515 516 KASSERT((left & 3) == 0, 517 ("%s: len = %d, not word-aligned", __func__, left)); 518 519 bcm_dma_setup_src(sc->sc_dma_ch, BCM_DMA_DREQ_EMMC, 520 BCM_DMA_SAME_ADDR, BCM_DMA_32BIT); 521 bcm_dma_setup_dst(sc->sc_dma_ch, BCM_DMA_DREQ_NONE, 522 BCM_DMA_INC_ADDR, 523 (left & 0xf) ? BCM_DMA_32BIT : BCM_DMA_128BIT); 524 525 bus_dmamap_load(sc->sc_dma_tag, sc->sc_dma_map, 526 (uint8_t *)slot->curcmd->data->data + slot->offset, left, 527 bcm_dmamap_cb, &paddr, 0); 528 529 bus_dmamap_sync(sc->sc_dma_tag, sc->sc_dma_map, 530 BUS_DMASYNC_PREREAD); 531 532 /* DMA start */ 533 if (bcm_dma_start(sc->sc_dma_ch, sc->sc_sdhci_buffer_phys, 534 paddr, left) != 0) 535 device_printf(sc->sc_dev, "failed DMA start\n"); 536} 537 538static void 539bcm_sdhci_write_dma(struct sdhci_slot *slot) 540{ 541 struct bcm_sdhci_softc *sc = device_get_softc(slot->bus); 542 size_t left; 543 bus_addr_t paddr; 544 545 if (sc->sc_dma_inuse) { 546 device_printf(sc->sc_dev, "DMA in use\n"); 547 return; 548 } 549 550 sc->sc_dma_inuse = 1; 551 552 left = min(BCM_SDHCI_BUFFER_SIZE, 553 slot->curcmd->data->len - slot->offset); 554 555 KASSERT((left & 3) == 0, 556 ("%s: len = %d, not word-aligned", __func__, left)); 557 558 bus_dmamap_load(sc->sc_dma_tag, sc->sc_dma_map, 559 (uint8_t *)slot->curcmd->data->data + slot->offset, left, 560 bcm_dmamap_cb, &paddr, 0); 561 562 bcm_dma_setup_src(sc->sc_dma_ch, BCM_DMA_DREQ_NONE, 563 BCM_DMA_INC_ADDR, 564 (left & 0xf) ? BCM_DMA_32BIT : BCM_DMA_128BIT); 565 bcm_dma_setup_dst(sc->sc_dma_ch, BCM_DMA_DREQ_EMMC, 566 BCM_DMA_SAME_ADDR, BCM_DMA_32BIT); 567 568 bus_dmamap_sync(sc->sc_dma_tag, sc->sc_dma_map, 569 BUS_DMASYNC_PREWRITE); 570 571 /* DMA start */ 572 if (bcm_dma_start(sc->sc_dma_ch, paddr, 573 sc->sc_sdhci_buffer_phys, left) != 0) 574 device_printf(sc->sc_dev, "failed DMA start\n"); 575} 576 577static int 578bcm_sdhci_will_handle_transfer(device_t dev, struct sdhci_slot *slot) 579{ 580 size_t left; 581 582 /* 583 * Do not use DMA for transfers less than block size or with a length 584 * that is not a multiple of four. 585 */ 586 left = min(BCM_DMA_BLOCK_SIZE, 587 slot->curcmd->data->len - slot->offset); 588 if (left < BCM_DMA_BLOCK_SIZE) 589 return (0); 590 if (left & 0x03) 591 return (0); 592 593 return (1); 594} 595 596static void 597bcm_sdhci_start_transfer(device_t dev, struct sdhci_slot *slot, 598 uint32_t *intmask) 599{ 600 601 /* Disable INT */ 602 slot->intmask &= ~(SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_END); 603 bcm_sdhci_write_4(dev, slot, SDHCI_SIGNAL_ENABLE, slot->intmask); 604 605 /* DMA transfer FIFO 1KB */ 606 if (slot->curcmd->data->flags & MMC_DATA_READ) 607 bcm_sdhci_read_dma(slot); 608 else 609 bcm_sdhci_write_dma(slot); 610} 611 612static void 613bcm_sdhci_finish_transfer(device_t dev, struct sdhci_slot *slot) 614{ 615 616 sdhci_finish_data(slot); 617} 618 619static device_method_t bcm_sdhci_methods[] = { 620 /* Device interface */ 621 DEVMETHOD(device_probe, bcm_sdhci_probe), 622 DEVMETHOD(device_attach, bcm_sdhci_attach), 623 DEVMETHOD(device_detach, bcm_sdhci_detach), 624 625 /* Bus interface */ 626 DEVMETHOD(bus_read_ivar, sdhci_generic_read_ivar), 627 DEVMETHOD(bus_write_ivar, sdhci_generic_write_ivar), 628 DEVMETHOD(bus_print_child, bus_generic_print_child), 629 630 /* MMC bridge interface */ 631 DEVMETHOD(mmcbr_update_ios, sdhci_generic_update_ios), 632 DEVMETHOD(mmcbr_request, sdhci_generic_request), 633 DEVMETHOD(mmcbr_get_ro, bcm_sdhci_get_ro), 634 DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host), 635 DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host), 636 637 DEVMETHOD(sdhci_min_freq, bcm_sdhci_min_freq), 638 /* Platform transfer methods */ 639 DEVMETHOD(sdhci_platform_will_handle, bcm_sdhci_will_handle_transfer), 640 DEVMETHOD(sdhci_platform_start_transfer, bcm_sdhci_start_transfer), 641 DEVMETHOD(sdhci_platform_finish_transfer, bcm_sdhci_finish_transfer), 642 /* SDHCI registers accessors */ 643 DEVMETHOD(sdhci_read_1, bcm_sdhci_read_1), 644 DEVMETHOD(sdhci_read_2, bcm_sdhci_read_2), 645 DEVMETHOD(sdhci_read_4, bcm_sdhci_read_4), 646 DEVMETHOD(sdhci_read_multi_4, bcm_sdhci_read_multi_4), 647 DEVMETHOD(sdhci_write_1, bcm_sdhci_write_1), 648 DEVMETHOD(sdhci_write_2, bcm_sdhci_write_2), 649 DEVMETHOD(sdhci_write_4, bcm_sdhci_write_4), 650 DEVMETHOD(sdhci_write_multi_4, bcm_sdhci_write_multi_4), 651 652 { 0, 0 } 653}; 654 655static devclass_t bcm_sdhci_devclass; 656 657static driver_t bcm_sdhci_driver = { 658 "sdhci_bcm", 659 bcm_sdhci_methods, 660 sizeof(struct bcm_sdhci_softc), 661}; 662 663DRIVER_MODULE(sdhci_bcm, simplebus, bcm_sdhci_driver, bcm_sdhci_devclass, 0, 0); 664MODULE_DEPEND(sdhci_bcm, sdhci, 1, 1, 1); 665