bcm2835_intr.c revision 299117
1/*- 2 * Copyright (c) 2012 Damjan Marion <dmarion@Freebsd.org> 3 * All rights reserved. 4 * 5 * Based on OMAP3 INTC code by Ben Gray 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 30#include <sys/cdefs.h> 31__FBSDID("$FreeBSD: head/sys/arm/broadcom/bcm2835/bcm2835_intr.c 299117 2016-05-05 13:31:19Z skra $"); 32 33#include "opt_platform.h" 34 35#include <sys/param.h> 36#include <sys/systm.h> 37#include <sys/bus.h> 38#include <sys/kernel.h> 39#include <sys/ktr.h> 40#include <sys/module.h> 41#include <sys/proc.h> 42#include <sys/rman.h> 43#include <machine/bus.h> 44#include <machine/intr.h> 45 46#include <dev/fdt/fdt_common.h> 47#include <dev/ofw/openfirm.h> 48#include <dev/ofw/ofw_bus.h> 49#include <dev/ofw/ofw_bus_subr.h> 50 51#ifdef SOC_BCM2836 52#include <arm/broadcom/bcm2835/bcm2836.h> 53#endif 54 55#ifdef INTRNG 56#include "pic_if.h" 57#endif 58 59#define INTC_PENDING_BASIC 0x00 60#define INTC_PENDING_BANK1 0x04 61#define INTC_PENDING_BANK2 0x08 62#define INTC_FIQ_CONTROL 0x0C 63#define INTC_ENABLE_BANK1 0x10 64#define INTC_ENABLE_BANK2 0x14 65#define INTC_ENABLE_BASIC 0x18 66#define INTC_DISABLE_BANK1 0x1C 67#define INTC_DISABLE_BANK2 0x20 68#define INTC_DISABLE_BASIC 0x24 69 70#define INTC_PENDING_BASIC_ARM 0x0000FF 71#define INTC_PENDING_BASIC_GPU1_PEND 0x000100 72#define INTC_PENDING_BASIC_GPU2_PEND 0x000200 73#define INTC_PENDING_BASIC_GPU1_7 0x000400 74#define INTC_PENDING_BASIC_GPU1_9 0x000800 75#define INTC_PENDING_BASIC_GPU1_10 0x001000 76#define INTC_PENDING_BASIC_GPU1_18 0x002000 77#define INTC_PENDING_BASIC_GPU1_19 0x004000 78#define INTC_PENDING_BASIC_GPU2_21 0x008000 79#define INTC_PENDING_BASIC_GPU2_22 0x010000 80#define INTC_PENDING_BASIC_GPU2_23 0x020000 81#define INTC_PENDING_BASIC_GPU2_24 0x040000 82#define INTC_PENDING_BASIC_GPU2_25 0x080000 83#define INTC_PENDING_BASIC_GPU2_30 0x100000 84#define INTC_PENDING_BASIC_MASK 0x1FFFFF 85 86#define INTC_PENDING_BASIC_GPU1_MASK (INTC_PENDING_BASIC_GPU1_7 | \ 87 INTC_PENDING_BASIC_GPU1_9 | \ 88 INTC_PENDING_BASIC_GPU1_10 | \ 89 INTC_PENDING_BASIC_GPU1_18 | \ 90 INTC_PENDING_BASIC_GPU1_19) 91 92#define INTC_PENDING_BASIC_GPU2_MASK (INTC_PENDING_BASIC_GPU2_21 | \ 93 INTC_PENDING_BASIC_GPU2_22 | \ 94 INTC_PENDING_BASIC_GPU2_23 | \ 95 INTC_PENDING_BASIC_GPU2_24 | \ 96 INTC_PENDING_BASIC_GPU2_25 | \ 97 INTC_PENDING_BASIC_GPU2_30) 98 99#define INTC_PENDING_BANK1_MASK (~((1 << 7) | (1 << 9) | (1 << 10) | \ 100 (1 << 18) | (1 << 19))) 101#define INTC_PENDING_BANK2_MASK (~((1 << 21) | (1 << 22) | (1 << 23) | \ 102 (1 << 24) | (1 << 25) | (1 << 30))) 103 104#define BANK1_START 8 105#define BANK1_END (BANK1_START + 32 - 1) 106#define BANK2_START (BANK1_START + 32) 107#define BANK2_END (BANK2_START + 32 - 1) 108#ifndef INTRNG 109#define BANK3_START (BANK2_START + 32) 110#define BANK3_END (BANK3_START + 32 - 1) 111#endif 112 113#define IS_IRQ_BASIC(n) (((n) >= 0) && ((n) < BANK1_START)) 114#define IS_IRQ_BANK1(n) (((n) >= BANK1_START) && ((n) <= BANK1_END)) 115#define IS_IRQ_BANK2(n) (((n) >= BANK2_START) && ((n) <= BANK2_END)) 116#ifndef INTRNG 117#define ID_IRQ_BCM2836(n) (((n) >= BANK3_START) && ((n) <= BANK3_END)) 118#endif 119#define IRQ_BANK1(n) ((n) - BANK1_START) 120#define IRQ_BANK2(n) ((n) - BANK2_START) 121 122#ifdef DEBUG 123#define dprintf(fmt, args...) printf(fmt, ##args) 124#else 125#define dprintf(fmt, args...) 126#endif 127 128#ifdef INTRNG 129#define BCM_INTC_NIRQS 72 /* 8 + 32 + 32 */ 130 131struct bcm_intc_irqsrc { 132 struct intr_irqsrc bii_isrc; 133 u_int bii_irq; 134 uint16_t bii_disable_reg; 135 uint16_t bii_enable_reg; 136 uint32_t bii_mask; 137}; 138#endif 139 140struct bcm_intc_softc { 141 device_t sc_dev; 142 struct resource * intc_res; 143 bus_space_tag_t intc_bst; 144 bus_space_handle_t intc_bsh; 145#ifdef INTRNG 146 struct resource * intc_irq_res; 147 void * intc_irq_hdl; 148 struct bcm_intc_irqsrc intc_isrcs[BCM_INTC_NIRQS]; 149#endif 150}; 151 152static struct bcm_intc_softc *bcm_intc_sc = NULL; 153 154#define intc_read_4(_sc, reg) \ 155 bus_space_read_4((_sc)->intc_bst, (_sc)->intc_bsh, (reg)) 156#define intc_write_4(_sc, reg, val) \ 157 bus_space_write_4((_sc)->intc_bst, (_sc)->intc_bsh, (reg), (val)) 158 159#ifdef INTRNG 160static inline void 161bcm_intc_isrc_mask(struct bcm_intc_softc *sc, struct bcm_intc_irqsrc *bii) 162{ 163 164 intc_write_4(sc, bii->bii_disable_reg, bii->bii_mask); 165} 166 167static inline void 168bcm_intc_isrc_unmask(struct bcm_intc_softc *sc, struct bcm_intc_irqsrc *bii) 169{ 170 171 intc_write_4(sc, bii->bii_enable_reg, bii->bii_mask); 172} 173 174static inline int 175bcm2835_intc_active_intr(struct bcm_intc_softc *sc) 176{ 177 uint32_t pending, pending_gpu; 178 179 pending = intc_read_4(sc, INTC_PENDING_BASIC) & INTC_PENDING_BASIC_MASK; 180 if (pending == 0) 181 return (-1); 182 if (pending & INTC_PENDING_BASIC_ARM) 183 return (ffs(pending) - 1); 184 if (pending & INTC_PENDING_BASIC_GPU1_MASK) { 185 if (pending & INTC_PENDING_BASIC_GPU1_7) 186 return (BANK1_START + 7); 187 if (pending & INTC_PENDING_BASIC_GPU1_9) 188 return (BANK1_START + 9); 189 if (pending & INTC_PENDING_BASIC_GPU1_10) 190 return (BANK1_START + 10); 191 if (pending & INTC_PENDING_BASIC_GPU1_18) 192 return (BANK1_START + 18); 193 if (pending & INTC_PENDING_BASIC_GPU1_19) 194 return (BANK1_START + 19); 195 } 196 if (pending & INTC_PENDING_BASIC_GPU2_MASK) { 197 if (pending & INTC_PENDING_BASIC_GPU2_21) 198 return (BANK2_START + 21); 199 if (pending & INTC_PENDING_BASIC_GPU2_22) 200 return (BANK2_START + 22); 201 if (pending & INTC_PENDING_BASIC_GPU2_23) 202 return (BANK2_START + 23); 203 if (pending & INTC_PENDING_BASIC_GPU2_24) 204 return (BANK2_START + 24); 205 if (pending & INTC_PENDING_BASIC_GPU2_25) 206 return (BANK2_START + 25); 207 if (pending & INTC_PENDING_BASIC_GPU2_30) 208 return (BANK2_START + 30); 209 } 210 if (pending & INTC_PENDING_BASIC_GPU1_PEND) { 211 pending_gpu = intc_read_4(sc, INTC_PENDING_BANK1); 212 pending_gpu &= INTC_PENDING_BANK1_MASK; 213 if (pending_gpu != 0) 214 return (BANK1_START + ffs(pending_gpu) - 1); 215 } 216 if (pending & INTC_PENDING_BASIC_GPU2_PEND) { 217 pending_gpu = intc_read_4(sc, INTC_PENDING_BANK2); 218 pending_gpu &= INTC_PENDING_BANK2_MASK; 219 if (pending_gpu != 0) 220 return (BANK2_START + ffs(pending_gpu) - 1); 221 } 222 return (-1); /* It shouldn't end here, but it's hardware. */ 223} 224 225static int 226bcm2835_intc_intr(void *arg) 227{ 228 int irq, num; 229 struct bcm_intc_softc *sc = arg; 230 231 for (num = 0; ; num++) { 232 irq = bcm2835_intc_active_intr(sc); 233 if (irq == -1) 234 break; 235 if (intr_isrc_dispatch(&sc->intc_isrcs[irq].bii_isrc, 236 curthread->td_intr_frame) != 0) { 237 bcm_intc_isrc_mask(sc, &sc->intc_isrcs[irq]); 238 device_printf(sc->sc_dev, "Stray irq %u disabled\n", 239 irq); 240 } 241 arm_irq_memory_barrier(0); /* XXX */ 242 } 243 if (num == 0) 244 device_printf(sc->sc_dev, "Spurious interrupt detected\n"); 245 246 return (FILTER_HANDLED); 247} 248 249static void 250bcm_intc_enable_intr(device_t dev, struct intr_irqsrc *isrc) 251{ 252 struct bcm_intc_irqsrc *bii = (struct bcm_intc_irqsrc *)isrc; 253 254 arm_irq_memory_barrier(bii->bii_irq); 255 bcm_intc_isrc_unmask(device_get_softc(dev), bii); 256} 257 258static void 259bcm_intc_disable_intr(device_t dev, struct intr_irqsrc *isrc) 260{ 261 262 bcm_intc_isrc_mask(device_get_softc(dev), 263 (struct bcm_intc_irqsrc *)isrc); 264} 265 266static int 267bcm_intc_map_intr(device_t dev, struct intr_map_data *data, 268 struct intr_irqsrc **isrcp) 269{ 270 u_int irq; 271 struct intr_map_data_fdt *daf; 272 struct bcm_intc_softc *sc; 273 274 if (data->type != INTR_MAP_DATA_FDT) 275 return (ENOTSUP); 276 277 daf = (struct intr_map_data_fdt *)data; 278 if (daf->ncells == 1) 279 irq = daf->cells[0]; 280 else if (daf->ncells == 2) 281 irq = daf->cells[0] * 32 + daf->cells[1]; 282 else 283 return (EINVAL); 284 285 if (irq >= BCM_INTC_NIRQS) 286 return (EINVAL); 287 288 sc = device_get_softc(dev); 289 *isrcp = &sc->intc_isrcs[irq].bii_isrc; 290 return (0); 291} 292 293static void 294bcm_intc_pre_ithread(device_t dev, struct intr_irqsrc *isrc) 295{ 296 297 bcm_intc_disable_intr(dev, isrc); 298} 299 300static void 301bcm_intc_post_ithread(device_t dev, struct intr_irqsrc *isrc) 302{ 303 304 bcm_intc_enable_intr(dev, isrc); 305} 306 307static void 308bcm_intc_post_filter(device_t dev, struct intr_irqsrc *isrc) 309{ 310} 311 312static int 313bcm_intc_pic_register(struct bcm_intc_softc *sc, intptr_t xref) 314{ 315 struct bcm_intc_irqsrc *bii; 316 int error; 317 uint32_t irq; 318 const char *name; 319 320 name = device_get_nameunit(sc->sc_dev); 321 for (irq = 0; irq < BCM_INTC_NIRQS; irq++) { 322 bii = &sc->intc_isrcs[irq]; 323 bii->bii_irq = irq; 324 if (IS_IRQ_BASIC(irq)) { 325 bii->bii_disable_reg = INTC_DISABLE_BASIC; 326 bii->bii_enable_reg = INTC_ENABLE_BASIC; 327 bii->bii_mask = 1 << irq; 328 } else if (IS_IRQ_BANK1(irq)) { 329 bii->bii_disable_reg = INTC_DISABLE_BANK1; 330 bii->bii_enable_reg = INTC_ENABLE_BANK1; 331 bii->bii_mask = 1 << IRQ_BANK1(irq); 332 } else if (IS_IRQ_BANK2(irq)) { 333 bii->bii_disable_reg = INTC_DISABLE_BANK2; 334 bii->bii_enable_reg = INTC_ENABLE_BANK2; 335 bii->bii_mask = 1 << IRQ_BANK2(irq); 336 } else 337 return (ENXIO); 338 339 error = intr_isrc_register(&bii->bii_isrc, sc->sc_dev, 0, 340 "%s,%u", name, irq); 341 if (error != 0) 342 return (error); 343 } 344 return (intr_pic_register(sc->sc_dev, xref)); 345} 346#endif 347 348static int 349bcm_intc_probe(device_t dev) 350{ 351 352 if (!ofw_bus_status_okay(dev)) 353 return (ENXIO); 354 355 if (!ofw_bus_is_compatible(dev, "broadcom,bcm2835-armctrl-ic")) 356 return (ENXIO); 357 device_set_desc(dev, "BCM2835 Interrupt Controller"); 358 return (BUS_PROBE_DEFAULT); 359} 360 361static int 362bcm_intc_attach(device_t dev) 363{ 364 struct bcm_intc_softc *sc = device_get_softc(dev); 365 int rid = 0; 366#ifdef INTRNG 367 intptr_t xref; 368#endif 369 sc->sc_dev = dev; 370 371 if (bcm_intc_sc) 372 return (ENXIO); 373 374 sc->intc_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); 375 if (sc->intc_res == NULL) { 376 device_printf(dev, "could not allocate memory resource\n"); 377 return (ENXIO); 378 } 379 380#ifdef INTRNG 381 xref = OF_xref_from_node(ofw_bus_get_node(dev)); 382 if (bcm_intc_pic_register(sc, xref) != 0) { 383 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->intc_res); 384 device_printf(dev, "could not register PIC\n"); 385 return (ENXIO); 386 } 387 388 rid = 0; 389 sc->intc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 390 RF_ACTIVE); 391 if (sc->intc_irq_res == NULL) { 392 if (intr_pic_claim_root(dev, xref, bcm2835_intc_intr, sc, 0) != 0) { 393 /* XXX clean up */ 394 device_printf(dev, "could not set PIC as a root\n"); 395 return (ENXIO); 396 } 397 } else { 398 if (bus_setup_intr(dev, sc->intc_irq_res, INTR_TYPE_CLK, 399 bcm2835_intc_intr, NULL, sc, &sc->intc_irq_hdl)) { 400 /* XXX clean up */ 401 device_printf(dev, "could not setup irq handler\n"); 402 return (ENXIO); 403 } 404 } 405#endif 406 sc->intc_bst = rman_get_bustag(sc->intc_res); 407 sc->intc_bsh = rman_get_bushandle(sc->intc_res); 408 409 bcm_intc_sc = sc; 410 411 return (0); 412} 413 414static device_method_t bcm_intc_methods[] = { 415 DEVMETHOD(device_probe, bcm_intc_probe), 416 DEVMETHOD(device_attach, bcm_intc_attach), 417 418#ifdef INTRNG 419 DEVMETHOD(pic_disable_intr, bcm_intc_disable_intr), 420 DEVMETHOD(pic_enable_intr, bcm_intc_enable_intr), 421 DEVMETHOD(pic_map_intr, bcm_intc_map_intr), 422 DEVMETHOD(pic_post_filter, bcm_intc_post_filter), 423 DEVMETHOD(pic_post_ithread, bcm_intc_post_ithread), 424 DEVMETHOD(pic_pre_ithread, bcm_intc_pre_ithread), 425#endif 426 427 { 0, 0 } 428}; 429 430static driver_t bcm_intc_driver = { 431 "intc", 432 bcm_intc_methods, 433 sizeof(struct bcm_intc_softc), 434}; 435 436static devclass_t bcm_intc_devclass; 437 438DRIVER_MODULE(intc, simplebus, bcm_intc_driver, bcm_intc_devclass, 0, 0); 439 440#ifndef INTRNG 441int 442arm_get_next_irq(int last_irq) 443{ 444 struct bcm_intc_softc *sc = bcm_intc_sc; 445 uint32_t pending; 446 int32_t irq = last_irq + 1; 447#ifdef SOC_BCM2836 448 int ret; 449#endif 450 451 /* Sanity check */ 452 if (irq < 0) 453 irq = 0; 454 455#ifdef SOC_BCM2836 456 if ((ret = bcm2836_get_next_irq(irq)) < 0) 457 return (-1); 458 if (ret != BCM2836_GPU_IRQ) 459 return (ret + BANK3_START); 460#endif 461 462 /* TODO: should we mask last_irq? */ 463 if (irq < BANK1_START) { 464 pending = intc_read_4(sc, INTC_PENDING_BASIC); 465 if ((pending & 0xFF) == 0) { 466 irq = BANK1_START; /* skip to next bank */ 467 } else do { 468 if (pending & (1 << irq)) 469 return irq; 470 irq++; 471 } while (irq < BANK1_START); 472 } 473 if (irq < BANK2_START) { 474 pending = intc_read_4(sc, INTC_PENDING_BANK1); 475 if (pending == 0) { 476 irq = BANK2_START; /* skip to next bank */ 477 } else do { 478 if (pending & (1 << IRQ_BANK1(irq))) 479 return irq; 480 irq++; 481 } while (irq < BANK2_START); 482 } 483 if (irq < BANK3_START) { 484 pending = intc_read_4(sc, INTC_PENDING_BANK2); 485 if (pending != 0) do { 486 if (pending & (1 << IRQ_BANK2(irq))) 487 return irq; 488 irq++; 489 } while (irq < BANK3_START); 490 } 491 return (-1); 492} 493 494void 495arm_mask_irq(uintptr_t nb) 496{ 497 struct bcm_intc_softc *sc = bcm_intc_sc; 498 dprintf("%s: %d\n", __func__, nb); 499 500 if (IS_IRQ_BASIC(nb)) 501 intc_write_4(sc, INTC_DISABLE_BASIC, (1 << nb)); 502 else if (IS_IRQ_BANK1(nb)) 503 intc_write_4(sc, INTC_DISABLE_BANK1, (1 << IRQ_BANK1(nb))); 504 else if (IS_IRQ_BANK2(nb)) 505 intc_write_4(sc, INTC_DISABLE_BANK2, (1 << IRQ_BANK2(nb))); 506#ifdef SOC_BCM2836 507 else if (ID_IRQ_BCM2836(nb)) 508 bcm2836_mask_irq(nb - BANK3_START); 509#endif 510 else 511 printf("arm_mask_irq: Invalid IRQ number: %d\n", nb); 512} 513 514void 515arm_unmask_irq(uintptr_t nb) 516{ 517 struct bcm_intc_softc *sc = bcm_intc_sc; 518 dprintf("%s: %d\n", __func__, nb); 519 520 if (IS_IRQ_BASIC(nb)) 521 intc_write_4(sc, INTC_ENABLE_BASIC, (1 << nb)); 522 else if (IS_IRQ_BANK1(nb)) 523 intc_write_4(sc, INTC_ENABLE_BANK1, (1 << IRQ_BANK1(nb))); 524 else if (IS_IRQ_BANK2(nb)) 525 intc_write_4(sc, INTC_ENABLE_BANK2, (1 << IRQ_BANK2(nb))); 526#ifdef SOC_BCM2836 527 else if (ID_IRQ_BCM2836(nb)) 528 bcm2836_unmask_irq(nb - BANK3_START); 529#endif 530 else 531 printf("arm_mask_irq: Invalid IRQ number: %d\n", nb); 532} 533 534#ifdef SMP 535void 536intr_pic_init_secondary(void) 537{ 538} 539#endif 540#endif 541