1239922Sgonzo/*- 2239922Sgonzo * Copyright (c) 2012 Damjan Marion <dmarion@Freebsd.org> 3239922Sgonzo * All rights reserved. 4239922Sgonzo * 5239922Sgonzo * Based on OMAP3 INTC code by Ben Gray 6239922Sgonzo * 7239922Sgonzo * Redistribution and use in source and binary forms, with or without 8239922Sgonzo * modification, are permitted provided that the following conditions 9239922Sgonzo * are met: 10239922Sgonzo * 1. Redistributions of source code must retain the above copyright 11239922Sgonzo * notice, this list of conditions and the following disclaimer. 12239922Sgonzo * 2. Redistributions in binary form must reproduce the above copyright 13239922Sgonzo * notice, this list of conditions and the following disclaimer in the 14239922Sgonzo * documentation and/or other materials provided with the distribution. 15239922Sgonzo * 16239922Sgonzo * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17239922Sgonzo * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18239922Sgonzo * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19239922Sgonzo * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20239922Sgonzo * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21239922Sgonzo * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22239922Sgonzo * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23239922Sgonzo * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24239922Sgonzo * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25239922Sgonzo * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26239922Sgonzo * SUCH DAMAGE. 27239922Sgonzo */ 28239922Sgonzo 29239922Sgonzo 30239922Sgonzo#include <sys/cdefs.h> 31239922Sgonzo__FBSDID("$FreeBSD: stable/11/sys/arm/broadcom/bcm2835/bcm2835_intr.c 307575 2016-10-18 19:15:43Z gonzo $"); 32239922Sgonzo 33297580Sskra#include "opt_platform.h" 34297580Sskra 35239922Sgonzo#include <sys/param.h> 36239922Sgonzo#include <sys/systm.h> 37239922Sgonzo#include <sys/bus.h> 38239922Sgonzo#include <sys/kernel.h> 39239922Sgonzo#include <sys/ktr.h> 40239922Sgonzo#include <sys/module.h> 41297580Sskra#include <sys/proc.h> 42239922Sgonzo#include <sys/rman.h> 43239922Sgonzo#include <machine/bus.h> 44239922Sgonzo#include <machine/intr.h> 45239922Sgonzo 46239922Sgonzo#include <dev/fdt/fdt_common.h> 47239922Sgonzo#include <dev/ofw/openfirm.h> 48239922Sgonzo#include <dev/ofw/ofw_bus.h> 49239922Sgonzo#include <dev/ofw/ofw_bus_subr.h> 50239922Sgonzo 51280558Sandrew#ifdef SOC_BCM2836 52280558Sandrew#include <arm/broadcom/bcm2835/bcm2836.h> 53280558Sandrew#endif 54280558Sandrew 55298068Sandrew#ifdef INTRNG 56297580Sskra#include "pic_if.h" 57297580Sskra#endif 58297580Sskra 59239922Sgonzo#define INTC_PENDING_BASIC 0x00 60239922Sgonzo#define INTC_PENDING_BANK1 0x04 61239922Sgonzo#define INTC_PENDING_BANK2 0x08 62239922Sgonzo#define INTC_FIQ_CONTROL 0x0C 63239922Sgonzo#define INTC_ENABLE_BANK1 0x10 64239922Sgonzo#define INTC_ENABLE_BANK2 0x14 65239922Sgonzo#define INTC_ENABLE_BASIC 0x18 66239922Sgonzo#define INTC_DISABLE_BANK1 0x1C 67239922Sgonzo#define INTC_DISABLE_BANK2 0x20 68239922Sgonzo#define INTC_DISABLE_BASIC 0x24 69239922Sgonzo 70297580Sskra#define INTC_PENDING_BASIC_ARM 0x0000FF 71297580Sskra#define INTC_PENDING_BASIC_GPU1_PEND 0x000100 72297580Sskra#define INTC_PENDING_BASIC_GPU2_PEND 0x000200 73297580Sskra#define INTC_PENDING_BASIC_GPU1_7 0x000400 74297580Sskra#define INTC_PENDING_BASIC_GPU1_9 0x000800 75297580Sskra#define INTC_PENDING_BASIC_GPU1_10 0x001000 76297580Sskra#define INTC_PENDING_BASIC_GPU1_18 0x002000 77297580Sskra#define INTC_PENDING_BASIC_GPU1_19 0x004000 78297580Sskra#define INTC_PENDING_BASIC_GPU2_21 0x008000 79297580Sskra#define INTC_PENDING_BASIC_GPU2_22 0x010000 80297580Sskra#define INTC_PENDING_BASIC_GPU2_23 0x020000 81297580Sskra#define INTC_PENDING_BASIC_GPU2_24 0x040000 82297580Sskra#define INTC_PENDING_BASIC_GPU2_25 0x080000 83297580Sskra#define INTC_PENDING_BASIC_GPU2_30 0x100000 84297580Sskra#define INTC_PENDING_BASIC_MASK 0x1FFFFF 85297580Sskra 86297580Sskra#define INTC_PENDING_BASIC_GPU1_MASK (INTC_PENDING_BASIC_GPU1_7 | \ 87297580Sskra INTC_PENDING_BASIC_GPU1_9 | \ 88297580Sskra INTC_PENDING_BASIC_GPU1_10 | \ 89297580Sskra INTC_PENDING_BASIC_GPU1_18 | \ 90297580Sskra INTC_PENDING_BASIC_GPU1_19) 91297580Sskra 92297580Sskra#define INTC_PENDING_BASIC_GPU2_MASK (INTC_PENDING_BASIC_GPU2_21 | \ 93297580Sskra INTC_PENDING_BASIC_GPU2_22 | \ 94297580Sskra INTC_PENDING_BASIC_GPU2_23 | \ 95297580Sskra INTC_PENDING_BASIC_GPU2_24 | \ 96297580Sskra INTC_PENDING_BASIC_GPU2_25 | \ 97297580Sskra INTC_PENDING_BASIC_GPU2_30) 98297580Sskra 99297580Sskra#define INTC_PENDING_BANK1_MASK (~((1 << 7) | (1 << 9) | (1 << 10) | \ 100297580Sskra (1 << 18) | (1 << 19))) 101297580Sskra#define INTC_PENDING_BANK2_MASK (~((1 << 21) | (1 << 22) | (1 << 23) | \ 102297580Sskra (1 << 24) | (1 << 25) | (1 << 30))) 103297580Sskra 104239922Sgonzo#define BANK1_START 8 105239922Sgonzo#define BANK1_END (BANK1_START + 32 - 1) 106239922Sgonzo#define BANK2_START (BANK1_START + 32) 107239922Sgonzo#define BANK2_END (BANK2_START + 32 - 1) 108298068Sandrew#ifndef INTRNG 109266470Shselasky#define BANK3_START (BANK2_START + 32) 110280558Sandrew#define BANK3_END (BANK3_START + 32 - 1) 111297580Sskra#endif 112239922Sgonzo 113239922Sgonzo#define IS_IRQ_BASIC(n) (((n) >= 0) && ((n) < BANK1_START)) 114239922Sgonzo#define IS_IRQ_BANK1(n) (((n) >= BANK1_START) && ((n) <= BANK1_END)) 115239922Sgonzo#define IS_IRQ_BANK2(n) (((n) >= BANK2_START) && ((n) <= BANK2_END)) 116298068Sandrew#ifndef INTRNG 117280558Sandrew#define ID_IRQ_BCM2836(n) (((n) >= BANK3_START) && ((n) <= BANK3_END)) 118297580Sskra#endif 119239922Sgonzo#define IRQ_BANK1(n) ((n) - BANK1_START) 120239922Sgonzo#define IRQ_BANK2(n) ((n) - BANK2_START) 121239922Sgonzo 122239922Sgonzo#ifdef DEBUG 123239922Sgonzo#define dprintf(fmt, args...) printf(fmt, ##args) 124239922Sgonzo#else 125239922Sgonzo#define dprintf(fmt, args...) 126239922Sgonzo#endif 127239922Sgonzo 128298068Sandrew#ifdef INTRNG 129297580Sskra#define BCM_INTC_NIRQS 72 /* 8 + 32 + 32 */ 130297580Sskra 131297580Sskrastruct bcm_intc_irqsrc { 132297580Sskra struct intr_irqsrc bii_isrc; 133297580Sskra u_int bii_irq; 134297580Sskra uint16_t bii_disable_reg; 135297580Sskra uint16_t bii_enable_reg; 136297580Sskra uint32_t bii_mask; 137297580Sskra}; 138297580Sskra#endif 139297580Sskra 140239922Sgonzostruct bcm_intc_softc { 141239922Sgonzo device_t sc_dev; 142239922Sgonzo struct resource * intc_res; 143239922Sgonzo bus_space_tag_t intc_bst; 144239922Sgonzo bus_space_handle_t intc_bsh; 145298068Sandrew#ifdef INTRNG 146297580Sskra struct resource * intc_irq_res; 147297580Sskra void * intc_irq_hdl; 148297580Sskra struct bcm_intc_irqsrc intc_isrcs[BCM_INTC_NIRQS]; 149297580Sskra#endif 150239922Sgonzo}; 151239922Sgonzo 152239922Sgonzostatic struct bcm_intc_softc *bcm_intc_sc = NULL; 153239922Sgonzo 154276017Sandrew#define intc_read_4(_sc, reg) \ 155276017Sandrew bus_space_read_4((_sc)->intc_bst, (_sc)->intc_bsh, (reg)) 156276017Sandrew#define intc_write_4(_sc, reg, val) \ 157276017Sandrew bus_space_write_4((_sc)->intc_bst, (_sc)->intc_bsh, (reg), (val)) 158239922Sgonzo 159298068Sandrew#ifdef INTRNG 160297580Sskrastatic inline void 161297580Sskrabcm_intc_isrc_mask(struct bcm_intc_softc *sc, struct bcm_intc_irqsrc *bii) 162297580Sskra{ 163297580Sskra 164297580Sskra intc_write_4(sc, bii->bii_disable_reg, bii->bii_mask); 165297580Sskra} 166297580Sskra 167297580Sskrastatic inline void 168297580Sskrabcm_intc_isrc_unmask(struct bcm_intc_softc *sc, struct bcm_intc_irqsrc *bii) 169297580Sskra{ 170297580Sskra 171297580Sskra intc_write_4(sc, bii->bii_enable_reg, bii->bii_mask); 172297580Sskra} 173297580Sskra 174297580Sskrastatic inline int 175297580Sskrabcm2835_intc_active_intr(struct bcm_intc_softc *sc) 176297580Sskra{ 177297580Sskra uint32_t pending, pending_gpu; 178297580Sskra 179297580Sskra pending = intc_read_4(sc, INTC_PENDING_BASIC) & INTC_PENDING_BASIC_MASK; 180297580Sskra if (pending == 0) 181297580Sskra return (-1); 182297580Sskra if (pending & INTC_PENDING_BASIC_ARM) 183297580Sskra return (ffs(pending) - 1); 184297580Sskra if (pending & INTC_PENDING_BASIC_GPU1_MASK) { 185297580Sskra if (pending & INTC_PENDING_BASIC_GPU1_7) 186297580Sskra return (BANK1_START + 7); 187297580Sskra if (pending & INTC_PENDING_BASIC_GPU1_9) 188297580Sskra return (BANK1_START + 9); 189297580Sskra if (pending & INTC_PENDING_BASIC_GPU1_10) 190297580Sskra return (BANK1_START + 10); 191297580Sskra if (pending & INTC_PENDING_BASIC_GPU1_18) 192297580Sskra return (BANK1_START + 18); 193297580Sskra if (pending & INTC_PENDING_BASIC_GPU1_19) 194297580Sskra return (BANK1_START + 19); 195297580Sskra } 196297580Sskra if (pending & INTC_PENDING_BASIC_GPU2_MASK) { 197297580Sskra if (pending & INTC_PENDING_BASIC_GPU2_21) 198297580Sskra return (BANK2_START + 21); 199297580Sskra if (pending & INTC_PENDING_BASIC_GPU2_22) 200297580Sskra return (BANK2_START + 22); 201297580Sskra if (pending & INTC_PENDING_BASIC_GPU2_23) 202297580Sskra return (BANK2_START + 23); 203297580Sskra if (pending & INTC_PENDING_BASIC_GPU2_24) 204297580Sskra return (BANK2_START + 24); 205297580Sskra if (pending & INTC_PENDING_BASIC_GPU2_25) 206297580Sskra return (BANK2_START + 25); 207297580Sskra if (pending & INTC_PENDING_BASIC_GPU2_30) 208297580Sskra return (BANK2_START + 30); 209297580Sskra } 210297580Sskra if (pending & INTC_PENDING_BASIC_GPU1_PEND) { 211297580Sskra pending_gpu = intc_read_4(sc, INTC_PENDING_BANK1); 212297580Sskra pending_gpu &= INTC_PENDING_BANK1_MASK; 213297580Sskra if (pending_gpu != 0) 214297580Sskra return (BANK1_START + ffs(pending_gpu) - 1); 215297580Sskra } 216297580Sskra if (pending & INTC_PENDING_BASIC_GPU2_PEND) { 217297580Sskra pending_gpu = intc_read_4(sc, INTC_PENDING_BANK2); 218297580Sskra pending_gpu &= INTC_PENDING_BANK2_MASK; 219297580Sskra if (pending_gpu != 0) 220297580Sskra return (BANK2_START + ffs(pending_gpu) - 1); 221297580Sskra } 222297580Sskra return (-1); /* It shouldn't end here, but it's hardware. */ 223297580Sskra} 224297580Sskra 225239922Sgonzostatic int 226297580Sskrabcm2835_intc_intr(void *arg) 227297580Sskra{ 228297580Sskra int irq, num; 229297580Sskra struct bcm_intc_softc *sc = arg; 230297580Sskra 231297580Sskra for (num = 0; ; num++) { 232297580Sskra irq = bcm2835_intc_active_intr(sc); 233297580Sskra if (irq == -1) 234297580Sskra break; 235297580Sskra if (intr_isrc_dispatch(&sc->intc_isrcs[irq].bii_isrc, 236297580Sskra curthread->td_intr_frame) != 0) { 237297580Sskra bcm_intc_isrc_mask(sc, &sc->intc_isrcs[irq]); 238297580Sskra device_printf(sc->sc_dev, "Stray irq %u disabled\n", 239297580Sskra irq); 240297580Sskra } 241297580Sskra arm_irq_memory_barrier(0); /* XXX */ 242297580Sskra } 243297580Sskra if (num == 0) 244297580Sskra device_printf(sc->sc_dev, "Spurious interrupt detected\n"); 245297580Sskra 246297580Sskra return (FILTER_HANDLED); 247297580Sskra} 248297580Sskra 249297580Sskrastatic void 250297580Sskrabcm_intc_enable_intr(device_t dev, struct intr_irqsrc *isrc) 251297580Sskra{ 252297580Sskra struct bcm_intc_irqsrc *bii = (struct bcm_intc_irqsrc *)isrc; 253297580Sskra 254297580Sskra arm_irq_memory_barrier(bii->bii_irq); 255297580Sskra bcm_intc_isrc_unmask(device_get_softc(dev), bii); 256297580Sskra} 257297580Sskra 258297580Sskrastatic void 259297580Sskrabcm_intc_disable_intr(device_t dev, struct intr_irqsrc *isrc) 260297580Sskra{ 261297580Sskra 262297580Sskra bcm_intc_isrc_mask(device_get_softc(dev), 263297580Sskra (struct bcm_intc_irqsrc *)isrc); 264297580Sskra} 265297580Sskra 266297580Sskrastatic int 267297580Sskrabcm_intc_map_intr(device_t dev, struct intr_map_data *data, 268297580Sskra struct intr_irqsrc **isrcp) 269297580Sskra{ 270297580Sskra u_int irq; 271299117Sskra struct intr_map_data_fdt *daf; 272297580Sskra struct bcm_intc_softc *sc; 273307575Sgonzo bool valid; 274297580Sskra 275297580Sskra if (data->type != INTR_MAP_DATA_FDT) 276297580Sskra return (ENOTSUP); 277299117Sskra 278299117Sskra daf = (struct intr_map_data_fdt *)data; 279299117Sskra if (daf->ncells == 1) 280299117Sskra irq = daf->cells[0]; 281307575Sgonzo else if (daf->ncells == 2) { 282307575Sgonzo valid = true; 283307575Sgonzo switch (daf->cells[0]) { 284307575Sgonzo case 0: 285307575Sgonzo irq = daf->cells[1]; 286307575Sgonzo if (irq >= BANK1_START) 287307575Sgonzo valid = false; 288307575Sgonzo break; 289307575Sgonzo case 1: 290307575Sgonzo irq = daf->cells[1] + BANK1_START; 291307575Sgonzo if (irq > BANK1_END) 292307575Sgonzo valid = false; 293307575Sgonzo break; 294307575Sgonzo case 2: 295307575Sgonzo irq = daf->cells[1] + BANK2_START; 296307575Sgonzo if (irq > BANK2_END) 297307575Sgonzo valid = false; 298307575Sgonzo break; 299307575Sgonzo default: 300307575Sgonzo valid = false; 301307575Sgonzo break; 302307575Sgonzo } 303307575Sgonzo 304307575Sgonzo if (!valid) { 305307575Sgonzo device_printf(dev, 306307575Sgonzo "invalid IRQ config: bank=%d, irq=%d\n", 307307575Sgonzo daf->cells[0], daf->cells[1]); 308307575Sgonzo return (EINVAL); 309307575Sgonzo } 310307575Sgonzo } 311297580Sskra else 312297580Sskra return (EINVAL); 313297580Sskra 314297580Sskra if (irq >= BCM_INTC_NIRQS) 315297580Sskra return (EINVAL); 316297580Sskra 317297580Sskra sc = device_get_softc(dev); 318297580Sskra *isrcp = &sc->intc_isrcs[irq].bii_isrc; 319297580Sskra return (0); 320297580Sskra} 321297580Sskra 322297580Sskrastatic void 323297580Sskrabcm_intc_pre_ithread(device_t dev, struct intr_irqsrc *isrc) 324297580Sskra{ 325297580Sskra 326297580Sskra bcm_intc_disable_intr(dev, isrc); 327297580Sskra} 328297580Sskra 329297580Sskrastatic void 330297580Sskrabcm_intc_post_ithread(device_t dev, struct intr_irqsrc *isrc) 331297580Sskra{ 332297580Sskra 333297580Sskra bcm_intc_enable_intr(dev, isrc); 334297580Sskra} 335297580Sskra 336297580Sskrastatic void 337297580Sskrabcm_intc_post_filter(device_t dev, struct intr_irqsrc *isrc) 338297580Sskra{ 339297580Sskra} 340297580Sskra 341297580Sskrastatic int 342297580Sskrabcm_intc_pic_register(struct bcm_intc_softc *sc, intptr_t xref) 343297580Sskra{ 344297580Sskra struct bcm_intc_irqsrc *bii; 345297580Sskra int error; 346297580Sskra uint32_t irq; 347297580Sskra const char *name; 348297580Sskra 349297580Sskra name = device_get_nameunit(sc->sc_dev); 350297580Sskra for (irq = 0; irq < BCM_INTC_NIRQS; irq++) { 351297580Sskra bii = &sc->intc_isrcs[irq]; 352297580Sskra bii->bii_irq = irq; 353297580Sskra if (IS_IRQ_BASIC(irq)) { 354297580Sskra bii->bii_disable_reg = INTC_DISABLE_BASIC; 355297580Sskra bii->bii_enable_reg = INTC_ENABLE_BASIC; 356297580Sskra bii->bii_mask = 1 << irq; 357297580Sskra } else if (IS_IRQ_BANK1(irq)) { 358297580Sskra bii->bii_disable_reg = INTC_DISABLE_BANK1; 359297580Sskra bii->bii_enable_reg = INTC_ENABLE_BANK1; 360297580Sskra bii->bii_mask = 1 << IRQ_BANK1(irq); 361297580Sskra } else if (IS_IRQ_BANK2(irq)) { 362297580Sskra bii->bii_disable_reg = INTC_DISABLE_BANK2; 363297580Sskra bii->bii_enable_reg = INTC_ENABLE_BANK2; 364297580Sskra bii->bii_mask = 1 << IRQ_BANK2(irq); 365297580Sskra } else 366297580Sskra return (ENXIO); 367297580Sskra 368297580Sskra error = intr_isrc_register(&bii->bii_isrc, sc->sc_dev, 0, 369297580Sskra "%s,%u", name, irq); 370297580Sskra if (error != 0) 371297580Sskra return (error); 372297580Sskra } 373300149Sandrew if (intr_pic_register(sc->sc_dev, xref) == NULL) 374300149Sandrew return (ENXIO); 375300149Sandrew 376300149Sandrew return (0); 377297580Sskra} 378297580Sskra#endif 379297580Sskra 380297580Sskrastatic int 381239922Sgonzobcm_intc_probe(device_t dev) 382239922Sgonzo{ 383261410Sian 384261410Sian if (!ofw_bus_status_okay(dev)) 385261410Sian return (ENXIO); 386261410Sian 387307575Sgonzo if (!ofw_bus_is_compatible(dev, "broadcom,bcm2835-armctrl-ic") && 388307575Sgonzo !ofw_bus_is_compatible(dev, "brcm,bcm2836-armctrl-ic")) 389239922Sgonzo return (ENXIO); 390239922Sgonzo device_set_desc(dev, "BCM2835 Interrupt Controller"); 391239922Sgonzo return (BUS_PROBE_DEFAULT); 392239922Sgonzo} 393239922Sgonzo 394239922Sgonzostatic int 395239922Sgonzobcm_intc_attach(device_t dev) 396239922Sgonzo{ 397239922Sgonzo struct bcm_intc_softc *sc = device_get_softc(dev); 398239922Sgonzo int rid = 0; 399298068Sandrew#ifdef INTRNG 400297580Sskra intptr_t xref; 401297580Sskra#endif 402239922Sgonzo sc->sc_dev = dev; 403239922Sgonzo 404239922Sgonzo if (bcm_intc_sc) 405239922Sgonzo return (ENXIO); 406239922Sgonzo 407239922Sgonzo sc->intc_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); 408239922Sgonzo if (sc->intc_res == NULL) { 409239922Sgonzo device_printf(dev, "could not allocate memory resource\n"); 410239922Sgonzo return (ENXIO); 411239922Sgonzo } 412239922Sgonzo 413298068Sandrew#ifdef INTRNG 414297580Sskra xref = OF_xref_from_node(ofw_bus_get_node(dev)); 415297580Sskra if (bcm_intc_pic_register(sc, xref) != 0) { 416297580Sskra bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->intc_res); 417297580Sskra device_printf(dev, "could not register PIC\n"); 418297580Sskra return (ENXIO); 419297580Sskra } 420297580Sskra 421297580Sskra rid = 0; 422297580Sskra sc->intc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 423297580Sskra RF_ACTIVE); 424297580Sskra if (sc->intc_irq_res == NULL) { 425297580Sskra if (intr_pic_claim_root(dev, xref, bcm2835_intc_intr, sc, 0) != 0) { 426297580Sskra /* XXX clean up */ 427297580Sskra device_printf(dev, "could not set PIC as a root\n"); 428297580Sskra return (ENXIO); 429297580Sskra } 430297580Sskra } else { 431297580Sskra if (bus_setup_intr(dev, sc->intc_irq_res, INTR_TYPE_CLK, 432297580Sskra bcm2835_intc_intr, NULL, sc, &sc->intc_irq_hdl)) { 433297580Sskra /* XXX clean up */ 434297580Sskra device_printf(dev, "could not setup irq handler\n"); 435297580Sskra return (ENXIO); 436297580Sskra } 437297580Sskra } 438297580Sskra#endif 439239922Sgonzo sc->intc_bst = rman_get_bustag(sc->intc_res); 440239922Sgonzo sc->intc_bsh = rman_get_bushandle(sc->intc_res); 441239922Sgonzo 442239922Sgonzo bcm_intc_sc = sc; 443239922Sgonzo 444239922Sgonzo return (0); 445239922Sgonzo} 446239922Sgonzo 447239922Sgonzostatic device_method_t bcm_intc_methods[] = { 448239922Sgonzo DEVMETHOD(device_probe, bcm_intc_probe), 449239922Sgonzo DEVMETHOD(device_attach, bcm_intc_attach), 450297580Sskra 451298068Sandrew#ifdef INTRNG 452297580Sskra DEVMETHOD(pic_disable_intr, bcm_intc_disable_intr), 453297580Sskra DEVMETHOD(pic_enable_intr, bcm_intc_enable_intr), 454297580Sskra DEVMETHOD(pic_map_intr, bcm_intc_map_intr), 455297580Sskra DEVMETHOD(pic_post_filter, bcm_intc_post_filter), 456297580Sskra DEVMETHOD(pic_post_ithread, bcm_intc_post_ithread), 457297580Sskra DEVMETHOD(pic_pre_ithread, bcm_intc_pre_ithread), 458297580Sskra#endif 459297580Sskra 460239922Sgonzo { 0, 0 } 461239922Sgonzo}; 462239922Sgonzo 463239922Sgonzostatic driver_t bcm_intc_driver = { 464239922Sgonzo "intc", 465239922Sgonzo bcm_intc_methods, 466239922Sgonzo sizeof(struct bcm_intc_softc), 467239922Sgonzo}; 468239922Sgonzo 469239922Sgonzostatic devclass_t bcm_intc_devclass; 470239922Sgonzo 471307575SgonzoEARLY_DRIVER_MODULE(intc, simplebus, bcm_intc_driver, bcm_intc_devclass, 472307575Sgonzo 0, 0, BUS_PASS_INTERRUPT + BUS_PASS_ORDER_LATE); 473239922Sgonzo 474298068Sandrew#ifndef INTRNG 475239922Sgonzoint 476239922Sgonzoarm_get_next_irq(int last_irq) 477239922Sgonzo{ 478276017Sandrew struct bcm_intc_softc *sc = bcm_intc_sc; 479239922Sgonzo uint32_t pending; 480239922Sgonzo int32_t irq = last_irq + 1; 481280558Sandrew#ifdef SOC_BCM2836 482280558Sandrew int ret; 483280558Sandrew#endif 484239922Sgonzo 485239922Sgonzo /* Sanity check */ 486239922Sgonzo if (irq < 0) 487239922Sgonzo irq = 0; 488266470Shselasky 489280558Sandrew#ifdef SOC_BCM2836 490290457Sskra if ((ret = bcm2836_get_next_irq(irq)) < 0) 491290457Sskra return (-1); 492290457Sskra if (ret != BCM2836_GPU_IRQ) 493280558Sandrew return (ret + BANK3_START); 494280558Sandrew#endif 495280558Sandrew 496239922Sgonzo /* TODO: should we mask last_irq? */ 497266470Shselasky if (irq < BANK1_START) { 498276017Sandrew pending = intc_read_4(sc, INTC_PENDING_BASIC); 499266470Shselasky if ((pending & 0xFF) == 0) { 500266470Shselasky irq = BANK1_START; /* skip to next bank */ 501266470Shselasky } else do { 502266470Shselasky if (pending & (1 << irq)) 503266470Shselasky return irq; 504266470Shselasky irq++; 505266470Shselasky } while (irq < BANK1_START); 506239922Sgonzo } 507266470Shselasky if (irq < BANK2_START) { 508276017Sandrew pending = intc_read_4(sc, INTC_PENDING_BANK1); 509266470Shselasky if (pending == 0) { 510266470Shselasky irq = BANK2_START; /* skip to next bank */ 511266470Shselasky } else do { 512266470Shselasky if (pending & (1 << IRQ_BANK1(irq))) 513266470Shselasky return irq; 514266470Shselasky irq++; 515266470Shselasky } while (irq < BANK2_START); 516239922Sgonzo } 517266470Shselasky if (irq < BANK3_START) { 518276017Sandrew pending = intc_read_4(sc, INTC_PENDING_BANK2); 519266470Shselasky if (pending != 0) do { 520266470Shselasky if (pending & (1 << IRQ_BANK2(irq))) 521266470Shselasky return irq; 522266470Shselasky irq++; 523266470Shselasky } while (irq < BANK3_START); 524239922Sgonzo } 525239922Sgonzo return (-1); 526239922Sgonzo} 527239922Sgonzo 528239922Sgonzovoid 529239922Sgonzoarm_mask_irq(uintptr_t nb) 530239922Sgonzo{ 531276017Sandrew struct bcm_intc_softc *sc = bcm_intc_sc; 532239922Sgonzo dprintf("%s: %d\n", __func__, nb); 533239922Sgonzo 534239922Sgonzo if (IS_IRQ_BASIC(nb)) 535276017Sandrew intc_write_4(sc, INTC_DISABLE_BASIC, (1 << nb)); 536239922Sgonzo else if (IS_IRQ_BANK1(nb)) 537276017Sandrew intc_write_4(sc, INTC_DISABLE_BANK1, (1 << IRQ_BANK1(nb))); 538239922Sgonzo else if (IS_IRQ_BANK2(nb)) 539276017Sandrew intc_write_4(sc, INTC_DISABLE_BANK2, (1 << IRQ_BANK2(nb))); 540280558Sandrew#ifdef SOC_BCM2836 541280558Sandrew else if (ID_IRQ_BCM2836(nb)) 542280558Sandrew bcm2836_mask_irq(nb - BANK3_START); 543280558Sandrew#endif 544239922Sgonzo else 545239922Sgonzo printf("arm_mask_irq: Invalid IRQ number: %d\n", nb); 546239922Sgonzo} 547239922Sgonzo 548239922Sgonzovoid 549239922Sgonzoarm_unmask_irq(uintptr_t nb) 550239922Sgonzo{ 551276017Sandrew struct bcm_intc_softc *sc = bcm_intc_sc; 552239922Sgonzo dprintf("%s: %d\n", __func__, nb); 553239922Sgonzo 554239922Sgonzo if (IS_IRQ_BASIC(nb)) 555276017Sandrew intc_write_4(sc, INTC_ENABLE_BASIC, (1 << nb)); 556239922Sgonzo else if (IS_IRQ_BANK1(nb)) 557276017Sandrew intc_write_4(sc, INTC_ENABLE_BANK1, (1 << IRQ_BANK1(nb))); 558239922Sgonzo else if (IS_IRQ_BANK2(nb)) 559276017Sandrew intc_write_4(sc, INTC_ENABLE_BANK2, (1 << IRQ_BANK2(nb))); 560280558Sandrew#ifdef SOC_BCM2836 561280558Sandrew else if (ID_IRQ_BCM2836(nb)) 562280558Sandrew bcm2836_unmask_irq(nb - BANK3_START); 563280558Sandrew#endif 564239922Sgonzo else 565239922Sgonzo printf("arm_mask_irq: Invalid IRQ number: %d\n", nb); 566239922Sgonzo} 567296100Sandrew 568296100Sandrew#ifdef SMP 569296100Sandrewvoid 570296100Sandrewintr_pic_init_secondary(void) 571296100Sandrew{ 572296100Sandrew} 573296100Sandrew#endif 574297580Sskra#endif 575