if_ate.c revision 271859
1/*- 2 * Copyright (c) 2006 M. Warner Losh. All rights reserved. 3 * Copyright (c) 2009 Greg Ansley. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27/* TODO 28 * 29 * 1) Turn on the clock in pmc? Turn off? 30 * 2) GPIO initializtion in board setup code. 31 */ 32 33#include "opt_platform.h" 34 35#include <sys/cdefs.h> 36__FBSDID("$FreeBSD: head/sys/arm/at91/if_ate.c 271859 2014-09-19 09:20:16Z glebius $"); 37 38#include <sys/param.h> 39#include <sys/systm.h> 40#include <sys/bus.h> 41#include <sys/kernel.h> 42#include <sys/malloc.h> 43#include <sys/mbuf.h> 44#include <sys/module.h> 45#include <sys/rman.h> 46#include <sys/socket.h> 47#include <sys/sockio.h> 48#include <sys/sysctl.h> 49 50#include <machine/bus.h> 51 52#include <net/ethernet.h> 53#include <net/if.h> 54#include <net/if_arp.h> 55#include <net/if_dl.h> 56#include <net/if_media.h> 57#include <net/if_mib.h> 58#include <net/if_types.h> 59#include <net/if_var.h> 60 61#ifdef INET 62#include <netinet/in.h> 63#include <netinet/in_systm.h> 64#include <netinet/in_var.h> 65#include <netinet/ip.h> 66#endif 67 68#include <net/bpf.h> 69#include <net/bpfdesc.h> 70 71#include <dev/mii/mii.h> 72#include <dev/mii/miivar.h> 73 74#include "opt_at91.h" 75#include <arm/at91/at91reg.h> 76#include <arm/at91/at91var.h> 77#include <arm/at91/if_atereg.h> 78 79#ifdef FDT 80#include <dev/fdt/fdt_common.h> 81#include <dev/ofw/ofw_bus.h> 82#include <dev/ofw/ofw_bus_subr.h> 83#endif 84 85#include "miibus_if.h" 86 87/* 88 * Driver-specific flags. 89 */ 90#define ATE_FLAG_DETACHING 0x01 91#define ATE_FLAG_MULTICAST 0x02 92 93/* 94 * Old EMAC assumes whole packet fits in one buffer; 95 * new EBACB assumes all receive buffers are 128 bytes 96 */ 97#define RX_BUF_SIZE(sc) (sc->is_emacb ? 128 : MCLBYTES) 98 99/* 100 * EMACB has an 11 bit counter for Rx/Tx Descriptors 101 * for max total of 1024 decriptors each. 102 */ 103#define ATE_MAX_RX_DESCR 1024 104#define ATE_MAX_TX_DESCR 1024 105 106/* How many buffers to allocate */ 107#define ATE_MAX_TX_BUFFERS 4 /* We have ping-pong tx buffers */ 108 109/* How much memory to use for rx buffers */ 110#define ATE_RX_MEMORY (ATE_MAX_RX_DESCR * 128) 111 112/* Actual number of descriptors we allocate */ 113#define ATE_NUM_RX_DESCR ATE_MAX_RX_DESCR 114#define ATE_NUM_TX_DESCR ATE_MAX_TX_BUFFERS 115 116#if ATE_NUM_TX_DESCR > ATE_MAX_TX_DESCR 117#error "Can't have more TX buffers that descriptors" 118#endif 119#if ATE_NUM_RX_DESCR > ATE_MAX_RX_DESCR 120#error "Can't have more RX buffers that descriptors" 121#endif 122 123/* Wrap indexes the same way the hardware does */ 124#define NEXT_RX_IDX(sc, cur) \ 125 ((sc->rx_descs[cur].addr & ETH_WRAP_BIT) ? 0 : (cur + 1)) 126 127#define NEXT_TX_IDX(sc, cur) \ 128 ((sc->tx_descs[cur].status & ETHB_TX_WRAP) ? 0 : (cur + 1)) 129 130struct ate_softc 131{ 132 struct ifnet *ifp; /* ifnet pointer */ 133 struct mtx sc_mtx; /* Basically a perimeter lock */ 134 device_t dev; /* Myself */ 135 device_t miibus; /* My child miibus */ 136 struct resource *irq_res; /* IRQ resource */ 137 struct resource *mem_res; /* Memory resource */ 138 struct callout tick_ch; /* Tick callout */ 139 struct ifmib_iso_8802_3 mibdata; /* Stuff for network mgmt */ 140 bus_dma_tag_t mtag; /* bus dma tag for mbufs */ 141 bus_dma_tag_t rx_tag; 142 bus_dma_tag_t rx_desc_tag; 143 bus_dmamap_t rx_desc_map; 144 bus_dmamap_t rx_map[ATE_MAX_RX_DESCR]; 145 bus_addr_t rx_desc_phys; /* PA of rx descriptors */ 146 eth_rx_desc_t *rx_descs; /* VA of rx descriptors */ 147 void *rx_buf[ATE_NUM_RX_DESCR]; /* RX buffer space */ 148 int rxhead; /* Current RX map/desc index */ 149 uint32_t rx_buf_size; /* Size of Rx buffers */ 150 151 bus_dma_tag_t tx_desc_tag; 152 bus_dmamap_t tx_desc_map; 153 bus_dmamap_t tx_map[ATE_MAX_TX_BUFFERS]; 154 bus_addr_t tx_desc_phys; /* PA of tx descriptors */ 155 eth_tx_desc_t *tx_descs; /* VA of tx descriptors */ 156 int txhead; /* Current TX map/desc index */ 157 int txtail; /* Current TX map/desc index */ 158 struct mbuf *sent_mbuf[ATE_MAX_TX_BUFFERS]; /* Sent mbufs */ 159 void *intrhand; /* Interrupt handle */ 160 int flags; 161 int if_flags; 162 int use_rmii; 163 int is_emacb; /* SAM9x hardware version */ 164}; 165 166static inline uint32_t 167RD4(struct ate_softc *sc, bus_size_t off) 168{ 169 170 return (bus_read_4(sc->mem_res, off)); 171} 172 173static inline void 174WR4(struct ate_softc *sc, bus_size_t off, uint32_t val) 175{ 176 177 bus_write_4(sc->mem_res, off, val); 178} 179 180static inline void 181BARRIER(struct ate_softc *sc, bus_size_t off, bus_size_t len, int flags) 182{ 183 184 bus_barrier(sc->mem_res, off, len, flags); 185} 186 187#define ATE_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 188#define ATE_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 189#define ATE_LOCK_INIT(_sc) \ 190 mtx_init(&_sc->sc_mtx, device_get_nameunit(_sc->dev), \ 191 MTX_NETWORK_LOCK, MTX_DEF) 192#define ATE_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx); 193#define ATE_ASSERT_LOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_OWNED); 194#define ATE_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_NOTOWNED); 195 196static devclass_t ate_devclass; 197 198/* 199 * ifnet entry points. 200 */ 201static void ateinit_locked(void *); 202static void atestart_locked(struct ifnet *); 203 204static void ateinit(void *); 205static void atestart(struct ifnet *); 206static void atestop(struct ate_softc *); 207static int ateioctl(struct ifnet * ifp, u_long, caddr_t); 208 209/* 210 * Bus entry points. 211 */ 212static int ate_probe(device_t dev); 213static int ate_attach(device_t dev); 214static int ate_detach(device_t dev); 215static void ate_intr(void *); 216 217/* 218 * Helper routines. 219 */ 220static int ate_activate(device_t dev); 221static void ate_deactivate(struct ate_softc *sc); 222static int ate_ifmedia_upd(struct ifnet *ifp); 223static void ate_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr); 224static int ate_get_mac(struct ate_softc *sc, u_char *eaddr); 225static void ate_set_mac(struct ate_softc *sc, u_char *eaddr); 226static void ate_rxfilter(struct ate_softc *sc); 227 228static int ate_miibus_readreg(device_t dev, int phy, int reg); 229 230static int ate_miibus_writereg(device_t dev, int phy, int reg, int data); 231/* 232 * The AT91 family of products has the ethernet interface called EMAC. 233 * However, it isn't self identifying. It is anticipated that the parent bus 234 * code will take care to only add ate devices where they really are. As 235 * such, we do nothing here to identify the device and just set its name. 236 */ 237static int 238ate_probe(device_t dev) 239{ 240#ifdef FDT 241 if (!ofw_bus_is_compatible(dev, "cdns,at32ap7000-macb")) 242 return (ENXIO); 243#endif 244 device_set_desc(dev, "EMAC"); 245 return (0); 246} 247 248static int 249ate_attach(device_t dev) 250{ 251 struct ate_softc *sc; 252 struct ifnet *ifp = NULL; 253 struct sysctl_ctx_list *sctx; 254 struct sysctl_oid *soid; 255 u_char eaddr[ETHER_ADDR_LEN]; 256 uint32_t rnd; 257 int rid, err; 258 259 sc = device_get_softc(dev); 260 sc->dev = dev; 261 ATE_LOCK_INIT(sc); 262 263 rid = 0; 264 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 265 RF_ACTIVE); 266 if (sc->mem_res == NULL) { 267 device_printf(dev, "could not allocate memory resources.\n"); 268 err = ENOMEM; 269 goto out; 270 } 271 rid = 0; 272 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 273 RF_ACTIVE); 274 if (sc->irq_res == NULL) { 275 device_printf(dev, "could not allocate interrupt resources.\n"); 276 err = ENOMEM; 277 goto out; 278 } 279 280 /* New or old version, chooses buffer size. */ 281 sc->is_emacb = at91_is_sam9() || at91_is_sam9xe(); 282 sc->rx_buf_size = RX_BUF_SIZE(sc); 283 284 err = ate_activate(dev); 285 if (err) 286 goto out; 287 288 /* Default to what boot rom did */ 289 if (!sc->is_emacb) 290 sc->use_rmii = 291 (RD4(sc, ETH_CFG) & ETH_CFG_RMII) == ETH_CFG_RMII; 292 else 293 sc->use_rmii = 294 (RD4(sc, ETHB_UIO) & ETHB_UIO_RMII) == ETHB_UIO_RMII; 295 296#ifdef AT91_ATE_USE_RMII 297 /* Compile time override */ 298 sc->use_rmii = 1; 299#endif 300 /* Sysctls */ 301 sctx = device_get_sysctl_ctx(dev); 302 soid = device_get_sysctl_tree(dev); 303 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "rmii", 304 CTLFLAG_RW, &sc->use_rmii, 0, "rmii in use"); 305 306 /* Calling atestop before ifp is set is OK. */ 307 ATE_LOCK(sc); 308 atestop(sc); 309 ATE_UNLOCK(sc); 310 callout_init_mtx(&sc->tick_ch, &sc->sc_mtx, 0); 311 312 if ((err = ate_get_mac(sc, eaddr)) != 0) { 313 /* No MAC address configured. Generate the random one. */ 314 if (bootverbose) 315 device_printf(dev, 316 "Generating random ethernet address.\n"); 317 rnd = arc4random(); 318 319 /* 320 * Set OUI to convenient locally assigned address. 'b' 321 * is 0x62, which has the locally assigned bit set, and 322 * the broadcast/multicast bit clear. 323 */ 324 eaddr[0] = 'b'; 325 eaddr[1] = 's'; 326 eaddr[2] = 'd'; 327 eaddr[3] = (rnd >> 16) & 0xff; 328 eaddr[4] = (rnd >> 8) & 0xff; 329 eaddr[5] = (rnd >> 0) & 0xff; 330 } 331 332 sc->ifp = ifp = if_alloc(IFT_ETHER); 333 err = mii_attach(dev, &sc->miibus, ifp, ate_ifmedia_upd, 334 ate_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0); 335 if (err != 0) { 336 device_printf(dev, "attaching PHYs failed\n"); 337 goto out; 338 } 339 /* 340 * XXX: Clear the isolate bit, or we won't get up, 341 * at least on the HL201 342 */ 343 ate_miibus_writereg(dev, 0, 0, 0x3000); 344 345 ifp->if_softc = sc; 346 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 347 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 348 ifp->if_capabilities |= IFCAP_VLAN_MTU; 349 ifp->if_capenable |= IFCAP_VLAN_MTU; /* The hw bits already set. */ 350 ifp->if_start = atestart; 351 ifp->if_ioctl = ateioctl; 352 ifp->if_init = ateinit; 353 ifp->if_baudrate = 10000000; 354 IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN); 355 ifp->if_snd.ifq_drv_maxlen = IFQ_MAXLEN; 356 IFQ_SET_READY(&ifp->if_snd); 357 ifp->if_linkmib = &sc->mibdata; 358 ifp->if_linkmiblen = sizeof(sc->mibdata); 359 sc->mibdata.dot3Compliance = DOT3COMPLIANCE_COLLS; 360 sc->if_flags = ifp->if_flags; 361 362 ether_ifattach(ifp, eaddr); 363 364 /* Activate the interrupt. */ 365 err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_NET | INTR_MPSAFE, 366 NULL, ate_intr, sc, &sc->intrhand); 367 if (err) { 368 device_printf(dev, "could not establish interrupt handler.\n"); 369 ether_ifdetach(ifp); 370 goto out; 371 } 372 373out: 374 if (err) 375 ate_detach(dev); 376 return (err); 377} 378 379static int 380ate_detach(device_t dev) 381{ 382 struct ate_softc *sc; 383 struct ifnet *ifp; 384 385 sc = device_get_softc(dev); 386 KASSERT(sc != NULL, ("[ate: %d]: sc is NULL", __LINE__)); 387 ifp = sc->ifp; 388 if (device_is_attached(dev)) { 389 ATE_LOCK(sc); 390 sc->flags |= ATE_FLAG_DETACHING; 391 atestop(sc); 392 ATE_UNLOCK(sc); 393 callout_drain(&sc->tick_ch); 394 ether_ifdetach(ifp); 395 } 396 if (sc->miibus != NULL) { 397 device_delete_child(dev, sc->miibus); 398 sc->miibus = NULL; 399 } 400 bus_generic_detach(sc->dev); 401 ate_deactivate(sc); 402 if (sc->intrhand != NULL) { 403 bus_teardown_intr(dev, sc->irq_res, sc->intrhand); 404 sc->intrhand = NULL; 405 } 406 if (ifp != NULL) { 407 if_free(ifp); 408 sc->ifp = NULL; 409 } 410 if (sc->mem_res != NULL) { 411 bus_release_resource(dev, SYS_RES_IOPORT, 412 rman_get_rid(sc->mem_res), sc->mem_res); 413 sc->mem_res = NULL; 414 } 415 if (sc->irq_res != NULL) { 416 bus_release_resource(dev, SYS_RES_IRQ, 417 rman_get_rid(sc->irq_res), sc->irq_res); 418 sc->irq_res = NULL; 419 } 420 ATE_LOCK_DESTROY(sc); 421 return (0); 422} 423 424static void 425ate_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 426{ 427 428 if (error != 0) 429 return; 430 *(bus_addr_t *)arg = segs[0].ds_addr; 431} 432 433static void 434ate_load_rx_buf(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 435{ 436 struct ate_softc *sc; 437 438 if (error != 0) 439 return; 440 sc = (struct ate_softc *)arg; 441 442 bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, BUS_DMASYNC_PREWRITE); 443 sc->rx_descs[sc->rxhead].addr = segs[0].ds_addr; 444 sc->rx_descs[sc->rxhead].status = 0; 445 bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, BUS_DMASYNC_POSTWRITE); 446} 447 448static uint32_t 449ate_mac_hash(const uint8_t *buf) 450{ 451 uint32_t index = 0; 452 for (int i = 0; i < 48; i++) { 453 index ^= ((buf[i >> 3] >> (i & 7)) & 1) << (i % 6); 454 } 455 return (index); 456} 457 458/* 459 * Compute the multicast filter for this device. 460 */ 461static int 462ate_setmcast(struct ate_softc *sc) 463{ 464 uint32_t index; 465 uint32_t mcaf[2]; 466 u_char *af = (u_char *) mcaf; 467 struct ifmultiaddr *ifma; 468 struct ifnet *ifp; 469 470 ifp = sc->ifp; 471 472 if ((ifp->if_flags & IFF_PROMISC) != 0) 473 return (0); 474 if ((ifp->if_flags & IFF_ALLMULTI) != 0) { 475 WR4(sc, ETH_HSL, 0xffffffff); 476 WR4(sc, ETH_HSH, 0xffffffff); 477 return (1); 478 } 479 480 /* Compute the multicast hash. */ 481 mcaf[0] = 0; 482 mcaf[1] = 0; 483 if_maddr_rlock(ifp); 484 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 485 if (ifma->ifma_addr->sa_family != AF_LINK) 486 continue; 487 index = ate_mac_hash(LLADDR((struct sockaddr_dl *) 488 ifma->ifma_addr)); 489 af[index >> 3] |= 1 << (index & 7); 490 } 491 if_maddr_runlock(ifp); 492 493 /* 494 * Write the hash to the hash register. This card can also 495 * accept unicast packets as well as multicast packets using this 496 * register for easier bridging operations, but we don't take 497 * advantage of that. Locks here are to avoid LOR with the 498 * if_maddr_rlock, but might not be strictly necessary. 499 */ 500 WR4(sc, ETH_HSL, mcaf[0]); 501 WR4(sc, ETH_HSH, mcaf[1]); 502 return (mcaf[0] || mcaf[1]); 503} 504 505static int 506ate_activate(device_t dev) 507{ 508 struct ate_softc *sc; 509 int i; 510 511 sc = device_get_softc(dev); 512 513 /* Allocate DMA tags and maps for TX mbufs */ 514 if (bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0, 515 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 516 1, MCLBYTES, 0, busdma_lock_mutex, &sc->sc_mtx, &sc->mtag)) 517 goto errout; 518 for (i = 0; i < ATE_MAX_TX_BUFFERS; i++) { 519 if ( bus_dmamap_create(sc->mtag, 0, &sc->tx_map[i])) 520 goto errout; 521 } 522 523 524 /* DMA tag and map for the RX descriptors. */ 525 if (bus_dma_tag_create(bus_get_dma_tag(dev), sizeof(eth_rx_desc_t), 526 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 527 ATE_NUM_RX_DESCR * sizeof(eth_rx_desc_t), 1, 528 ATE_NUM_RX_DESCR * sizeof(eth_rx_desc_t), 0, busdma_lock_mutex, 529 &sc->sc_mtx, &sc->rx_desc_tag)) 530 goto errout; 531 if (bus_dmamem_alloc(sc->rx_desc_tag, (void **)&sc->rx_descs, 532 BUS_DMA_NOWAIT | BUS_DMA_COHERENT, &sc->rx_desc_map) != 0) 533 goto errout; 534 if (bus_dmamap_load(sc->rx_desc_tag, sc->rx_desc_map, 535 sc->rx_descs, ATE_NUM_RX_DESCR * sizeof(eth_rx_desc_t), 536 ate_getaddr, &sc->rx_desc_phys, 0) != 0) 537 goto errout; 538 539 /* Allocate DMA tags and maps for RX. buffers */ 540 if (bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0, 541 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 542 sc->rx_buf_size, 1, sc->rx_buf_size, 0, 543 busdma_lock_mutex, &sc->sc_mtx, &sc->rx_tag)) 544 goto errout; 545 546 /* 547 * Allocate our RX buffers. 548 * This chip has a RX structure that's filled in. 549 * XXX On MACB (SAM9 part) we should receive directly into mbuf 550 * to avoid the copy. XXX 551 */ 552 sc->rxhead = 0; 553 for (sc->rxhead = 0; sc->rxhead < ATE_RX_MEMORY/sc->rx_buf_size; 554 sc->rxhead++) { 555 if (bus_dmamem_alloc(sc->rx_tag, 556 (void **)&sc->rx_buf[sc->rxhead], BUS_DMA_NOWAIT, 557 &sc->rx_map[sc->rxhead]) != 0) 558 goto errout; 559 560 if (bus_dmamap_load(sc->rx_tag, sc->rx_map[sc->rxhead], 561 sc->rx_buf[sc->rxhead], sc->rx_buf_size, 562 ate_load_rx_buf, sc, 0) != 0) { 563 printf("bus_dmamem_load\n"); 564 goto errout; 565 } 566 bus_dmamap_sync(sc->rx_tag, sc->rx_map[sc->rxhead], BUS_DMASYNC_PREREAD); 567 } 568 569 /* 570 * For the last buffer, set the wrap bit so the controller 571 * restarts from the first descriptor. 572 */ 573 sc->rx_descs[--sc->rxhead].addr |= ETH_WRAP_BIT; 574 sc->rxhead = 0; 575 576 /* Flush the memory for the EMAC rx descriptor. */ 577 bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, BUS_DMASYNC_PREWRITE); 578 579 /* Write the descriptor queue address. */ 580 WR4(sc, ETH_RBQP, sc->rx_desc_phys); 581 582 /* 583 * DMA tag and map for the TX descriptors. 584 */ 585 if (bus_dma_tag_create(bus_get_dma_tag(dev), sizeof(eth_tx_desc_t), 586 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 587 ATE_MAX_TX_BUFFERS * sizeof(eth_tx_desc_t), 1, 588 ATE_MAX_TX_BUFFERS * sizeof(eth_tx_desc_t), 0, busdma_lock_mutex, 589 &sc->sc_mtx, &sc->tx_desc_tag) != 0) 590 goto errout; 591 592 if (bus_dmamem_alloc(sc->tx_desc_tag, (void **)&sc->tx_descs, 593 BUS_DMA_NOWAIT | BUS_DMA_COHERENT, &sc->tx_desc_map) != 0) 594 goto errout; 595 596 if (bus_dmamap_load(sc->tx_desc_tag, sc->tx_desc_map, 597 sc->tx_descs, ATE_MAX_TX_BUFFERS * sizeof(eth_tx_desc_t), 598 ate_getaddr, &sc->tx_desc_phys, 0) != 0) 599 goto errout; 600 601 /* Initilize descriptors; mark all empty */ 602 for (i = 0; i < ATE_MAX_TX_BUFFERS; i++) { 603 sc->tx_descs[i].addr =0; 604 sc->tx_descs[i].status = ETHB_TX_USED; 605 sc->sent_mbuf[i] = NULL; 606 } 607 608 /* Mark last entry to cause wrap when indexing through */ 609 sc->tx_descs[ATE_MAX_TX_BUFFERS - 1].status = 610 ETHB_TX_WRAP | ETHB_TX_USED; 611 612 /* Flush the memory for the EMAC tx descriptor. */ 613 bus_dmamap_sync(sc->tx_desc_tag, sc->tx_desc_map, BUS_DMASYNC_PREWRITE); 614 615 sc->txhead = sc->txtail = 0; 616 if (sc->is_emacb) { 617 /* Write the descriptor queue address. */ 618 WR4(sc, ETHB_TBQP, sc->tx_desc_phys); 619 620 /* EMACB: Enable transceiver input clock */ 621 WR4(sc, ETHB_UIO, RD4(sc, ETHB_UIO) | ETHB_UIO_CLKE); 622 } 623 624 return (0); 625 626errout: 627 return (ENOMEM); 628} 629 630static void 631ate_deactivate(struct ate_softc *sc) 632{ 633 int i; 634 635 KASSERT(sc != NULL, ("[ate, %d]: sc is NULL!", __LINE__)); 636 if (sc->mtag != NULL) { 637 for (i = 0; i < ATE_MAX_TX_BUFFERS; i++) { 638 if (sc->sent_mbuf[i] != NULL) { 639 bus_dmamap_sync(sc->mtag, sc->tx_map[i], 640 BUS_DMASYNC_POSTWRITE); 641 bus_dmamap_unload(sc->mtag, sc->tx_map[i]); 642 m_freem(sc->sent_mbuf[i]); 643 } 644 bus_dmamap_destroy(sc->mtag, sc->tx_map[i]); 645 sc->sent_mbuf[i] = NULL; 646 sc->tx_map[i] = NULL; 647 } 648 bus_dma_tag_destroy(sc->mtag); 649 } 650 if (sc->rx_desc_tag != NULL) { 651 if (sc->rx_descs != NULL) { 652 if (sc->rx_desc_phys != 0) { 653 bus_dmamap_sync(sc->rx_desc_tag, 654 sc->rx_desc_map, BUS_DMASYNC_POSTREAD); 655 bus_dmamap_unload(sc->rx_desc_tag, 656 sc->rx_desc_map); 657 sc->rx_desc_phys = 0; 658 } 659 } 660 } 661 if (sc->rx_tag != NULL) { 662 for (i = 0; sc->rx_buf[i] != NULL; i++) { 663 if (sc->rx_descs[i].addr != 0) { 664 bus_dmamap_sync(sc->rx_tag, 665 sc->rx_map[i], 666 BUS_DMASYNC_POSTREAD); 667 bus_dmamap_unload(sc->rx_tag, 668 sc->rx_map[i]); 669 sc->rx_descs[i].addr = 0; 670 } 671 bus_dmamem_free(sc->rx_tag, sc->rx_buf[i], 672 sc->rx_map[i]); 673 sc->rx_buf[i] = NULL; 674 } 675 bus_dma_tag_destroy(sc->rx_tag); 676 } 677 if (sc->rx_desc_tag != NULL) { 678 if (sc->rx_descs != NULL) 679 bus_dmamem_free(sc->rx_desc_tag, sc->rx_descs, 680 sc->rx_desc_map); 681 bus_dma_tag_destroy(sc->rx_desc_tag); 682 sc->rx_descs = NULL; 683 sc->rx_desc_tag = NULL; 684 } 685 686 if (sc->is_emacb) 687 WR4(sc, ETHB_UIO, RD4(sc, ETHB_UIO) & ~ETHB_UIO_CLKE); 688} 689 690/* 691 * Change media according to request. 692 */ 693static int 694ate_ifmedia_upd(struct ifnet *ifp) 695{ 696 struct ate_softc *sc = ifp->if_softc; 697 struct mii_data *mii; 698 699 mii = device_get_softc(sc->miibus); 700 ATE_LOCK(sc); 701 mii_mediachg(mii); 702 ATE_UNLOCK(sc); 703 return (0); 704} 705 706/* 707 * Notify the world which media we're using. 708 */ 709static void 710ate_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 711{ 712 struct ate_softc *sc = ifp->if_softc; 713 struct mii_data *mii; 714 715 mii = device_get_softc(sc->miibus); 716 ATE_LOCK(sc); 717 mii_pollstat(mii); 718 ifmr->ifm_active = mii->mii_media_active; 719 ifmr->ifm_status = mii->mii_media_status; 720 ATE_UNLOCK(sc); 721} 722 723static void 724ate_stat_update(struct ate_softc *sc, int active) 725{ 726 uint32_t reg; 727 728 /* 729 * The speed and full/half-duplex state needs to be reflected 730 * in the ETH_CFG register. 731 */ 732 reg = RD4(sc, ETH_CFG); 733 reg &= ~(ETH_CFG_SPD | ETH_CFG_FD); 734 if (IFM_SUBTYPE(active) != IFM_10_T) 735 reg |= ETH_CFG_SPD; 736 if (active & IFM_FDX) 737 reg |= ETH_CFG_FD; 738 WR4(sc, ETH_CFG, reg); 739} 740 741static void 742ate_tick(void *xsc) 743{ 744 struct ate_softc *sc = xsc; 745 struct ifnet *ifp = sc->ifp; 746 struct mii_data *mii; 747 int active; 748 uint32_t c; 749 750 /* 751 * The KB920x boot loader tests ETH_SR & ETH_SR_LINK and will ask 752 * the MII if there's a link if this bit is clear. Not sure if we 753 * should do the same thing here or not. 754 */ 755 ATE_ASSERT_LOCKED(sc); 756 if (sc->miibus != NULL) { 757 mii = device_get_softc(sc->miibus); 758 active = mii->mii_media_active; 759 mii_tick(mii); 760 if (mii->mii_media_status & IFM_ACTIVE && 761 active != mii->mii_media_active) 762 ate_stat_update(sc, mii->mii_media_active); 763 } 764 765 /* 766 * Update the stats as best we can. When we're done, clear 767 * the status counters and start over. We're supposed to read these 768 * registers often enough that they won't overflow. Hopefully 769 * once a second is often enough. Some don't map well to 770 * the dot3Stats mib, so for those we just count them as general 771 * errors. Stats for iframes, ibutes, oframes and obytes are 772 * collected elsewhere. These registers zero on a read to prevent 773 * races. For all the collision stats, also update the collision 774 * stats for the interface. 775 */ 776 sc->mibdata.dot3StatsAlignmentErrors += RD4(sc, ETH_ALE); 777 sc->mibdata.dot3StatsFCSErrors += RD4(sc, ETH_SEQE); 778 c = RD4(sc, ETH_SCOL); 779 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, c); 780 sc->mibdata.dot3StatsSingleCollisionFrames += c; 781 c = RD4(sc, ETH_MCOL); 782 sc->mibdata.dot3StatsMultipleCollisionFrames += c; 783 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, c); 784 sc->mibdata.dot3StatsSQETestErrors += RD4(sc, ETH_SQEE); 785 sc->mibdata.dot3StatsDeferredTransmissions += RD4(sc, ETH_DTE); 786 c = RD4(sc, ETH_LCOL); 787 sc->mibdata.dot3StatsLateCollisions += c; 788 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, c); 789 c = RD4(sc, ETH_ECOL); 790 sc->mibdata.dot3StatsExcessiveCollisions += c; 791 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, c); 792 sc->mibdata.dot3StatsCarrierSenseErrors += RD4(sc, ETH_CSE); 793 sc->mibdata.dot3StatsFrameTooLongs += RD4(sc, ETH_ELR); 794 sc->mibdata.dot3StatsInternalMacReceiveErrors += RD4(sc, ETH_DRFC); 795 796 /* 797 * Not sure where to lump these, so count them against the errors 798 * for the interface. 799 */ 800 if_inc_counter(sc->ifp, IFCOUNTER_OERRORS, RD4(sc, ETH_TUE)); 801 if_inc_counter(sc->ifp, IFCOUNTER_IERRORS, 802 RD4(sc, ETH_CDE) + RD4(sc, ETH_RJB) + RD4(sc, ETH_USF)); 803 804 /* Schedule another timeout one second from now. */ 805 callout_reset(&sc->tick_ch, hz, ate_tick, sc); 806} 807 808static void 809ate_set_mac(struct ate_softc *sc, u_char *eaddr) 810{ 811 812 WR4(sc, ETH_SA1L, (eaddr[3] << 24) | (eaddr[2] << 16) | 813 (eaddr[1] << 8) | eaddr[0]); 814 WR4(sc, ETH_SA1H, (eaddr[5] << 8) | (eaddr[4])); 815} 816 817static int 818ate_get_mac(struct ate_softc *sc, u_char *eaddr) 819{ 820 bus_size_t sa_low_reg[] = { ETH_SA1L, ETH_SA2L, ETH_SA3L, ETH_SA4L }; 821 bus_size_t sa_high_reg[] = { ETH_SA1H, ETH_SA2H, ETH_SA3H, ETH_SA4H }; 822 uint32_t low, high; 823 int i; 824 825 /* 826 * The boot loader may setup the MAC with an address(es), grab the 827 * first MAC address from the SA[1-4][HL] registers. 828 */ 829 for (i = 0; i < 4; i++) { 830 low = RD4(sc, sa_low_reg[i]); 831 high = RD4(sc, sa_high_reg[i]); 832 if ((low | (high & 0xffff)) != 0) { 833 eaddr[0] = low & 0xff; 834 eaddr[1] = (low >> 8) & 0xff; 835 eaddr[2] = (low >> 16) & 0xff; 836 eaddr[3] = (low >> 24) & 0xff; 837 eaddr[4] = high & 0xff; 838 eaddr[5] = (high >> 8) & 0xff; 839 return (0); 840 } 841 } 842 return (ENXIO); 843} 844 845static void 846ate_intr(void *xsc) 847{ 848 struct ate_softc *sc = xsc; 849 struct ifnet *ifp = sc->ifp; 850 struct mbuf *mb; 851 eth_rx_desc_t *rxdhead; 852 uint32_t status, reg, idx; 853 int remain, count, done; 854 855 status = RD4(sc, ETH_ISR); 856 if (status == 0) 857 return; 858 859 if (status & ETH_ISR_RCOM) { 860 bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, 861 BUS_DMASYNC_POSTREAD); 862 863 rxdhead = &sc->rx_descs[sc->rxhead]; 864 while (rxdhead->addr & ETH_CPU_OWNER) { 865 if (!sc->is_emacb) { 866 /* 867 * Simulate SAM9 FIRST/LAST bits for RM9200. 868 * RM9200 EMAC has only on Rx buffer per packet. 869 * But sometime we are handed a zero lenght packet. 870 */ 871 if ((rxdhead->status & ETH_LEN_MASK) == 0) 872 rxdhead->status = 0; /* Mark error */ 873 else 874 rxdhead->status |= ETH_BUF_FIRST | ETH_BUF_LAST; 875 } 876 877 if ((rxdhead->status & ETH_BUF_FIRST) == 0) { 878 /* Something went wrong during RX so 879 release back to EMAC all buffers of invalid packets. 880 */ 881 rxdhead->status = 0; 882 rxdhead->addr &= ~ETH_CPU_OWNER; 883 sc->rxhead = NEXT_RX_IDX(sc, sc->rxhead); 884 rxdhead = &sc->rx_descs[sc->rxhead]; 885 continue; 886 } 887 888 /* Find end of packet or start of next */ 889 idx = sc->rxhead; 890 if ((sc->rx_descs[idx].status & ETH_BUF_LAST) == 0) { 891 idx = NEXT_RX_IDX(sc, idx); 892 893 while ((sc->rx_descs[idx].addr & ETH_CPU_OWNER) && 894 ((sc->rx_descs[idx].status & 895 (ETH_BUF_FIRST|ETH_BUF_LAST))== 0)) 896 idx = NEXT_RX_IDX(sc, idx); 897 } 898 899 /* Packet NOT yet completely in memory; we are done */ 900 if ((sc->rx_descs[idx].addr & ETH_CPU_OWNER) == 0 || 901 ((sc->rx_descs[idx].status & (ETH_BUF_FIRST|ETH_BUF_LAST))== 0)) 902 break; 903 904 /* Packets with no end descriptor are invalid. */ 905 if ((sc->rx_descs[idx].status & ETH_BUF_LAST) == 0) { 906 rxdhead->status &= ~ETH_BUF_FIRST; 907 continue; 908 } 909 910 /* FCS is not coppied into mbuf. */ 911 remain = (sc->rx_descs[idx].status & ETH_LEN_MASK) - 4; 912 913 /* Get an appropriately sized mbuf. */ 914 mb = m_get2(remain + ETHER_ALIGN, M_NOWAIT, MT_DATA, 915 M_PKTHDR); 916 if (mb == NULL) { 917 if_inc_counter(sc->ifp, IFCOUNTER_IQDROPS, 1); 918 rxdhead->status = 0; 919 continue; 920 } 921 mb->m_data += ETHER_ALIGN; 922 mb->m_pkthdr.rcvif = ifp; 923 924 WR4(sc, ETH_RSR, RD4(sc, ETH_RSR)); /* Reset status */ 925 926 /* Now we process the buffers that make up the packet */ 927 do { 928 929 /* Last buffer may just be 1-4 bytes of FCS so remain 930 * may be zero for last decriptor. */ 931 if (remain > 0) { 932 /* Make sure we get the current bytes */ 933 bus_dmamap_sync(sc->rx_tag, sc->rx_map[sc->rxhead], 934 BUS_DMASYNC_POSTREAD); 935 936 count = MIN(remain, sc->rx_buf_size); 937 938 /* XXX Performance robbing copy. Could 939 * recieve directly to mbufs if not an 940 * RM9200. And even then we could likely 941 * copy just the protocol headers. XXX */ 942 m_append(mb, count, sc->rx_buf[sc->rxhead]); 943 remain -= count; 944 } 945 946 done = (rxdhead->status & ETH_BUF_LAST) != 0; 947 948 /* Return the descriptor to the EMAC */ 949 rxdhead->status = 0; 950 rxdhead->addr &= ~ETH_CPU_OWNER; 951 bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, 952 BUS_DMASYNC_PREWRITE); 953 954 /* Move on to next descriptor with wrap */ 955 sc->rxhead = NEXT_RX_IDX(sc, sc->rxhead); 956 rxdhead = &sc->rx_descs[sc->rxhead]; 957 958 } while (!done); 959 960 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 961 (*ifp->if_input)(ifp, mb); 962 } 963 } 964 965 966 if (status & ETH_ISR_TCOM) { 967 bus_dmamap_sync(sc->tx_desc_tag, sc->tx_desc_map, 968 BUS_DMASYNC_POSTREAD); 969 970 ATE_LOCK(sc); 971 /* XXX TSR register should be cleared */ 972 if (!sc->is_emacb) { 973 /* Simulate Transmit descriptor table */ 974 975 /* First packet done */ 976 if (sc->txtail < sc->txhead) 977 sc->tx_descs[sc->txtail].status |= ETHB_TX_USED; 978 979 /* Second Packet done */ 980 if (sc->txtail + 1 < sc->txhead && 981 RD4(sc, ETH_TSR) & ETH_TSR_IDLE) 982 sc->tx_descs[sc->txtail + 1].status |= ETHB_TX_USED; 983 } 984 985 while ((sc->tx_descs[sc->txtail].status & ETHB_TX_USED) && 986 sc->sent_mbuf[sc->txtail] != NULL) { 987 bus_dmamap_sync(sc->mtag, sc->tx_map[sc->txtail], 988 BUS_DMASYNC_POSTWRITE); 989 bus_dmamap_unload(sc->mtag, sc->tx_map[sc->txtail]); 990 m_freem(sc->sent_mbuf[sc->txtail]); 991 sc->tx_descs[sc->txtail].addr = 0; 992 sc->sent_mbuf[sc->txtail] = NULL; 993 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 994 sc->txtail = NEXT_TX_IDX(sc, sc->txtail); 995 } 996 997 /* Flush descriptors to EMAC */ 998 bus_dmamap_sync(sc->tx_desc_tag, sc->tx_desc_map, BUS_DMASYNC_PREWRITE); 999 1000 /* 1001 * We're no longer busy, so clear the busy flag and call the 1002 * start routine to xmit more packets. 1003 */ 1004 sc->ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1005 atestart_locked(sc->ifp); 1006 ATE_UNLOCK(sc); 1007 } 1008 1009 if (status & ETH_ISR_RBNA) { 1010 /* Workaround RM9200 Errata #11 */ 1011 if (bootverbose) 1012 device_printf(sc->dev, "RBNA workaround\n"); 1013 reg = RD4(sc, ETH_CTL); 1014 WR4(sc, ETH_CTL, reg & ~ETH_CTL_RE); 1015 BARRIER(sc, ETH_CTL, 4, BUS_SPACE_BARRIER_WRITE); 1016 WR4(sc, ETH_CTL, reg | ETH_CTL_RE); 1017 } 1018 1019 /* XXX need to work around SAM9260 errata 43.2.4.1: 1020 * disable the mac, reset tx buffer, enable mac on TUND */ 1021} 1022 1023/* 1024 * Reset and initialize the chip. 1025 */ 1026static void 1027ateinit_locked(void *xsc) 1028{ 1029 struct ate_softc *sc = xsc; 1030 struct ifnet *ifp = sc->ifp; 1031 struct mii_data *mii; 1032 uint8_t eaddr[ETHER_ADDR_LEN]; 1033 uint32_t reg; 1034 1035 ATE_ASSERT_LOCKED(sc); 1036 1037 /* 1038 * XXX TODO(3) 1039 * we need to turn on the EMAC clock in the pmc. With the 1040 * default boot loader, this is already turned on. However, we 1041 * need to think about how best to turn it on/off as the interface 1042 * is brought up/down, as well as dealing with the mii bus... 1043 * 1044 * We also need to multiplex the pins correctly (in board_xxx.c). 1045 */ 1046 1047 /* 1048 * There are two different ways that the mii bus is connected 1049 * to this chip mii or rmii. 1050 */ 1051 if (!sc->is_emacb) { 1052 /* RM9200 */ 1053 reg = RD4(sc, ETH_CFG); 1054 if (sc->use_rmii) 1055 reg |= ETH_CFG_RMII; 1056 else 1057 reg &= ~ETH_CFG_RMII; 1058 WR4(sc, ETH_CFG, reg); 1059 } else { 1060 /* SAM9 */ 1061 reg = ETHB_UIO_CLKE; 1062 reg |= (sc->use_rmii) ? ETHB_UIO_RMII : 0; 1063 WR4(sc, ETHB_UIO, reg); 1064 } 1065 1066 ate_rxfilter(sc); 1067 1068 /* 1069 * Set the chip MAC address. 1070 */ 1071 bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN); 1072 ate_set_mac(sc, eaddr); 1073 1074 /* Make sure we know state of TX queue */ 1075 sc->txhead = sc->txtail = 0; 1076 if (sc->is_emacb) { 1077 /* Write the descriptor queue address. */ 1078 WR4(sc, ETHB_TBQP, sc->tx_desc_phys); 1079 } 1080 1081 /* 1082 * Turn on MACs and interrupt processing. 1083 */ 1084 WR4(sc, ETH_CTL, RD4(sc, ETH_CTL) | ETH_CTL_TE | ETH_CTL_RE); 1085 WR4(sc, ETH_IER, ETH_ISR_RCOM | ETH_ISR_TCOM | ETH_ISR_RBNA); 1086 1087 /* Enable big packets. */ 1088 WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) | ETH_CFG_BIG); 1089 1090 /* 1091 * Set 'running' flag, and clear output active flag 1092 * and attempt to start the output. 1093 */ 1094 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1095 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1096 1097 mii = device_get_softc(sc->miibus); 1098 mii_pollstat(mii); 1099 ate_stat_update(sc, mii->mii_media_active); 1100 atestart_locked(ifp); 1101 1102 callout_reset(&sc->tick_ch, hz, ate_tick, sc); 1103} 1104 1105/* 1106 * Dequeue packets and transmit. 1107 */ 1108static void 1109atestart_locked(struct ifnet *ifp) 1110{ 1111 struct ate_softc *sc = ifp->if_softc; 1112 struct mbuf *m, *mdefrag; 1113 bus_dma_segment_t segs[1]; 1114 int nseg, e; 1115 1116 ATE_ASSERT_LOCKED(sc); 1117 if (ifp->if_drv_flags & IFF_DRV_OACTIVE) 1118 return; 1119 1120 while (sc->tx_descs[sc->txhead].status & ETHB_TX_USED) { 1121 /* 1122 * Check to see if there's room to put another packet into the 1123 * xmit queue. The old EMAC version has a ping-pong buffer for 1124 * xmit packets. We use OACTIVE to indicate "we can stuff more 1125 * into our buffers (clear) or not (set)." 1126 */ 1127 /* RM9200 has only two hardware entries */ 1128 if (!sc->is_emacb && (RD4(sc, ETH_TSR) & ETH_TSR_BNQ) == 0) { 1129 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1130 return; 1131 } 1132 1133 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 1134 if (m == 0) 1135 break; 1136 1137 e = bus_dmamap_load_mbuf_sg(sc->mtag, sc->tx_map[sc->txhead], m, 1138 segs, &nseg, 0); 1139 if (e == EFBIG) { 1140 mdefrag = m_defrag(m, M_NOWAIT); 1141 if (mdefrag == NULL) { 1142 IFQ_DRV_PREPEND(&ifp->if_snd, m); 1143 return; 1144 } 1145 m = mdefrag; 1146 e = bus_dmamap_load_mbuf_sg(sc->mtag, 1147 sc->tx_map[sc->txhead], m, segs, &nseg, 0); 1148 } 1149 if (e != 0) { 1150 m_freem(m); 1151 continue; 1152 } 1153 1154 /* 1155 * There's a small race between the loop in ate_intr finishing 1156 * and the check above to see if the packet was finished, as well 1157 * as when atestart gets called via other paths. Lose the race 1158 * gracefully and free the mbuf... 1159 */ 1160 if (sc->sent_mbuf[sc->txhead] != NULL) { 1161 bus_dmamap_sync(sc->mtag, sc->tx_map[sc->txtail], 1162 BUS_DMASYNC_POSTWRITE); 1163 bus_dmamap_unload(sc->mtag, sc->tx_map[sc->txtail]); 1164 m_free(sc->sent_mbuf[sc->txhead]); 1165 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 1166 } 1167 1168 sc->sent_mbuf[sc->txhead] = m; 1169 1170 bus_dmamap_sync(sc->mtag, sc->tx_map[sc->txhead], 1171 BUS_DMASYNC_PREWRITE); 1172 1173 /* Tell the hardware to xmit the packet. */ 1174 if (!sc->is_emacb) { 1175 WR4(sc, ETH_TAR, segs[0].ds_addr); 1176 BARRIER(sc, ETH_TAR, 4, BUS_SPACE_BARRIER_WRITE); 1177 WR4(sc, ETH_TCR, segs[0].ds_len); 1178 } else { 1179 bus_dmamap_sync(sc->tx_desc_tag, sc->tx_desc_map, 1180 BUS_DMASYNC_POSTWRITE); 1181 sc->tx_descs[sc->txhead].addr = segs[0].ds_addr; 1182 sc->tx_descs[sc->txhead].status = segs[0].ds_len | 1183 (sc->tx_descs[sc->txhead].status & ETHB_TX_WRAP) | 1184 ETHB_TX_BUF_LAST; 1185 bus_dmamap_sync(sc->tx_desc_tag, sc->tx_desc_map, 1186 BUS_DMASYNC_PREWRITE); 1187 WR4(sc, ETH_CTL, RD4(sc, ETH_CTL) | ETHB_CTL_TGO); 1188 } 1189 sc->txhead = NEXT_TX_IDX(sc, sc->txhead); 1190 1191 /* Tap off here if there is a bpf listener. */ 1192 BPF_MTAP(ifp, m); 1193 } 1194 1195 if ((sc->tx_descs[sc->txhead].status & ETHB_TX_USED) == 0) 1196 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1197} 1198 1199static void 1200ateinit(void *xsc) 1201{ 1202 struct ate_softc *sc = xsc; 1203 1204 ATE_LOCK(sc); 1205 ateinit_locked(sc); 1206 ATE_UNLOCK(sc); 1207} 1208 1209static void 1210atestart(struct ifnet *ifp) 1211{ 1212 struct ate_softc *sc = ifp->if_softc; 1213 1214 ATE_LOCK(sc); 1215 atestart_locked(ifp); 1216 ATE_UNLOCK(sc); 1217} 1218 1219/* 1220 * Turn off interrupts, and stop the NIC. Can be called with sc->ifp NULL, 1221 * so be careful. 1222 */ 1223static void 1224atestop(struct ate_softc *sc) 1225{ 1226 struct ifnet *ifp; 1227 int i; 1228 1229 ATE_ASSERT_LOCKED(sc); 1230 ifp = sc->ifp; 1231 if (ifp) { 1232 //ifp->if_timer = 0; 1233 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1234 } 1235 1236 callout_stop(&sc->tick_ch); 1237 1238 /* 1239 * Enable some parts of the MAC that are needed always (like the 1240 * MII bus. This turns off the RE and TE bits, which will remain 1241 * off until ateinit() is called to turn them on. With RE and TE 1242 * turned off, there's no DMA to worry about after this write. 1243 */ 1244 WR4(sc, ETH_CTL, ETH_CTL_MPE); 1245 1246 /* 1247 * Turn off all the configured options and revert to defaults. 1248 */ 1249 1250 /* Make sure thate the MDIO clk is less than 1251 * 2.5 Mhz. Can no longer default to /32 since 1252 * SAM9 family may have MCK > 80 Mhz */ 1253 if (at91_master_clock <= 2000000) 1254 WR4(sc, ETH_CFG, ETH_CFG_CLK_8); 1255 else if (at91_master_clock <= 4000000) 1256 WR4(sc, ETH_CFG, ETH_CFG_CLK_16); 1257 else if (at91_master_clock <= 800000) 1258 WR4(sc, ETH_CFG, ETH_CFG_CLK_32); 1259 else 1260 WR4(sc, ETH_CFG, ETH_CFG_CLK_64); 1261 1262 /* 1263 * Turn off all the interrupts, and ack any pending ones by reading 1264 * the ISR. 1265 */ 1266 WR4(sc, ETH_IDR, 0xffffffff); 1267 RD4(sc, ETH_ISR); 1268 1269 /* 1270 * Clear out the Transmit and Receiver Status registers of any 1271 * errors they may be reporting 1272 */ 1273 WR4(sc, ETH_TSR, 0xffffffff); 1274 WR4(sc, ETH_RSR, 0xffffffff); 1275 1276 /* Release TX resources. */ 1277 for (i = 0; i < ATE_MAX_TX_BUFFERS; i++) { 1278 if (sc->sent_mbuf[i] != NULL) { 1279 bus_dmamap_sync(sc->mtag, sc->tx_map[i], 1280 BUS_DMASYNC_POSTWRITE); 1281 bus_dmamap_unload(sc->mtag, sc->tx_map[i]); 1282 m_freem(sc->sent_mbuf[i]); 1283 sc->sent_mbuf[i] = NULL; 1284 } 1285 } 1286 1287 /* Turn off transeiver input clock */ 1288 if (sc->is_emacb) 1289 WR4(sc, ETHB_UIO, RD4(sc, ETHB_UIO) & ~ETHB_UIO_CLKE); 1290 1291 /* 1292 * XXX we should power down the EMAC if it isn't in use, after 1293 * putting it into loopback mode. This saves about 400uA according 1294 * to the datasheet. 1295 */ 1296} 1297 1298static void 1299ate_rxfilter(struct ate_softc *sc) 1300{ 1301 struct ifnet *ifp; 1302 uint32_t reg; 1303 int enabled; 1304 1305 KASSERT(sc != NULL, ("[ate, %d]: sc is NULL!", __LINE__)); 1306 ATE_ASSERT_LOCKED(sc); 1307 ifp = sc->ifp; 1308 1309 /* Wipe out old filter settings. */ 1310 reg = RD4(sc, ETH_CFG); 1311 reg &= ~(ETH_CFG_CAF | ETH_CFG_MTI | ETH_CFG_UNI); 1312 reg |= ETH_CFG_NBC; 1313 sc->flags &= ~ATE_FLAG_MULTICAST; 1314 1315 /* Set new parameters. */ 1316 if ((ifp->if_flags & IFF_BROADCAST) != 0) 1317 reg &= ~ETH_CFG_NBC; 1318 if ((ifp->if_flags & IFF_PROMISC) != 0) { 1319 reg |= ETH_CFG_CAF; 1320 } else { 1321 enabled = ate_setmcast(sc); 1322 if (enabled != 0) { 1323 reg |= ETH_CFG_MTI; 1324 sc->flags |= ATE_FLAG_MULTICAST; 1325 } 1326 } 1327 WR4(sc, ETH_CFG, reg); 1328} 1329 1330static int 1331ateioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1332{ 1333 struct ate_softc *sc = ifp->if_softc; 1334 struct mii_data *mii; 1335 struct ifreq *ifr = (struct ifreq *)data; 1336 int drv_flags, flags; 1337 int mask, error, enabled; 1338 1339 error = 0; 1340 flags = ifp->if_flags; 1341 drv_flags = ifp->if_drv_flags; 1342 switch (cmd) { 1343 case SIOCSIFFLAGS: 1344 ATE_LOCK(sc); 1345 if ((flags & IFF_UP) != 0) { 1346 if ((drv_flags & IFF_DRV_RUNNING) != 0) { 1347 if (((flags ^ sc->if_flags) 1348 & (IFF_PROMISC | IFF_ALLMULTI)) != 0) 1349 ate_rxfilter(sc); 1350 } else { 1351 if ((sc->flags & ATE_FLAG_DETACHING) == 0) 1352 ateinit_locked(sc); 1353 } 1354 } else if ((drv_flags & IFF_DRV_RUNNING) != 0) { 1355 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1356 atestop(sc); 1357 } 1358 sc->if_flags = flags; 1359 ATE_UNLOCK(sc); 1360 break; 1361 1362 case SIOCADDMULTI: 1363 case SIOCDELMULTI: 1364 if ((drv_flags & IFF_DRV_RUNNING) != 0) { 1365 ATE_LOCK(sc); 1366 enabled = ate_setmcast(sc); 1367 if (enabled != (sc->flags & ATE_FLAG_MULTICAST)) 1368 ate_rxfilter(sc); 1369 ATE_UNLOCK(sc); 1370 } 1371 break; 1372 1373 case SIOCSIFMEDIA: 1374 case SIOCGIFMEDIA: 1375 mii = device_get_softc(sc->miibus); 1376 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 1377 break; 1378 case SIOCSIFCAP: 1379 mask = ifp->if_capenable ^ ifr->ifr_reqcap; 1380 if (mask & IFCAP_VLAN_MTU) { 1381 ATE_LOCK(sc); 1382 if (ifr->ifr_reqcap & IFCAP_VLAN_MTU) { 1383 WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) | ETH_CFG_BIG); 1384 ifp->if_capenable |= IFCAP_VLAN_MTU; 1385 } else { 1386 WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) & ~ETH_CFG_BIG); 1387 ifp->if_capenable &= ~IFCAP_VLAN_MTU; 1388 } 1389 ATE_UNLOCK(sc); 1390 } 1391 default: 1392 error = ether_ioctl(ifp, cmd, data); 1393 break; 1394 } 1395 return (error); 1396} 1397 1398static void 1399ate_child_detached(device_t dev, device_t child) 1400{ 1401 struct ate_softc *sc; 1402 1403 sc = device_get_softc(dev); 1404 if (child == sc->miibus) 1405 sc->miibus = NULL; 1406} 1407 1408/* 1409 * MII bus support routines. 1410 */ 1411static int 1412ate_miibus_readreg(device_t dev, int phy, int reg) 1413{ 1414 struct ate_softc *sc; 1415 int val; 1416 1417 /* 1418 * XXX if we implement agressive power savings, then we need 1419 * XXX to make sure that the clock to the emac is on here 1420 */ 1421 1422 sc = device_get_softc(dev); 1423 DELAY(1); /* Hangs w/o this delay really 30.5us atm */ 1424 WR4(sc, ETH_MAN, ETH_MAN_REG_RD(phy, reg)); 1425 while ((RD4(sc, ETH_SR) & ETH_SR_IDLE) == 0) 1426 continue; 1427 val = RD4(sc, ETH_MAN) & ETH_MAN_VALUE_MASK; 1428 1429 return (val); 1430} 1431 1432static int 1433ate_miibus_writereg(device_t dev, int phy, int reg, int data) 1434{ 1435 struct ate_softc *sc; 1436 1437 /* 1438 * XXX if we implement agressive power savings, then we need 1439 * XXX to make sure that the clock to the emac is on here 1440 */ 1441 1442 sc = device_get_softc(dev); 1443 WR4(sc, ETH_MAN, ETH_MAN_REG_WR(phy, reg, data)); 1444 while ((RD4(sc, ETH_SR) & ETH_SR_IDLE) == 0) 1445 continue; 1446 return (0); 1447} 1448 1449static device_method_t ate_methods[] = { 1450 /* Device interface */ 1451 DEVMETHOD(device_probe, ate_probe), 1452 DEVMETHOD(device_attach, ate_attach), 1453 DEVMETHOD(device_detach, ate_detach), 1454 1455 /* Bus interface */ 1456 DEVMETHOD(bus_child_detached, ate_child_detached), 1457 1458 /* MII interface */ 1459 DEVMETHOD(miibus_readreg, ate_miibus_readreg), 1460 DEVMETHOD(miibus_writereg, ate_miibus_writereg), 1461 1462 DEVMETHOD_END 1463}; 1464 1465static driver_t ate_driver = { 1466 "ate", 1467 ate_methods, 1468 sizeof(struct ate_softc), 1469}; 1470 1471#ifdef FDT 1472DRIVER_MODULE(ate, simplebus, ate_driver, ate_devclass, NULL, NULL); 1473#else 1474DRIVER_MODULE(ate, atmelarm, ate_driver, ate_devclass, NULL, NULL); 1475#endif 1476DRIVER_MODULE(miibus, ate, miibus_driver, miibus_devclass, NULL, NULL); 1477MODULE_DEPEND(ate, miibus, 1, 1, 1); 1478MODULE_DEPEND(ate, ether, 1, 1, 1); 1479