if_ate.c revision 257258
1/*- 2 * Copyright (c) 2006 M. Warner Losh. All rights reserved. 3 * Copyright (c) 2009 Greg Ansley. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27/* TODO 28 * 29 * 1) Turn on the clock in pmc? Turn off? 30 * 2) GPIO initializtion in board setup code. 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/arm/at91/if_ate.c 257258 2013-10-28 15:20:17Z ian $"); 35 36#include <sys/param.h> 37#include <sys/systm.h> 38#include <sys/bus.h> 39#include <sys/kernel.h> 40#include <sys/malloc.h> 41#include <sys/mbuf.h> 42#include <sys/module.h> 43#include <sys/rman.h> 44#include <sys/socket.h> 45#include <sys/sockio.h> 46#include <sys/sysctl.h> 47 48#include <machine/bus.h> 49 50#include <net/ethernet.h> 51#include <net/if.h> 52#include <net/if_arp.h> 53#include <net/if_dl.h> 54#include <net/if_media.h> 55#include <net/if_mib.h> 56#include <net/if_types.h> 57#include <net/if_var.h> 58 59#ifdef INET 60#include <netinet/in.h> 61#include <netinet/in_systm.h> 62#include <netinet/in_var.h> 63#include <netinet/ip.h> 64#endif 65 66#include <net/bpf.h> 67#include <net/bpfdesc.h> 68 69#include <dev/mii/mii.h> 70#include <dev/mii/miivar.h> 71 72#include "opt_at91.h" 73#include <arm/at91/at91reg.h> 74#include <arm/at91/at91var.h> 75#include <arm/at91/if_atereg.h> 76 77#include "miibus_if.h" 78 79/* 80 * Driver-specific flags. 81 */ 82#define ATE_FLAG_DETACHING 0x01 83#define ATE_FLAG_MULTICAST 0x02 84 85/* 86 * Old EMAC assumes whole packet fits in one buffer; 87 * new EBACB assumes all receive buffers are 128 bytes 88 */ 89#define RX_BUF_SIZE(sc) (sc->is_emacb ? 128 : MCLBYTES) 90 91/* 92 * EMACB has an 11 bit counter for Rx/Tx Descriptors 93 * for max total of 1024 decriptors each. 94 */ 95#define ATE_MAX_RX_DESCR 1024 96#define ATE_MAX_TX_DESCR 1024 97 98/* How many buffers to allocate */ 99#define ATE_MAX_TX_BUFFERS 4 /* We have ping-pong tx buffers */ 100 101/* How much memory to use for rx buffers */ 102#define ATE_RX_MEMORY (ATE_MAX_RX_DESCR * 128) 103 104/* Actual number of descriptors we allocate */ 105#define ATE_NUM_RX_DESCR ATE_MAX_RX_DESCR 106#define ATE_NUM_TX_DESCR ATE_MAX_TX_BUFFERS 107 108#if ATE_NUM_TX_DESCR > ATE_MAX_TX_DESCR 109#error "Can't have more TX buffers that descriptors" 110#endif 111#if ATE_NUM_RX_DESCR > ATE_MAX_RX_DESCR 112#error "Can't have more RX buffers that descriptors" 113#endif 114 115/* Wrap indexes the same way the hardware does */ 116#define NEXT_RX_IDX(sc, cur) \ 117 ((sc->rx_descs[cur].addr & ETH_WRAP_BIT) ? 0 : (cur + 1)) 118 119#define NEXT_TX_IDX(sc, cur) \ 120 ((sc->tx_descs[cur].status & ETHB_TX_WRAP) ? 0 : (cur + 1)) 121 122struct ate_softc 123{ 124 struct ifnet *ifp; /* ifnet pointer */ 125 struct mtx sc_mtx; /* Basically a perimeter lock */ 126 device_t dev; /* Myself */ 127 device_t miibus; /* My child miibus */ 128 struct resource *irq_res; /* IRQ resource */ 129 struct resource *mem_res; /* Memory resource */ 130 struct callout tick_ch; /* Tick callout */ 131 struct ifmib_iso_8802_3 mibdata; /* Stuff for network mgmt */ 132 bus_dma_tag_t mtag; /* bus dma tag for mbufs */ 133 bus_dma_tag_t rx_tag; 134 bus_dma_tag_t rx_desc_tag; 135 bus_dmamap_t rx_desc_map; 136 bus_dmamap_t rx_map[ATE_MAX_RX_DESCR]; 137 bus_addr_t rx_desc_phys; /* PA of rx descriptors */ 138 eth_rx_desc_t *rx_descs; /* VA of rx descriptors */ 139 void *rx_buf[ATE_NUM_RX_DESCR]; /* RX buffer space */ 140 int rxhead; /* Current RX map/desc index */ 141 uint32_t rx_buf_size; /* Size of Rx buffers */ 142 143 bus_dma_tag_t tx_desc_tag; 144 bus_dmamap_t tx_desc_map; 145 bus_dmamap_t tx_map[ATE_MAX_TX_BUFFERS]; 146 bus_addr_t tx_desc_phys; /* PA of tx descriptors */ 147 eth_tx_desc_t *tx_descs; /* VA of tx descriptors */ 148 int txhead; /* Current TX map/desc index */ 149 int txtail; /* Current TX map/desc index */ 150 struct mbuf *sent_mbuf[ATE_MAX_TX_BUFFERS]; /* Sent mbufs */ 151 void *intrhand; /* Interrupt handle */ 152 int flags; 153 int if_flags; 154 int use_rmii; 155 int is_emacb; /* SAM9x hardware version */ 156}; 157 158static inline uint32_t 159RD4(struct ate_softc *sc, bus_size_t off) 160{ 161 162 return (bus_read_4(sc->mem_res, off)); 163} 164 165static inline void 166WR4(struct ate_softc *sc, bus_size_t off, uint32_t val) 167{ 168 169 bus_write_4(sc->mem_res, off, val); 170} 171 172static inline void 173BARRIER(struct ate_softc *sc, bus_size_t off, bus_size_t len, int flags) 174{ 175 176 bus_barrier(sc->mem_res, off, len, flags); 177} 178 179#define ATE_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 180#define ATE_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 181#define ATE_LOCK_INIT(_sc) \ 182 mtx_init(&_sc->sc_mtx, device_get_nameunit(_sc->dev), \ 183 MTX_NETWORK_LOCK, MTX_DEF) 184#define ATE_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx); 185#define ATE_ASSERT_LOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_OWNED); 186#define ATE_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_NOTOWNED); 187 188static devclass_t ate_devclass; 189 190/* 191 * ifnet entry points. 192 */ 193static void ateinit_locked(void *); 194static void atestart_locked(struct ifnet *); 195 196static void ateinit(void *); 197static void atestart(struct ifnet *); 198static void atestop(struct ate_softc *); 199static int ateioctl(struct ifnet * ifp, u_long, caddr_t); 200 201/* 202 * Bus entry points. 203 */ 204static int ate_probe(device_t dev); 205static int ate_attach(device_t dev); 206static int ate_detach(device_t dev); 207static void ate_intr(void *); 208 209/* 210 * Helper routines. 211 */ 212static int ate_activate(device_t dev); 213static void ate_deactivate(struct ate_softc *sc); 214static int ate_ifmedia_upd(struct ifnet *ifp); 215static void ate_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr); 216static int ate_get_mac(struct ate_softc *sc, u_char *eaddr); 217static void ate_set_mac(struct ate_softc *sc, u_char *eaddr); 218static void ate_rxfilter(struct ate_softc *sc); 219 220static int ate_miibus_readreg(device_t dev, int phy, int reg); 221 222static int ate_miibus_writereg(device_t dev, int phy, int reg, int data); 223/* 224 * The AT91 family of products has the ethernet interface called EMAC. 225 * However, it isn't self identifying. It is anticipated that the parent bus 226 * code will take care to only add ate devices where they really are. As 227 * such, we do nothing here to identify the device and just set its name. 228 */ 229static int 230ate_probe(device_t dev) 231{ 232 233 device_set_desc(dev, "EMAC"); 234 return (0); 235} 236 237static int 238ate_attach(device_t dev) 239{ 240 struct ate_softc *sc; 241 struct ifnet *ifp = NULL; 242 struct sysctl_ctx_list *sctx; 243 struct sysctl_oid *soid; 244 u_char eaddr[ETHER_ADDR_LEN]; 245 uint32_t rnd; 246 int rid, err; 247 248 sc = device_get_softc(dev); 249 sc->dev = dev; 250 ATE_LOCK_INIT(sc); 251 252 rid = 0; 253 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 254 RF_ACTIVE); 255 if (sc->mem_res == NULL) { 256 device_printf(dev, "could not allocate memory resources.\n"); 257 err = ENOMEM; 258 goto out; 259 } 260 rid = 0; 261 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 262 RF_ACTIVE); 263 if (sc->irq_res == NULL) { 264 device_printf(dev, "could not allocate interrupt resources.\n"); 265 err = ENOMEM; 266 goto out; 267 } 268 269 /* New or old version, chooses buffer size. */ 270 sc->is_emacb = at91_is_sam9() || at91_is_sam9xe(); 271 sc->rx_buf_size = RX_BUF_SIZE(sc); 272 273 err = ate_activate(dev); 274 if (err) 275 goto out; 276 277 /* Default to what boot rom did */ 278 if (!sc->is_emacb) 279 sc->use_rmii = 280 (RD4(sc, ETH_CFG) & ETH_CFG_RMII) == ETH_CFG_RMII; 281 else 282 sc->use_rmii = 283 (RD4(sc, ETHB_UIO) & ETHB_UIO_RMII) == ETHB_UIO_RMII; 284 285#ifdef AT91_ATE_USE_RMII 286 /* Compile time override */ 287 sc->use_rmii = 1; 288#endif 289 /* Sysctls */ 290 sctx = device_get_sysctl_ctx(dev); 291 soid = device_get_sysctl_tree(dev); 292 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "rmii", 293 CTLFLAG_RW, &sc->use_rmii, 0, "rmii in use"); 294 295 /* Calling atestop before ifp is set is OK. */ 296 ATE_LOCK(sc); 297 atestop(sc); 298 ATE_UNLOCK(sc); 299 callout_init_mtx(&sc->tick_ch, &sc->sc_mtx, 0); 300 301 if ((err = ate_get_mac(sc, eaddr)) != 0) { 302 /* No MAC address configured. Generate the random one. */ 303 if (bootverbose) 304 device_printf(dev, 305 "Generating random ethernet address.\n"); 306 rnd = arc4random(); 307 308 /* 309 * Set OUI to convenient locally assigned address. 'b' 310 * is 0x62, which has the locally assigned bit set, and 311 * the broadcast/multicast bit clear. 312 */ 313 eaddr[0] = 'b'; 314 eaddr[1] = 's'; 315 eaddr[2] = 'd'; 316 eaddr[3] = (rnd >> 16) & 0xff; 317 eaddr[4] = (rnd >> 8) & 0xff; 318 eaddr[5] = (rnd >> 0) & 0xff; 319 } 320 321 sc->ifp = ifp = if_alloc(IFT_ETHER); 322 err = mii_attach(dev, &sc->miibus, ifp, ate_ifmedia_upd, 323 ate_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0); 324 if (err != 0) { 325 device_printf(dev, "attaching PHYs failed\n"); 326 goto out; 327 } 328 /* 329 * XXX: Clear the isolate bit, or we won't get up, 330 * at least on the HL201 331 */ 332 ate_miibus_writereg(dev, 0, 0, 0x3000); 333 334 ifp->if_softc = sc; 335 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 336 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 337 ifp->if_capabilities |= IFCAP_VLAN_MTU; 338 ifp->if_capenable |= IFCAP_VLAN_MTU; /* The hw bits already set. */ 339 ifp->if_start = atestart; 340 ifp->if_ioctl = ateioctl; 341 ifp->if_init = ateinit; 342 ifp->if_baudrate = 10000000; 343 IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN); 344 ifp->if_snd.ifq_drv_maxlen = IFQ_MAXLEN; 345 IFQ_SET_READY(&ifp->if_snd); 346 ifp->if_linkmib = &sc->mibdata; 347 ifp->if_linkmiblen = sizeof(sc->mibdata); 348 sc->mibdata.dot3Compliance = DOT3COMPLIANCE_COLLS; 349 sc->if_flags = ifp->if_flags; 350 351 ether_ifattach(ifp, eaddr); 352 353 /* Activate the interrupt. */ 354 err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_NET | INTR_MPSAFE, 355 NULL, ate_intr, sc, &sc->intrhand); 356 if (err) { 357 device_printf(dev, "could not establish interrupt handler.\n"); 358 ether_ifdetach(ifp); 359 goto out; 360 } 361 362out: 363 if (err) 364 ate_detach(dev); 365 return (err); 366} 367 368static int 369ate_detach(device_t dev) 370{ 371 struct ate_softc *sc; 372 struct ifnet *ifp; 373 374 sc = device_get_softc(dev); 375 KASSERT(sc != NULL, ("[ate: %d]: sc is NULL", __LINE__)); 376 ifp = sc->ifp; 377 if (device_is_attached(dev)) { 378 ATE_LOCK(sc); 379 sc->flags |= ATE_FLAG_DETACHING; 380 atestop(sc); 381 ATE_UNLOCK(sc); 382 callout_drain(&sc->tick_ch); 383 ether_ifdetach(ifp); 384 } 385 if (sc->miibus != NULL) { 386 device_delete_child(dev, sc->miibus); 387 sc->miibus = NULL; 388 } 389 bus_generic_detach(sc->dev); 390 ate_deactivate(sc); 391 if (sc->intrhand != NULL) { 392 bus_teardown_intr(dev, sc->irq_res, sc->intrhand); 393 sc->intrhand = NULL; 394 } 395 if (ifp != NULL) { 396 if_free(ifp); 397 sc->ifp = NULL; 398 } 399 if (sc->mem_res != NULL) { 400 bus_release_resource(dev, SYS_RES_IOPORT, 401 rman_get_rid(sc->mem_res), sc->mem_res); 402 sc->mem_res = NULL; 403 } 404 if (sc->irq_res != NULL) { 405 bus_release_resource(dev, SYS_RES_IRQ, 406 rman_get_rid(sc->irq_res), sc->irq_res); 407 sc->irq_res = NULL; 408 } 409 ATE_LOCK_DESTROY(sc); 410 return (0); 411} 412 413static void 414ate_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 415{ 416 417 if (error != 0) 418 return; 419 *(bus_addr_t *)arg = segs[0].ds_addr; 420} 421 422static void 423ate_load_rx_buf(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 424{ 425 struct ate_softc *sc; 426 427 if (error != 0) 428 return; 429 sc = (struct ate_softc *)arg; 430 431 bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, BUS_DMASYNC_PREWRITE); 432 sc->rx_descs[sc->rxhead].addr = segs[0].ds_addr; 433 sc->rx_descs[sc->rxhead].status = 0; 434 bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, BUS_DMASYNC_POSTWRITE); 435} 436 437static uint32_t 438ate_mac_hash(const uint8_t *buf) 439{ 440 uint32_t index = 0; 441 for (int i = 0; i < 48; i++) { 442 index ^= ((buf[i >> 3] >> (i & 7)) & 1) << (i % 6); 443 } 444 return (index); 445} 446 447/* 448 * Compute the multicast filter for this device. 449 */ 450static int 451ate_setmcast(struct ate_softc *sc) 452{ 453 uint32_t index; 454 uint32_t mcaf[2]; 455 u_char *af = (u_char *) mcaf; 456 struct ifmultiaddr *ifma; 457 struct ifnet *ifp; 458 459 ifp = sc->ifp; 460 461 if ((ifp->if_flags & IFF_PROMISC) != 0) 462 return (0); 463 if ((ifp->if_flags & IFF_ALLMULTI) != 0) { 464 WR4(sc, ETH_HSL, 0xffffffff); 465 WR4(sc, ETH_HSH, 0xffffffff); 466 return (1); 467 } 468 469 /* Compute the multicast hash. */ 470 mcaf[0] = 0; 471 mcaf[1] = 0; 472 if_maddr_rlock(ifp); 473 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 474 if (ifma->ifma_addr->sa_family != AF_LINK) 475 continue; 476 index = ate_mac_hash(LLADDR((struct sockaddr_dl *) 477 ifma->ifma_addr)); 478 af[index >> 3] |= 1 << (index & 7); 479 } 480 if_maddr_runlock(ifp); 481 482 /* 483 * Write the hash to the hash register. This card can also 484 * accept unicast packets as well as multicast packets using this 485 * register for easier bridging operations, but we don't take 486 * advantage of that. Locks here are to avoid LOR with the 487 * if_maddr_rlock, but might not be strictly necessary. 488 */ 489 WR4(sc, ETH_HSL, mcaf[0]); 490 WR4(sc, ETH_HSH, mcaf[1]); 491 return (mcaf[0] || mcaf[1]); 492} 493 494static int 495ate_activate(device_t dev) 496{ 497 struct ate_softc *sc; 498 int i; 499 500 sc = device_get_softc(dev); 501 502 /* Allocate DMA tags and maps for TX mbufs */ 503 if (bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0, 504 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 505 1, MCLBYTES, 0, busdma_lock_mutex, &sc->sc_mtx, &sc->mtag)) 506 goto errout; 507 for (i = 0; i < ATE_MAX_TX_BUFFERS; i++) { 508 if ( bus_dmamap_create(sc->mtag, 0, &sc->tx_map[i])) 509 goto errout; 510 } 511 512 513 /* DMA tag and map for the RX descriptors. */ 514 if (bus_dma_tag_create(bus_get_dma_tag(dev), sizeof(eth_rx_desc_t), 515 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 516 ATE_NUM_RX_DESCR * sizeof(eth_rx_desc_t), 1, 517 ATE_NUM_RX_DESCR * sizeof(eth_rx_desc_t), 0, busdma_lock_mutex, 518 &sc->sc_mtx, &sc->rx_desc_tag)) 519 goto errout; 520 if (bus_dmamem_alloc(sc->rx_desc_tag, (void **)&sc->rx_descs, 521 BUS_DMA_NOWAIT | BUS_DMA_COHERENT, &sc->rx_desc_map) != 0) 522 goto errout; 523 if (bus_dmamap_load(sc->rx_desc_tag, sc->rx_desc_map, 524 sc->rx_descs, ATE_NUM_RX_DESCR * sizeof(eth_rx_desc_t), 525 ate_getaddr, &sc->rx_desc_phys, 0) != 0) 526 goto errout; 527 528 /* Allocate DMA tags and maps for RX. buffers */ 529 if (bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0, 530 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 531 sc->rx_buf_size, 1, sc->rx_buf_size, 0, 532 busdma_lock_mutex, &sc->sc_mtx, &sc->rx_tag)) 533 goto errout; 534 535 /* 536 * Allocate our RX buffers. 537 * This chip has a RX structure that's filled in. 538 * XXX On MACB (SAM9 part) we should receive directly into mbuf 539 * to avoid the copy. XXX 540 */ 541 sc->rxhead = 0; 542 for (sc->rxhead = 0; sc->rxhead < ATE_RX_MEMORY/sc->rx_buf_size; 543 sc->rxhead++) { 544 if (bus_dmamem_alloc(sc->rx_tag, 545 (void **)&sc->rx_buf[sc->rxhead], BUS_DMA_NOWAIT, 546 &sc->rx_map[sc->rxhead]) != 0) 547 goto errout; 548 549 if (bus_dmamap_load(sc->rx_tag, sc->rx_map[sc->rxhead], 550 sc->rx_buf[sc->rxhead], sc->rx_buf_size, 551 ate_load_rx_buf, sc, 0) != 0) { 552 printf("bus_dmamem_load\n"); 553 goto errout; 554 } 555 bus_dmamap_sync(sc->rx_tag, sc->rx_map[sc->rxhead], BUS_DMASYNC_PREREAD); 556 } 557 558 /* 559 * For the last buffer, set the wrap bit so the controller 560 * restarts from the first descriptor. 561 */ 562 sc->rx_descs[--sc->rxhead].addr |= ETH_WRAP_BIT; 563 sc->rxhead = 0; 564 565 /* Flush the memory for the EMAC rx descriptor. */ 566 bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, BUS_DMASYNC_PREWRITE); 567 568 /* Write the descriptor queue address. */ 569 WR4(sc, ETH_RBQP, sc->rx_desc_phys); 570 571 /* 572 * DMA tag and map for the TX descriptors. 573 */ 574 if (bus_dma_tag_create(bus_get_dma_tag(dev), sizeof(eth_tx_desc_t), 575 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 576 ATE_MAX_TX_BUFFERS * sizeof(eth_tx_desc_t), 1, 577 ATE_MAX_TX_BUFFERS * sizeof(eth_tx_desc_t), 0, busdma_lock_mutex, 578 &sc->sc_mtx, &sc->tx_desc_tag) != 0) 579 goto errout; 580 581 if (bus_dmamem_alloc(sc->tx_desc_tag, (void **)&sc->tx_descs, 582 BUS_DMA_NOWAIT | BUS_DMA_COHERENT, &sc->tx_desc_map) != 0) 583 goto errout; 584 585 if (bus_dmamap_load(sc->tx_desc_tag, sc->tx_desc_map, 586 sc->tx_descs, ATE_MAX_TX_BUFFERS * sizeof(eth_tx_desc_t), 587 ate_getaddr, &sc->tx_desc_phys, 0) != 0) 588 goto errout; 589 590 /* Initilize descriptors; mark all empty */ 591 for (i = 0; i < ATE_MAX_TX_BUFFERS; i++) { 592 sc->tx_descs[i].addr =0; 593 sc->tx_descs[i].status = ETHB_TX_USED; 594 sc->sent_mbuf[i] = NULL; 595 } 596 597 /* Mark last entry to cause wrap when indexing through */ 598 sc->tx_descs[ATE_MAX_TX_BUFFERS - 1].status = 599 ETHB_TX_WRAP | ETHB_TX_USED; 600 601 /* Flush the memory for the EMAC tx descriptor. */ 602 bus_dmamap_sync(sc->tx_desc_tag, sc->tx_desc_map, BUS_DMASYNC_PREWRITE); 603 604 sc->txhead = sc->txtail = 0; 605 if (sc->is_emacb) { 606 /* Write the descriptor queue address. */ 607 WR4(sc, ETHB_TBQP, sc->tx_desc_phys); 608 609 /* EMACB: Enable transceiver input clock */ 610 WR4(sc, ETHB_UIO, RD4(sc, ETHB_UIO) | ETHB_UIO_CLKE); 611 } 612 613 return (0); 614 615errout: 616 return (ENOMEM); 617} 618 619static void 620ate_deactivate(struct ate_softc *sc) 621{ 622 int i; 623 624 KASSERT(sc != NULL, ("[ate, %d]: sc is NULL!", __LINE__)); 625 if (sc->mtag != NULL) { 626 for (i = 0; i < ATE_MAX_TX_BUFFERS; i++) { 627 if (sc->sent_mbuf[i] != NULL) { 628 bus_dmamap_sync(sc->mtag, sc->tx_map[i], 629 BUS_DMASYNC_POSTWRITE); 630 bus_dmamap_unload(sc->mtag, sc->tx_map[i]); 631 m_freem(sc->sent_mbuf[i]); 632 } 633 bus_dmamap_destroy(sc->mtag, sc->tx_map[i]); 634 sc->sent_mbuf[i] = NULL; 635 sc->tx_map[i] = NULL; 636 } 637 bus_dma_tag_destroy(sc->mtag); 638 } 639 if (sc->rx_desc_tag != NULL) { 640 if (sc->rx_descs != NULL) { 641 if (sc->rx_desc_phys != 0) { 642 bus_dmamap_sync(sc->rx_desc_tag, 643 sc->rx_desc_map, BUS_DMASYNC_POSTREAD); 644 bus_dmamap_unload(sc->rx_desc_tag, 645 sc->rx_desc_map); 646 sc->rx_desc_phys = 0; 647 } 648 } 649 } 650 if (sc->rx_tag != NULL) { 651 for (i = 0; sc->rx_buf[i] != NULL; i++) { 652 if (sc->rx_descs[i].addr != 0) { 653 bus_dmamap_sync(sc->rx_tag, 654 sc->rx_map[i], 655 BUS_DMASYNC_POSTREAD); 656 bus_dmamap_unload(sc->rx_tag, 657 sc->rx_map[i]); 658 sc->rx_descs[i].addr = 0; 659 } 660 bus_dmamem_free(sc->rx_tag, sc->rx_buf[i], 661 sc->rx_map[i]); 662 sc->rx_buf[i] = NULL; 663 sc->rx_map[i] = NULL; 664 } 665 bus_dma_tag_destroy(sc->rx_tag); 666 } 667 if (sc->rx_desc_tag != NULL) { 668 if (sc->rx_descs != NULL) 669 bus_dmamem_free(sc->rx_desc_tag, sc->rx_descs, 670 sc->rx_desc_map); 671 bus_dma_tag_destroy(sc->rx_desc_tag); 672 sc->rx_descs = NULL; 673 sc->rx_desc_tag = NULL; 674 } 675 676 if (sc->is_emacb) 677 WR4(sc, ETHB_UIO, RD4(sc, ETHB_UIO) & ~ETHB_UIO_CLKE); 678} 679 680/* 681 * Change media according to request. 682 */ 683static int 684ate_ifmedia_upd(struct ifnet *ifp) 685{ 686 struct ate_softc *sc = ifp->if_softc; 687 struct mii_data *mii; 688 689 mii = device_get_softc(sc->miibus); 690 ATE_LOCK(sc); 691 mii_mediachg(mii); 692 ATE_UNLOCK(sc); 693 return (0); 694} 695 696/* 697 * Notify the world which media we're using. 698 */ 699static void 700ate_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 701{ 702 struct ate_softc *sc = ifp->if_softc; 703 struct mii_data *mii; 704 705 mii = device_get_softc(sc->miibus); 706 ATE_LOCK(sc); 707 mii_pollstat(mii); 708 ifmr->ifm_active = mii->mii_media_active; 709 ifmr->ifm_status = mii->mii_media_status; 710 ATE_UNLOCK(sc); 711} 712 713static void 714ate_stat_update(struct ate_softc *sc, int active) 715{ 716 uint32_t reg; 717 718 /* 719 * The speed and full/half-duplex state needs to be reflected 720 * in the ETH_CFG register. 721 */ 722 reg = RD4(sc, ETH_CFG); 723 reg &= ~(ETH_CFG_SPD | ETH_CFG_FD); 724 if (IFM_SUBTYPE(active) != IFM_10_T) 725 reg |= ETH_CFG_SPD; 726 if (active & IFM_FDX) 727 reg |= ETH_CFG_FD; 728 WR4(sc, ETH_CFG, reg); 729} 730 731static void 732ate_tick(void *xsc) 733{ 734 struct ate_softc *sc = xsc; 735 struct ifnet *ifp = sc->ifp; 736 struct mii_data *mii; 737 int active; 738 uint32_t c; 739 740 /* 741 * The KB920x boot loader tests ETH_SR & ETH_SR_LINK and will ask 742 * the MII if there's a link if this bit is clear. Not sure if we 743 * should do the same thing here or not. 744 */ 745 ATE_ASSERT_LOCKED(sc); 746 if (sc->miibus != NULL) { 747 mii = device_get_softc(sc->miibus); 748 active = mii->mii_media_active; 749 mii_tick(mii); 750 if (mii->mii_media_status & IFM_ACTIVE && 751 active != mii->mii_media_active) 752 ate_stat_update(sc, mii->mii_media_active); 753 } 754 755 /* 756 * Update the stats as best we can. When we're done, clear 757 * the status counters and start over. We're supposed to read these 758 * registers often enough that they won't overflow. Hopefully 759 * once a second is often enough. Some don't map well to 760 * the dot3Stats mib, so for those we just count them as general 761 * errors. Stats for iframes, ibutes, oframes and obytes are 762 * collected elsewhere. These registers zero on a read to prevent 763 * races. For all the collision stats, also update the collision 764 * stats for the interface. 765 */ 766 sc->mibdata.dot3StatsAlignmentErrors += RD4(sc, ETH_ALE); 767 sc->mibdata.dot3StatsFCSErrors += RD4(sc, ETH_SEQE); 768 c = RD4(sc, ETH_SCOL); 769 ifp->if_collisions += c; 770 sc->mibdata.dot3StatsSingleCollisionFrames += c; 771 c = RD4(sc, ETH_MCOL); 772 sc->mibdata.dot3StatsMultipleCollisionFrames += c; 773 ifp->if_collisions += c; 774 sc->mibdata.dot3StatsSQETestErrors += RD4(sc, ETH_SQEE); 775 sc->mibdata.dot3StatsDeferredTransmissions += RD4(sc, ETH_DTE); 776 c = RD4(sc, ETH_LCOL); 777 sc->mibdata.dot3StatsLateCollisions += c; 778 ifp->if_collisions += c; 779 c = RD4(sc, ETH_ECOL); 780 sc->mibdata.dot3StatsExcessiveCollisions += c; 781 ifp->if_collisions += c; 782 sc->mibdata.dot3StatsCarrierSenseErrors += RD4(sc, ETH_CSE); 783 sc->mibdata.dot3StatsFrameTooLongs += RD4(sc, ETH_ELR); 784 sc->mibdata.dot3StatsInternalMacReceiveErrors += RD4(sc, ETH_DRFC); 785 786 /* 787 * Not sure where to lump these, so count them against the errors 788 * for the interface. 789 */ 790 sc->ifp->if_oerrors += RD4(sc, ETH_TUE); 791 sc->ifp->if_ierrors += RD4(sc, ETH_CDE) + RD4(sc, ETH_RJB) + 792 RD4(sc, ETH_USF); 793 794 /* Schedule another timeout one second from now. */ 795 callout_reset(&sc->tick_ch, hz, ate_tick, sc); 796} 797 798static void 799ate_set_mac(struct ate_softc *sc, u_char *eaddr) 800{ 801 802 WR4(sc, ETH_SA1L, (eaddr[3] << 24) | (eaddr[2] << 16) | 803 (eaddr[1] << 8) | eaddr[0]); 804 WR4(sc, ETH_SA1H, (eaddr[5] << 8) | (eaddr[4])); 805} 806 807static int 808ate_get_mac(struct ate_softc *sc, u_char *eaddr) 809{ 810 bus_size_t sa_low_reg[] = { ETH_SA1L, ETH_SA2L, ETH_SA3L, ETH_SA4L }; 811 bus_size_t sa_high_reg[] = { ETH_SA1H, ETH_SA2H, ETH_SA3H, ETH_SA4H }; 812 uint32_t low, high; 813 int i; 814 815 /* 816 * The boot loader may setup the MAC with an address(es), grab the 817 * first MAC address from the SA[1-4][HL] registers. 818 */ 819 for (i = 0; i < 4; i++) { 820 low = RD4(sc, sa_low_reg[i]); 821 high = RD4(sc, sa_high_reg[i]); 822 if ((low | (high & 0xffff)) != 0) { 823 eaddr[0] = low & 0xff; 824 eaddr[1] = (low >> 8) & 0xff; 825 eaddr[2] = (low >> 16) & 0xff; 826 eaddr[3] = (low >> 24) & 0xff; 827 eaddr[4] = high & 0xff; 828 eaddr[5] = (high >> 8) & 0xff; 829 return (0); 830 } 831 } 832 return (ENXIO); 833} 834 835static void 836ate_intr(void *xsc) 837{ 838 struct ate_softc *sc = xsc; 839 struct ifnet *ifp = sc->ifp; 840 struct mbuf *mb; 841 eth_rx_desc_t *rxdhead; 842 uint32_t status, reg, idx; 843 int remain, count, done; 844 845 status = RD4(sc, ETH_ISR); 846 if (status == 0) 847 return; 848 849 if (status & ETH_ISR_RCOM) { 850 bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, 851 BUS_DMASYNC_POSTREAD); 852 853 rxdhead = &sc->rx_descs[sc->rxhead]; 854 while (rxdhead->addr & ETH_CPU_OWNER) { 855 if (!sc->is_emacb) { 856 /* 857 * Simulate SAM9 FIRST/LAST bits for RM9200. 858 * RM9200 EMAC has only on Rx buffer per packet. 859 * But sometime we are handed a zero lenght packet. 860 */ 861 if ((rxdhead->status & ETH_LEN_MASK) == 0) 862 rxdhead->status = 0; /* Mark error */ 863 else 864 rxdhead->status |= ETH_BUF_FIRST | ETH_BUF_LAST; 865 } 866 867 if ((rxdhead->status & ETH_BUF_FIRST) == 0) { 868 /* Something went wrong during RX so 869 release back to EMAC all buffers of invalid packets. 870 */ 871 rxdhead->status = 0; 872 rxdhead->addr &= ~ETH_CPU_OWNER; 873 sc->rxhead = NEXT_RX_IDX(sc, sc->rxhead); 874 rxdhead = &sc->rx_descs[sc->rxhead]; 875 continue; 876 } 877 878 /* Find end of packet or start of next */ 879 idx = sc->rxhead; 880 if ((sc->rx_descs[idx].status & ETH_BUF_LAST) == 0) { 881 idx = NEXT_RX_IDX(sc, idx); 882 883 while ((sc->rx_descs[idx].addr & ETH_CPU_OWNER) && 884 ((sc->rx_descs[idx].status & 885 (ETH_BUF_FIRST|ETH_BUF_LAST))== 0)) 886 idx = NEXT_RX_IDX(sc, idx); 887 } 888 889 /* Packet NOT yet completely in memory; we are done */ 890 if ((sc->rx_descs[idx].addr & ETH_CPU_OWNER) == 0 || 891 ((sc->rx_descs[idx].status & (ETH_BUF_FIRST|ETH_BUF_LAST))== 0)) 892 break; 893 894 /* Packets with no end descriptor are invalid. */ 895 if ((sc->rx_descs[idx].status & ETH_BUF_LAST) == 0) { 896 rxdhead->status &= ~ETH_BUF_FIRST; 897 continue; 898 } 899 900 /* FCS is not coppied into mbuf. */ 901 remain = (sc->rx_descs[idx].status & ETH_LEN_MASK) - 4; 902 903 /* Get an appropriately sized mbuf. */ 904 mb = m_get2(remain + ETHER_ALIGN, M_NOWAIT, MT_DATA, 905 M_PKTHDR); 906 if (mb == NULL) { 907 sc->ifp->if_iqdrops++; 908 rxdhead->status = 0; 909 continue; 910 } 911 mb->m_data += ETHER_ALIGN; 912 mb->m_pkthdr.rcvif = ifp; 913 914 WR4(sc, ETH_RSR, RD4(sc, ETH_RSR)); /* Reset status */ 915 916 /* Now we process the buffers that make up the packet */ 917 do { 918 919 /* Last buffer may just be 1-4 bytes of FCS so remain 920 * may be zero for last decriptor. */ 921 if (remain > 0) { 922 /* Make sure we get the current bytes */ 923 bus_dmamap_sync(sc->rx_tag, sc->rx_map[sc->rxhead], 924 BUS_DMASYNC_POSTREAD); 925 926 count = MIN(remain, sc->rx_buf_size); 927 928 /* XXX Performance robbing copy. Could 929 * recieve directly to mbufs if not an 930 * RM9200. And even then we could likely 931 * copy just the protocol headers. XXX */ 932 m_append(mb, count, sc->rx_buf[sc->rxhead]); 933 remain -= count; 934 } 935 936 done = (rxdhead->status & ETH_BUF_LAST) != 0; 937 938 /* Return the descriptor to the EMAC */ 939 rxdhead->status = 0; 940 rxdhead->addr &= ~ETH_CPU_OWNER; 941 bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, 942 BUS_DMASYNC_PREWRITE); 943 944 /* Move on to next descriptor with wrap */ 945 sc->rxhead = NEXT_RX_IDX(sc, sc->rxhead); 946 rxdhead = &sc->rx_descs[sc->rxhead]; 947 948 } while (!done); 949 950 if (mb != NULL) { 951 ifp->if_ipackets++; 952 (*ifp->if_input)(ifp, mb); 953 } 954 } 955 } 956 957 958 if (status & ETH_ISR_TCOM) { 959 bus_dmamap_sync(sc->tx_desc_tag, sc->tx_desc_map, 960 BUS_DMASYNC_POSTREAD); 961 962 ATE_LOCK(sc); 963 /* XXX TSR register should be cleared */ 964 if (!sc->is_emacb) { 965 /* Simulate Transmit descriptor table */ 966 967 /* First packet done */ 968 if (sc->txtail < sc->txhead) 969 sc->tx_descs[sc->txtail].status |= ETHB_TX_USED; 970 971 /* Second Packet done */ 972 if (sc->txtail + 1 < sc->txhead && 973 RD4(sc, ETH_TSR) & ETH_TSR_IDLE) 974 sc->tx_descs[sc->txtail + 1].status |= ETHB_TX_USED; 975 } 976 977 while (sc->txtail != sc->txhead && 978 sc->tx_descs[sc->txtail].status & ETHB_TX_USED ) { 979 980 bus_dmamap_sync(sc->mtag, sc->tx_map[sc->txtail], 981 BUS_DMASYNC_POSTWRITE); 982 bus_dmamap_unload(sc->mtag, sc->tx_map[sc->txtail]); 983 m_freem(sc->sent_mbuf[sc->txtail]); 984 sc->tx_descs[sc->txtail].addr = 0; 985 sc->sent_mbuf[sc->txtail] = NULL; 986 987 ifp->if_opackets++; 988 sc->txtail = NEXT_TX_IDX(sc, sc->txtail); 989 } 990 991 /* Flush descriptors to EMAC */ 992 bus_dmamap_sync(sc->tx_desc_tag, sc->tx_desc_map, BUS_DMASYNC_PREWRITE); 993 994 /* 995 * We're no longer busy, so clear the busy flag and call the 996 * start routine to xmit more packets. 997 */ 998 sc->ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 999 atestart_locked(sc->ifp); 1000 ATE_UNLOCK(sc); 1001 } 1002 1003 if (status & ETH_ISR_RBNA) { 1004 /* Workaround RM9200 Errata #11 */ 1005 if (bootverbose) 1006 device_printf(sc->dev, "RBNA workaround\n"); 1007 reg = RD4(sc, ETH_CTL); 1008 WR4(sc, ETH_CTL, reg & ~ETH_CTL_RE); 1009 BARRIER(sc, ETH_CTL, 4, BUS_SPACE_BARRIER_WRITE); 1010 WR4(sc, ETH_CTL, reg | ETH_CTL_RE); 1011 } 1012 1013 /* XXX need to work around SAM9260 errata 43.2.4.1: 1014 * disable the mac, reset tx buffer, enable mac on TUND */ 1015} 1016 1017/* 1018 * Reset and initialize the chip. 1019 */ 1020static void 1021ateinit_locked(void *xsc) 1022{ 1023 struct ate_softc *sc = xsc; 1024 struct ifnet *ifp = sc->ifp; 1025 struct mii_data *mii; 1026 uint8_t eaddr[ETHER_ADDR_LEN]; 1027 uint32_t reg; 1028 1029 ATE_ASSERT_LOCKED(sc); 1030 1031 /* 1032 * XXX TODO(3) 1033 * we need to turn on the EMAC clock in the pmc. With the 1034 * default boot loader, this is already turned on. However, we 1035 * need to think about how best to turn it on/off as the interface 1036 * is brought up/down, as well as dealing with the mii bus... 1037 * 1038 * We also need to multiplex the pins correctly (in board_xxx.c). 1039 */ 1040 1041 /* 1042 * There are two different ways that the mii bus is connected 1043 * to this chip mii or rmii. 1044 */ 1045 if (!sc->is_emacb) { 1046 /* RM9200 */ 1047 reg = RD4(sc, ETH_CFG); 1048 if (sc->use_rmii) 1049 reg |= ETH_CFG_RMII; 1050 else 1051 reg &= ~ETH_CFG_RMII; 1052 WR4(sc, ETH_CFG, reg); 1053 } else { 1054 /* SAM9 */ 1055 reg = ETHB_UIO_CLKE; 1056 reg |= (sc->use_rmii) ? ETHB_UIO_RMII : 0; 1057 WR4(sc, ETHB_UIO, reg); 1058 } 1059 1060 ate_rxfilter(sc); 1061 1062 /* 1063 * Set the chip MAC address. 1064 */ 1065 bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN); 1066 ate_set_mac(sc, eaddr); 1067 1068 /* Make sure we know state of TX queue */ 1069 sc->txhead = sc->txtail = 0; 1070 if (sc->is_emacb) { 1071 /* Write the descriptor queue address. */ 1072 WR4(sc, ETHB_TBQP, sc->tx_desc_phys); 1073 } 1074 1075 /* 1076 * Turn on MACs and interrupt processing. 1077 */ 1078 WR4(sc, ETH_CTL, RD4(sc, ETH_CTL) | ETH_CTL_TE | ETH_CTL_RE); 1079 WR4(sc, ETH_IER, ETH_ISR_RCOM | ETH_ISR_TCOM | ETH_ISR_RBNA); 1080 1081 /* Enable big packets. */ 1082 WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) | ETH_CFG_BIG); 1083 1084 /* 1085 * Set 'running' flag, and clear output active flag 1086 * and attempt to start the output. 1087 */ 1088 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1089 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1090 1091 mii = device_get_softc(sc->miibus); 1092 mii_pollstat(mii); 1093 ate_stat_update(sc, mii->mii_media_active); 1094 atestart_locked(ifp); 1095 1096 callout_reset(&sc->tick_ch, hz, ate_tick, sc); 1097} 1098 1099/* 1100 * Dequeue packets and transmit. 1101 */ 1102static void 1103atestart_locked(struct ifnet *ifp) 1104{ 1105 struct ate_softc *sc = ifp->if_softc; 1106 struct mbuf *m, *mdefrag; 1107 bus_dma_segment_t segs[1]; 1108 int nseg, e; 1109 1110 ATE_ASSERT_LOCKED(sc); 1111 if (ifp->if_drv_flags & IFF_DRV_OACTIVE) 1112 return; 1113 1114 while (sc->tx_descs[sc->txhead].status & ETHB_TX_USED) { 1115 /* 1116 * Check to see if there's room to put another packet into the 1117 * xmit queue. The old EMAC version has a ping-pong buffer for 1118 * xmit packets. We use OACTIVE to indicate "we can stuff more 1119 * into our buffers (clear) or not (set)." 1120 */ 1121 if (!sc->is_emacb) { 1122 /* RM9200 has only two hardware entries */ 1123 if (!sc->is_emacb && (RD4(sc, ETH_TSR) & ETH_TSR_BNQ) == 0) { 1124 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1125 return; 1126 } 1127 } 1128 1129 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 1130 if (m == 0) 1131 break; 1132 1133 e = bus_dmamap_load_mbuf_sg(sc->mtag, sc->tx_map[sc->txhead], m, 1134 segs, &nseg, 0); 1135 if (e == EFBIG) { 1136 mdefrag = m_defrag(m, M_NOWAIT); 1137 if (mdefrag == NULL) { 1138 IFQ_DRV_PREPEND(&ifp->if_snd, m); 1139 return; 1140 } 1141 m = mdefrag; 1142 e = bus_dmamap_load_mbuf_sg(sc->mtag, 1143 sc->tx_map[sc->txhead], m, segs, &nseg, 0); 1144 } 1145 if (e != 0) { 1146 m_freem(m); 1147 continue; 1148 } 1149 sc->sent_mbuf[sc->txhead] = m; 1150 1151 bus_dmamap_sync(sc->mtag, sc->tx_map[sc->txhead], 1152 BUS_DMASYNC_PREWRITE); 1153 1154 /* Tell the hardware to xmit the packet. */ 1155 if (!sc->is_emacb) { 1156 WR4(sc, ETH_TAR, segs[0].ds_addr); 1157 BARRIER(sc, ETH_TAR, 4, BUS_SPACE_BARRIER_WRITE); 1158 WR4(sc, ETH_TCR, segs[0].ds_len); 1159 } else { 1160 bus_dmamap_sync(sc->tx_desc_tag, sc->tx_desc_map, 1161 BUS_DMASYNC_POSTWRITE); 1162 sc->tx_descs[sc->txhead].addr = segs[0].ds_addr; 1163 sc->tx_descs[sc->txhead].status = segs[0].ds_len | 1164 (sc->tx_descs[sc->txhead].status & ETHB_TX_WRAP) | 1165 ETHB_TX_BUF_LAST; 1166 bus_dmamap_sync(sc->tx_desc_tag, sc->tx_desc_map, 1167 BUS_DMASYNC_PREWRITE); 1168 WR4(sc, ETH_CTL, RD4(sc, ETH_CTL) | ETHB_CTL_TGO); 1169 } 1170 sc->txhead = NEXT_TX_IDX(sc, sc->txhead); 1171 1172 /* Tap off here if there is a bpf listener. */ 1173 BPF_MTAP(ifp, m); 1174 } 1175 1176 if ((sc->tx_descs[sc->txhead].status & ETHB_TX_USED) == 0) 1177 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1178} 1179 1180static void 1181ateinit(void *xsc) 1182{ 1183 struct ate_softc *sc = xsc; 1184 1185 ATE_LOCK(sc); 1186 ateinit_locked(sc); 1187 ATE_UNLOCK(sc); 1188} 1189 1190static void 1191atestart(struct ifnet *ifp) 1192{ 1193 struct ate_softc *sc = ifp->if_softc; 1194 1195 ATE_LOCK(sc); 1196 atestart_locked(ifp); 1197 ATE_UNLOCK(sc); 1198} 1199 1200/* 1201 * Turn off interrupts, and stop the NIC. Can be called with sc->ifp NULL, 1202 * so be careful. 1203 */ 1204static void 1205atestop(struct ate_softc *sc) 1206{ 1207 struct ifnet *ifp; 1208 int i; 1209 1210 ATE_ASSERT_LOCKED(sc); 1211 ifp = sc->ifp; 1212 if (ifp) { 1213 //ifp->if_timer = 0; 1214 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1215 } 1216 1217 callout_stop(&sc->tick_ch); 1218 1219 /* 1220 * Enable some parts of the MAC that are needed always (like the 1221 * MII bus. This turns off the RE and TE bits, which will remain 1222 * off until ateinit() is called to turn them on. With RE and TE 1223 * turned off, there's no DMA to worry about after this write. 1224 */ 1225 WR4(sc, ETH_CTL, ETH_CTL_MPE); 1226 1227 /* 1228 * Turn off all the configured options and revert to defaults. 1229 */ 1230 1231 /* Make sure thate the MDIO clk is less than 1232 * 2.5 Mhz. Can no longer default to /32 since 1233 * SAM9 family may have MCK > 80 Mhz */ 1234 if (at91_master_clock <= 2000000) 1235 WR4(sc, ETH_CFG, ETH_CFG_CLK_8); 1236 else if (at91_master_clock <= 4000000) 1237 WR4(sc, ETH_CFG, ETH_CFG_CLK_16); 1238 else if (at91_master_clock <= 800000) 1239 WR4(sc, ETH_CFG, ETH_CFG_CLK_32); 1240 else 1241 WR4(sc, ETH_CFG, ETH_CFG_CLK_64); 1242 1243 /* 1244 * Turn off all the interrupts, and ack any pending ones by reading 1245 * the ISR. 1246 */ 1247 WR4(sc, ETH_IDR, 0xffffffff); 1248 RD4(sc, ETH_ISR); 1249 1250 /* 1251 * Clear out the Transmit and Receiver Status registers of any 1252 * errors they may be reporting 1253 */ 1254 WR4(sc, ETH_TSR, 0xffffffff); 1255 WR4(sc, ETH_RSR, 0xffffffff); 1256 1257 /* Release TX resources. */ 1258 for (i = 0; i < ATE_MAX_TX_BUFFERS; i++) { 1259 if (sc->sent_mbuf[i] != NULL) { 1260 bus_dmamap_sync(sc->mtag, sc->tx_map[i], 1261 BUS_DMASYNC_POSTWRITE); 1262 bus_dmamap_unload(sc->mtag, sc->tx_map[i]); 1263 m_freem(sc->sent_mbuf[i]); 1264 sc->sent_mbuf[i] = NULL; 1265 } 1266 } 1267 1268 /* Turn off transeiver input clock */ 1269 if (sc->is_emacb) 1270 WR4(sc, ETHB_UIO, RD4(sc, ETHB_UIO) & ~ETHB_UIO_CLKE); 1271 1272 /* 1273 * XXX we should power down the EMAC if it isn't in use, after 1274 * putting it into loopback mode. This saves about 400uA according 1275 * to the datasheet. 1276 */ 1277} 1278 1279static void 1280ate_rxfilter(struct ate_softc *sc) 1281{ 1282 struct ifnet *ifp; 1283 uint32_t reg; 1284 int enabled; 1285 1286 KASSERT(sc != NULL, ("[ate, %d]: sc is NULL!", __LINE__)); 1287 ATE_ASSERT_LOCKED(sc); 1288 ifp = sc->ifp; 1289 1290 /* Wipe out old filter settings. */ 1291 reg = RD4(sc, ETH_CFG); 1292 reg &= ~(ETH_CFG_CAF | ETH_CFG_MTI | ETH_CFG_UNI); 1293 reg |= ETH_CFG_NBC; 1294 sc->flags &= ~ATE_FLAG_MULTICAST; 1295 1296 /* Set new parameters. */ 1297 if ((ifp->if_flags & IFF_BROADCAST) != 0) 1298 reg &= ~ETH_CFG_NBC; 1299 if ((ifp->if_flags & IFF_PROMISC) != 0) { 1300 reg |= ETH_CFG_CAF; 1301 } else { 1302 enabled = ate_setmcast(sc); 1303 if (enabled != 0) { 1304 reg |= ETH_CFG_MTI; 1305 sc->flags |= ATE_FLAG_MULTICAST; 1306 } 1307 } 1308 WR4(sc, ETH_CFG, reg); 1309} 1310 1311static int 1312ateioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1313{ 1314 struct ate_softc *sc = ifp->if_softc; 1315 struct mii_data *mii; 1316 struct ifreq *ifr = (struct ifreq *)data; 1317 int drv_flags, flags; 1318 int mask, error, enabled; 1319 1320 error = 0; 1321 flags = ifp->if_flags; 1322 drv_flags = ifp->if_drv_flags; 1323 switch (cmd) { 1324 case SIOCSIFFLAGS: 1325 ATE_LOCK(sc); 1326 if ((flags & IFF_UP) != 0) { 1327 if ((drv_flags & IFF_DRV_RUNNING) != 0) { 1328 if (((flags ^ sc->if_flags) 1329 & (IFF_PROMISC | IFF_ALLMULTI)) != 0) 1330 ate_rxfilter(sc); 1331 } else { 1332 if ((sc->flags & ATE_FLAG_DETACHING) == 0) 1333 ateinit_locked(sc); 1334 } 1335 } else if ((drv_flags & IFF_DRV_RUNNING) != 0) { 1336 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1337 atestop(sc); 1338 } 1339 sc->if_flags = flags; 1340 ATE_UNLOCK(sc); 1341 break; 1342 1343 case SIOCADDMULTI: 1344 case SIOCDELMULTI: 1345 if ((drv_flags & IFF_DRV_RUNNING) != 0) { 1346 ATE_LOCK(sc); 1347 enabled = ate_setmcast(sc); 1348 if (enabled != (sc->flags & ATE_FLAG_MULTICAST)) 1349 ate_rxfilter(sc); 1350 ATE_UNLOCK(sc); 1351 } 1352 break; 1353 1354 case SIOCSIFMEDIA: 1355 case SIOCGIFMEDIA: 1356 mii = device_get_softc(sc->miibus); 1357 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 1358 break; 1359 case SIOCSIFCAP: 1360 mask = ifp->if_capenable ^ ifr->ifr_reqcap; 1361 if (mask & IFCAP_VLAN_MTU) { 1362 ATE_LOCK(sc); 1363 if (ifr->ifr_reqcap & IFCAP_VLAN_MTU) { 1364 WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) | ETH_CFG_BIG); 1365 ifp->if_capenable |= IFCAP_VLAN_MTU; 1366 } else { 1367 WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) & ~ETH_CFG_BIG); 1368 ifp->if_capenable &= ~IFCAP_VLAN_MTU; 1369 } 1370 ATE_UNLOCK(sc); 1371 } 1372 default: 1373 error = ether_ioctl(ifp, cmd, data); 1374 break; 1375 } 1376 return (error); 1377} 1378 1379static void 1380ate_child_detached(device_t dev, device_t child) 1381{ 1382 struct ate_softc *sc; 1383 1384 sc = device_get_softc(dev); 1385 if (child == sc->miibus) 1386 sc->miibus = NULL; 1387} 1388 1389/* 1390 * MII bus support routines. 1391 */ 1392static int 1393ate_miibus_readreg(device_t dev, int phy, int reg) 1394{ 1395 struct ate_softc *sc; 1396 int val; 1397 1398 /* 1399 * XXX if we implement agressive power savings, then we need 1400 * XXX to make sure that the clock to the emac is on here 1401 */ 1402 1403 sc = device_get_softc(dev); 1404 DELAY(1); /* Hangs w/o this delay really 30.5us atm */ 1405 WR4(sc, ETH_MAN, ETH_MAN_REG_RD(phy, reg)); 1406 while ((RD4(sc, ETH_SR) & ETH_SR_IDLE) == 0) 1407 continue; 1408 val = RD4(sc, ETH_MAN) & ETH_MAN_VALUE_MASK; 1409 1410 return (val); 1411} 1412 1413static int 1414ate_miibus_writereg(device_t dev, int phy, int reg, int data) 1415{ 1416 struct ate_softc *sc; 1417 1418 /* 1419 * XXX if we implement agressive power savings, then we need 1420 * XXX to make sure that the clock to the emac is on here 1421 */ 1422 1423 sc = device_get_softc(dev); 1424 WR4(sc, ETH_MAN, ETH_MAN_REG_WR(phy, reg, data)); 1425 while ((RD4(sc, ETH_SR) & ETH_SR_IDLE) == 0) 1426 continue; 1427 return (0); 1428} 1429 1430static device_method_t ate_methods[] = { 1431 /* Device interface */ 1432 DEVMETHOD(device_probe, ate_probe), 1433 DEVMETHOD(device_attach, ate_attach), 1434 DEVMETHOD(device_detach, ate_detach), 1435 1436 /* Bus interface */ 1437 DEVMETHOD(bus_child_detached, ate_child_detached), 1438 1439 /* MII interface */ 1440 DEVMETHOD(miibus_readreg, ate_miibus_readreg), 1441 DEVMETHOD(miibus_writereg, ate_miibus_writereg), 1442 1443 DEVMETHOD_END 1444}; 1445 1446static driver_t ate_driver = { 1447 "ate", 1448 ate_methods, 1449 sizeof(struct ate_softc), 1450}; 1451 1452DRIVER_MODULE(ate, atmelarm, ate_driver, ate_devclass, NULL, NULL); 1453DRIVER_MODULE(miibus, ate, miibus_driver, miibus_devclass, NULL, NULL); 1454MODULE_DEPEND(ate, miibus, 1, 1, 1); 1455MODULE_DEPEND(ate, ether, 1, 1, 1); 1456