if_ate.c revision 248189
1/*- 2 * Copyright (c) 2006 M. Warner Losh. All rights reserved. 3 * Copyright (c) 2009 Greg Ansley. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27/* TODO 28 * 29 * 1) Turn on the clock in pmc? Turn off? 30 * 2) GPIO initializtion in board setup code. 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/arm/at91/if_ate.c 248189 2013-03-12 10:05:36Z glebius $"); 35 36#include <sys/param.h> 37#include <sys/systm.h> 38#include <sys/bus.h> 39#include <sys/kernel.h> 40#include <sys/malloc.h> 41#include <sys/mbuf.h> 42#include <sys/module.h> 43#include <sys/rman.h> 44#include <sys/socket.h> 45#include <sys/sockio.h> 46#include <sys/sysctl.h> 47 48#include <machine/bus.h> 49 50#include <net/ethernet.h> 51#include <net/if.h> 52#include <net/if_arp.h> 53#include <net/if_dl.h> 54#include <net/if_media.h> 55#include <net/if_mib.h> 56#include <net/if_types.h> 57 58#ifdef INET 59#include <netinet/in.h> 60#include <netinet/in_systm.h> 61#include <netinet/in_var.h> 62#include <netinet/ip.h> 63#endif 64 65#include <net/bpf.h> 66#include <net/bpfdesc.h> 67 68#include <dev/mii/mii.h> 69#include <dev/mii/miivar.h> 70 71#include "opt_at91.h" 72#include <arm/at91/at91reg.h> 73#include <arm/at91/at91var.h> 74#include <arm/at91/if_atereg.h> 75 76#include "miibus_if.h" 77 78/* 79 * Driver-specific flags. 80 */ 81#define ATE_FLAG_DETACHING 0x01 82#define ATE_FLAG_MULTICAST 0x02 83 84/* 85 * Old EMAC assumes whole packet fits in one buffer; 86 * new EBACB assumes all receive buffers are 128 bytes 87 */ 88#define RX_BUF_SIZE(sc) (sc->is_emacb ? 128 : MCLBYTES) 89 90/* 91 * EMACB has an 11 bit counter for Rx/Tx Descriptors 92 * for max total of 1024 decriptors each. 93 */ 94#define ATE_MAX_RX_DESCR 1024 95#define ATE_MAX_TX_DESCR 1024 96 97/* How many buffers to allocate */ 98#define ATE_MAX_TX_BUFFERS 4 /* We have ping-pong tx buffers */ 99 100/* How much memory to use for rx buffers */ 101#define ATE_RX_MEMORY (ATE_MAX_RX_DESCR * 128) 102 103/* Actual number of descriptors we allocate */ 104#define ATE_NUM_RX_DESCR ATE_MAX_RX_DESCR 105#define ATE_NUM_TX_DESCR ATE_MAX_TX_BUFFERS 106 107#if ATE_NUM_TX_DESCR > ATE_MAX_TX_DESCR 108#error "Can't have more TX buffers that descriptors" 109#endif 110#if ATE_NUM_RX_DESCR > ATE_MAX_RX_DESCR 111#error "Can't have more RX buffers that descriptors" 112#endif 113 114/* Wrap indexes the same way the hardware does */ 115#define NEXT_RX_IDX(sc, cur) \ 116 ((sc->rx_descs[cur].addr & ETH_WRAP_BIT) ? 0 : (cur + 1)) 117 118#define NEXT_TX_IDX(sc, cur) \ 119 ((sc->tx_descs[cur].status & ETHB_TX_WRAP) ? 0 : (cur + 1)) 120 121struct ate_softc 122{ 123 struct ifnet *ifp; /* ifnet pointer */ 124 struct mtx sc_mtx; /* Basically a perimeter lock */ 125 device_t dev; /* Myself */ 126 device_t miibus; /* My child miibus */ 127 struct resource *irq_res; /* IRQ resource */ 128 struct resource *mem_res; /* Memory resource */ 129 struct callout tick_ch; /* Tick callout */ 130 struct ifmib_iso_8802_3 mibdata; /* Stuff for network mgmt */ 131 bus_dma_tag_t mtag; /* bus dma tag for mbufs */ 132 bus_dma_tag_t rx_tag; 133 bus_dma_tag_t rx_desc_tag; 134 bus_dmamap_t rx_desc_map; 135 bus_dmamap_t rx_map[ATE_MAX_RX_DESCR]; 136 bus_addr_t rx_desc_phys; /* PA of rx descriptors */ 137 eth_rx_desc_t *rx_descs; /* VA of rx descriptors */ 138 void *rx_buf[ATE_NUM_RX_DESCR]; /* RX buffer space */ 139 int rxhead; /* Current RX map/desc index */ 140 uint32_t rx_buf_size; /* Size of Rx buffers */ 141 142 bus_dma_tag_t tx_desc_tag; 143 bus_dmamap_t tx_desc_map; 144 bus_dmamap_t tx_map[ATE_MAX_TX_BUFFERS]; 145 bus_addr_t tx_desc_phys; /* PA of tx descriptors */ 146 eth_tx_desc_t *tx_descs; /* VA of tx descriptors */ 147 int txhead; /* Current TX map/desc index */ 148 int txtail; /* Current TX map/desc index */ 149 struct mbuf *sent_mbuf[ATE_MAX_TX_BUFFERS]; /* Sent mbufs */ 150 void *intrhand; /* Interrupt handle */ 151 int flags; 152 int if_flags; 153 int use_rmii; 154 int is_emacb; /* SAM9x hardware version */ 155}; 156 157static inline uint32_t 158RD4(struct ate_softc *sc, bus_size_t off) 159{ 160 161 return (bus_read_4(sc->mem_res, off)); 162} 163 164static inline void 165WR4(struct ate_softc *sc, bus_size_t off, uint32_t val) 166{ 167 168 bus_write_4(sc->mem_res, off, val); 169} 170 171static inline void 172BARRIER(struct ate_softc *sc, bus_size_t off, bus_size_t len, int flags) 173{ 174 175 bus_barrier(sc->mem_res, off, len, flags); 176} 177 178#define ATE_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 179#define ATE_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 180#define ATE_LOCK_INIT(_sc) \ 181 mtx_init(&_sc->sc_mtx, device_get_nameunit(_sc->dev), \ 182 MTX_NETWORK_LOCK, MTX_DEF) 183#define ATE_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx); 184#define ATE_ASSERT_LOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_OWNED); 185#define ATE_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_NOTOWNED); 186 187static devclass_t ate_devclass; 188 189/* 190 * ifnet entry points. 191 */ 192static void ateinit_locked(void *); 193static void atestart_locked(struct ifnet *); 194 195static void ateinit(void *); 196static void atestart(struct ifnet *); 197static void atestop(struct ate_softc *); 198static int ateioctl(struct ifnet * ifp, u_long, caddr_t); 199 200/* 201 * Bus entry points. 202 */ 203static int ate_probe(device_t dev); 204static int ate_attach(device_t dev); 205static int ate_detach(device_t dev); 206static void ate_intr(void *); 207 208/* 209 * Helper routines. 210 */ 211static int ate_activate(device_t dev); 212static void ate_deactivate(struct ate_softc *sc); 213static int ate_ifmedia_upd(struct ifnet *ifp); 214static void ate_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr); 215static int ate_get_mac(struct ate_softc *sc, u_char *eaddr); 216static void ate_set_mac(struct ate_softc *sc, u_char *eaddr); 217static void ate_rxfilter(struct ate_softc *sc); 218 219static int ate_miibus_readreg(device_t dev, int phy, int reg); 220 221static int ate_miibus_writereg(device_t dev, int phy, int reg, int data); 222/* 223 * The AT91 family of products has the ethernet interface called EMAC. 224 * However, it isn't self identifying. It is anticipated that the parent bus 225 * code will take care to only add ate devices where they really are. As 226 * such, we do nothing here to identify the device and just set its name. 227 */ 228static int 229ate_probe(device_t dev) 230{ 231 232 device_set_desc(dev, "EMAC"); 233 return (0); 234} 235 236static int 237ate_attach(device_t dev) 238{ 239 struct ate_softc *sc; 240 struct ifnet *ifp = NULL; 241 struct sysctl_ctx_list *sctx; 242 struct sysctl_oid *soid; 243 u_char eaddr[ETHER_ADDR_LEN]; 244 uint32_t rnd; 245 int rid, err; 246 247 sc = device_get_softc(dev); 248 sc->dev = dev; 249 ATE_LOCK_INIT(sc); 250 251 rid = 0; 252 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 253 RF_ACTIVE); 254 if (sc->mem_res == NULL) { 255 device_printf(dev, "could not allocate memory resources.\n"); 256 err = ENOMEM; 257 goto out; 258 } 259 rid = 0; 260 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 261 RF_ACTIVE); 262 if (sc->irq_res == NULL) { 263 device_printf(dev, "could not allocate interrupt resources.\n"); 264 err = ENOMEM; 265 goto out; 266 } 267 268 /* New or old version, chooses buffer size. */ 269 sc->is_emacb = at91_is_sam9() || at91_is_sam9xe(); 270 sc->rx_buf_size = RX_BUF_SIZE(sc); 271 272 err = ate_activate(dev); 273 if (err) 274 goto out; 275 276 /* Default to what boot rom did */ 277 if (!sc->is_emacb) 278 sc->use_rmii = 279 (RD4(sc, ETH_CFG) & ETH_CFG_RMII) == ETH_CFG_RMII; 280 else 281 sc->use_rmii = 282 (RD4(sc, ETHB_UIO) & ETHB_UIO_RMII) == ETHB_UIO_RMII; 283 284#ifdef AT91_ATE_USE_RMII 285 /* Compile time override */ 286 sc->use_rmii = 1; 287#endif 288 /* Sysctls */ 289 sctx = device_get_sysctl_ctx(dev); 290 soid = device_get_sysctl_tree(dev); 291 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "rmii", 292 CTLFLAG_RW, &sc->use_rmii, 0, "rmii in use"); 293 294 /* Calling atestop before ifp is set is OK. */ 295 ATE_LOCK(sc); 296 atestop(sc); 297 ATE_UNLOCK(sc); 298 callout_init_mtx(&sc->tick_ch, &sc->sc_mtx, 0); 299 300 if ((err = ate_get_mac(sc, eaddr)) != 0) { 301 /* No MAC address configured. Generate the random one. */ 302 if (bootverbose) 303 device_printf(dev, 304 "Generating random ethernet address.\n"); 305 rnd = arc4random(); 306 307 /* 308 * Set OUI to convenient locally assigned address. 'b' 309 * is 0x62, which has the locally assigned bit set, and 310 * the broadcast/multicast bit clear. 311 */ 312 eaddr[0] = 'b'; 313 eaddr[1] = 's'; 314 eaddr[2] = 'd'; 315 eaddr[3] = (rnd >> 16) & 0xff; 316 eaddr[4] = (rnd >> 8) & 0xff; 317 eaddr[5] = (rnd >> 0) & 0xff; 318 } 319 320 sc->ifp = ifp = if_alloc(IFT_ETHER); 321 err = mii_attach(dev, &sc->miibus, ifp, ate_ifmedia_upd, 322 ate_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0); 323 if (err != 0) { 324 device_printf(dev, "attaching PHYs failed\n"); 325 goto out; 326 } 327 /* 328 * XXX: Clear the isolate bit, or we won't get up, 329 * at least on the HL201 330 */ 331 ate_miibus_writereg(dev, 0, 0, 0x3000); 332 333 ifp->if_softc = sc; 334 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 335 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 336 ifp->if_capabilities |= IFCAP_VLAN_MTU; 337 ifp->if_capenable |= IFCAP_VLAN_MTU; /* The hw bits already set. */ 338 ifp->if_start = atestart; 339 ifp->if_ioctl = ateioctl; 340 ifp->if_init = ateinit; 341 ifp->if_baudrate = 10000000; 342 IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN); 343 ifp->if_snd.ifq_drv_maxlen = IFQ_MAXLEN; 344 IFQ_SET_READY(&ifp->if_snd); 345 ifp->if_linkmib = &sc->mibdata; 346 ifp->if_linkmiblen = sizeof(sc->mibdata); 347 sc->mibdata.dot3Compliance = DOT3COMPLIANCE_COLLS; 348 sc->if_flags = ifp->if_flags; 349 350 ether_ifattach(ifp, eaddr); 351 352 /* Activate the interrupt. */ 353 err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_NET | INTR_MPSAFE, 354 NULL, ate_intr, sc, &sc->intrhand); 355 if (err) { 356 device_printf(dev, "could not establish interrupt handler.\n"); 357 ether_ifdetach(ifp); 358 goto out; 359 } 360 361out: 362 if (err) 363 ate_detach(dev); 364 return (err); 365} 366 367static int 368ate_detach(device_t dev) 369{ 370 struct ate_softc *sc; 371 struct ifnet *ifp; 372 373 sc = device_get_softc(dev); 374 KASSERT(sc != NULL, ("[ate: %d]: sc is NULL", __LINE__)); 375 ifp = sc->ifp; 376 if (device_is_attached(dev)) { 377 ATE_LOCK(sc); 378 sc->flags |= ATE_FLAG_DETACHING; 379 atestop(sc); 380 ATE_UNLOCK(sc); 381 callout_drain(&sc->tick_ch); 382 ether_ifdetach(ifp); 383 } 384 if (sc->miibus != NULL) { 385 device_delete_child(dev, sc->miibus); 386 sc->miibus = NULL; 387 } 388 bus_generic_detach(sc->dev); 389 ate_deactivate(sc); 390 if (sc->intrhand != NULL) { 391 bus_teardown_intr(dev, sc->irq_res, sc->intrhand); 392 sc->intrhand = NULL; 393 } 394 if (ifp != NULL) { 395 if_free(ifp); 396 sc->ifp = NULL; 397 } 398 if (sc->mem_res != NULL) { 399 bus_release_resource(dev, SYS_RES_IOPORT, 400 rman_get_rid(sc->mem_res), sc->mem_res); 401 sc->mem_res = NULL; 402 } 403 if (sc->irq_res != NULL) { 404 bus_release_resource(dev, SYS_RES_IRQ, 405 rman_get_rid(sc->irq_res), sc->irq_res); 406 sc->irq_res = NULL; 407 } 408 ATE_LOCK_DESTROY(sc); 409 return (0); 410} 411 412static void 413ate_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 414{ 415 416 if (error != 0) 417 return; 418 *(bus_addr_t *)arg = segs[0].ds_addr; 419} 420 421static void 422ate_load_rx_buf(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 423{ 424 struct ate_softc *sc; 425 426 if (error != 0) 427 return; 428 sc = (struct ate_softc *)arg; 429 430 bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, BUS_DMASYNC_PREWRITE); 431 sc->rx_descs[sc->rxhead].addr = segs[0].ds_addr; 432 sc->rx_descs[sc->rxhead].status = 0; 433 bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, BUS_DMASYNC_POSTWRITE); 434} 435 436static uint32_t 437ate_mac_hash(const uint8_t *buf) 438{ 439 uint32_t index = 0; 440 for (int i = 0; i < 48; i++) { 441 index ^= ((buf[i >> 3] >> (i & 7)) & 1) << (i % 6); 442 } 443 return (index); 444} 445 446/* 447 * Compute the multicast filter for this device. 448 */ 449static int 450ate_setmcast(struct ate_softc *sc) 451{ 452 uint32_t index; 453 uint32_t mcaf[2]; 454 u_char *af = (u_char *) mcaf; 455 struct ifmultiaddr *ifma; 456 struct ifnet *ifp; 457 458 ifp = sc->ifp; 459 460 if ((ifp->if_flags & IFF_PROMISC) != 0) 461 return (0); 462 if ((ifp->if_flags & IFF_ALLMULTI) != 0) { 463 WR4(sc, ETH_HSL, 0xffffffff); 464 WR4(sc, ETH_HSH, 0xffffffff); 465 return (1); 466 } 467 468 /* Compute the multicast hash. */ 469 mcaf[0] = 0; 470 mcaf[1] = 0; 471 if_maddr_rlock(ifp); 472 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 473 if (ifma->ifma_addr->sa_family != AF_LINK) 474 continue; 475 index = ate_mac_hash(LLADDR((struct sockaddr_dl *) 476 ifma->ifma_addr)); 477 af[index >> 3] |= 1 << (index & 7); 478 } 479 if_maddr_runlock(ifp); 480 481 /* 482 * Write the hash to the hash register. This card can also 483 * accept unicast packets as well as multicast packets using this 484 * register for easier bridging operations, but we don't take 485 * advantage of that. Locks here are to avoid LOR with the 486 * if_maddr_rlock, but might not be strictly necessary. 487 */ 488 WR4(sc, ETH_HSL, mcaf[0]); 489 WR4(sc, ETH_HSH, mcaf[1]); 490 return (mcaf[0] || mcaf[1]); 491} 492 493static int 494ate_activate(device_t dev) 495{ 496 struct ate_softc *sc; 497 int i; 498 499 sc = device_get_softc(dev); 500 501 /* Allocate DMA tags and maps for TX mbufs */ 502 if (bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0, 503 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 504 1, MCLBYTES, 0, busdma_lock_mutex, &sc->sc_mtx, &sc->mtag)) 505 goto errout; 506 for (i = 0; i < ATE_MAX_TX_BUFFERS; i++) { 507 if ( bus_dmamap_create(sc->mtag, 0, &sc->tx_map[i])) 508 goto errout; 509 } 510 511 512 /* DMA tag and map for the RX descriptors. */ 513 if (bus_dma_tag_create(bus_get_dma_tag(dev), sizeof(eth_rx_desc_t), 514 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 515 ATE_NUM_RX_DESCR * sizeof(eth_rx_desc_t), 1, 516 ATE_NUM_RX_DESCR * sizeof(eth_rx_desc_t), 0, busdma_lock_mutex, 517 &sc->sc_mtx, &sc->rx_desc_tag)) 518 goto errout; 519 if (bus_dmamem_alloc(sc->rx_desc_tag, (void **)&sc->rx_descs, 520 BUS_DMA_NOWAIT | BUS_DMA_COHERENT, &sc->rx_desc_map) != 0) 521 goto errout; 522 if (bus_dmamap_load(sc->rx_desc_tag, sc->rx_desc_map, 523 sc->rx_descs, ATE_NUM_RX_DESCR * sizeof(eth_rx_desc_t), 524 ate_getaddr, &sc->rx_desc_phys, 0) != 0) 525 goto errout; 526 527 /* Allocate DMA tags and maps for RX. buffers */ 528 if (bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0, 529 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 530 sc->rx_buf_size, 1, sc->rx_buf_size, 0, 531 busdma_lock_mutex, &sc->sc_mtx, &sc->rx_tag)) 532 goto errout; 533 534 /* 535 * Allocate our RX buffers. 536 * This chip has a RX structure that's filled in. 537 * XXX On MACB (SAM9 part) we should receive directly into mbuf 538 * to avoid the copy. XXX 539 */ 540 sc->rxhead = 0; 541 for (sc->rxhead = 0; sc->rxhead < ATE_RX_MEMORY/sc->rx_buf_size; 542 sc->rxhead++) { 543 if (bus_dmamem_alloc(sc->rx_tag, 544 (void **)&sc->rx_buf[sc->rxhead], BUS_DMA_NOWAIT, 545 &sc->rx_map[sc->rxhead]) != 0) 546 goto errout; 547 548 if (bus_dmamap_load(sc->rx_tag, sc->rx_map[sc->rxhead], 549 sc->rx_buf[sc->rxhead], sc->rx_buf_size, 550 ate_load_rx_buf, sc, 0) != 0) { 551 printf("bus_dmamem_load\n"); 552 goto errout; 553 } 554 bus_dmamap_sync(sc->rx_tag, sc->rx_map[sc->rxhead], BUS_DMASYNC_PREREAD); 555 } 556 557 /* 558 * For the last buffer, set the wrap bit so the controller 559 * restarts from the first descriptor. 560 */ 561 sc->rx_descs[--sc->rxhead].addr |= ETH_WRAP_BIT; 562 sc->rxhead = 0; 563 564 /* Flush the memory for the EMAC rx descriptor. */ 565 bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, BUS_DMASYNC_PREWRITE); 566 567 /* Write the descriptor queue address. */ 568 WR4(sc, ETH_RBQP, sc->rx_desc_phys); 569 570 /* 571 * DMA tag and map for the TX descriptors. 572 */ 573 if (bus_dma_tag_create(bus_get_dma_tag(dev), sizeof(eth_tx_desc_t), 574 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 575 ATE_MAX_TX_BUFFERS * sizeof(eth_tx_desc_t), 1, 576 ATE_MAX_TX_BUFFERS * sizeof(eth_tx_desc_t), 0, busdma_lock_mutex, 577 &sc->sc_mtx, &sc->tx_desc_tag) != 0) 578 goto errout; 579 580 if (bus_dmamem_alloc(sc->tx_desc_tag, (void **)&sc->tx_descs, 581 BUS_DMA_NOWAIT | BUS_DMA_COHERENT, &sc->tx_desc_map) != 0) 582 goto errout; 583 584 if (bus_dmamap_load(sc->tx_desc_tag, sc->tx_desc_map, 585 sc->tx_descs, ATE_MAX_TX_BUFFERS * sizeof(eth_tx_desc_t), 586 ate_getaddr, &sc->tx_desc_phys, 0) != 0) 587 goto errout; 588 589 /* Initilize descriptors; mark all empty */ 590 for (i = 0; i < ATE_MAX_TX_BUFFERS; i++) { 591 sc->tx_descs[i].addr =0; 592 sc->tx_descs[i].status = ETHB_TX_USED; 593 sc->sent_mbuf[i] = NULL; 594 } 595 596 /* Mark last entry to cause wrap when indexing through */ 597 sc->tx_descs[ATE_MAX_TX_BUFFERS - 1].status = 598 ETHB_TX_WRAP | ETHB_TX_USED; 599 600 /* Flush the memory for the EMAC tx descriptor. */ 601 bus_dmamap_sync(sc->tx_desc_tag, sc->tx_desc_map, BUS_DMASYNC_PREWRITE); 602 603 sc->txhead = sc->txtail = 0; 604 if (sc->is_emacb) { 605 /* Write the descriptor queue address. */ 606 WR4(sc, ETHB_TBQP, sc->tx_desc_phys); 607 608 /* EMACB: Enable transceiver input clock */ 609 WR4(sc, ETHB_UIO, RD4(sc, ETHB_UIO) | ETHB_UIO_CLKE); 610 } 611 612 return (0); 613 614errout: 615 return (ENOMEM); 616} 617 618static void 619ate_deactivate(struct ate_softc *sc) 620{ 621 int i; 622 623 KASSERT(sc != NULL, ("[ate, %d]: sc is NULL!", __LINE__)); 624 if (sc->mtag != NULL) { 625 for (i = 0; i < ATE_MAX_TX_BUFFERS; i++) { 626 if (sc->sent_mbuf[i] != NULL) { 627 bus_dmamap_sync(sc->mtag, sc->tx_map[i], 628 BUS_DMASYNC_POSTWRITE); 629 bus_dmamap_unload(sc->mtag, sc->tx_map[i]); 630 m_freem(sc->sent_mbuf[i]); 631 } 632 bus_dmamap_destroy(sc->mtag, sc->tx_map[i]); 633 sc->sent_mbuf[i] = NULL; 634 sc->tx_map[i] = NULL; 635 } 636 bus_dma_tag_destroy(sc->mtag); 637 } 638 if (sc->rx_desc_tag != NULL) { 639 if (sc->rx_descs != NULL) { 640 if (sc->rx_desc_phys != 0) { 641 bus_dmamap_sync(sc->rx_desc_tag, 642 sc->rx_desc_map, BUS_DMASYNC_POSTREAD); 643 bus_dmamap_unload(sc->rx_desc_tag, 644 sc->rx_desc_map); 645 sc->rx_desc_phys = 0; 646 } 647 } 648 } 649 if (sc->rx_tag != NULL) { 650 for (i = 0; sc->rx_buf[i] != NULL; i++) { 651 if (sc->rx_descs[i].addr != 0) { 652 bus_dmamap_sync(sc->rx_tag, 653 sc->rx_map[i], 654 BUS_DMASYNC_POSTREAD); 655 bus_dmamap_unload(sc->rx_tag, 656 sc->rx_map[i]); 657 sc->rx_descs[i].addr = 0; 658 } 659 bus_dmamem_free(sc->rx_tag, sc->rx_buf[i], 660 sc->rx_map[i]); 661 sc->rx_buf[i] = NULL; 662 sc->rx_map[i] = NULL; 663 } 664 bus_dma_tag_destroy(sc->rx_tag); 665 } 666 if (sc->rx_desc_tag != NULL) { 667 if (sc->rx_descs != NULL) 668 bus_dmamem_free(sc->rx_desc_tag, sc->rx_descs, 669 sc->rx_desc_map); 670 bus_dma_tag_destroy(sc->rx_desc_tag); 671 sc->rx_descs = NULL; 672 sc->rx_desc_tag = NULL; 673 } 674 675 if (sc->is_emacb) 676 WR4(sc, ETHB_UIO, RD4(sc, ETHB_UIO) & ~ETHB_UIO_CLKE); 677} 678 679/* 680 * Change media according to request. 681 */ 682static int 683ate_ifmedia_upd(struct ifnet *ifp) 684{ 685 struct ate_softc *sc = ifp->if_softc; 686 struct mii_data *mii; 687 688 mii = device_get_softc(sc->miibus); 689 ATE_LOCK(sc); 690 mii_mediachg(mii); 691 ATE_UNLOCK(sc); 692 return (0); 693} 694 695/* 696 * Notify the world which media we're using. 697 */ 698static void 699ate_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 700{ 701 struct ate_softc *sc = ifp->if_softc; 702 struct mii_data *mii; 703 704 mii = device_get_softc(sc->miibus); 705 ATE_LOCK(sc); 706 mii_pollstat(mii); 707 ifmr->ifm_active = mii->mii_media_active; 708 ifmr->ifm_status = mii->mii_media_status; 709 ATE_UNLOCK(sc); 710} 711 712static void 713ate_stat_update(struct ate_softc *sc, int active) 714{ 715 uint32_t reg; 716 717 /* 718 * The speed and full/half-duplex state needs to be reflected 719 * in the ETH_CFG register. 720 */ 721 reg = RD4(sc, ETH_CFG); 722 reg &= ~(ETH_CFG_SPD | ETH_CFG_FD); 723 if (IFM_SUBTYPE(active) != IFM_10_T) 724 reg |= ETH_CFG_SPD; 725 if (active & IFM_FDX) 726 reg |= ETH_CFG_FD; 727 WR4(sc, ETH_CFG, reg); 728} 729 730static void 731ate_tick(void *xsc) 732{ 733 struct ate_softc *sc = xsc; 734 struct ifnet *ifp = sc->ifp; 735 struct mii_data *mii; 736 int active; 737 uint32_t c; 738 739 /* 740 * The KB920x boot loader tests ETH_SR & ETH_SR_LINK and will ask 741 * the MII if there's a link if this bit is clear. Not sure if we 742 * should do the same thing here or not. 743 */ 744 ATE_ASSERT_LOCKED(sc); 745 if (sc->miibus != NULL) { 746 mii = device_get_softc(sc->miibus); 747 active = mii->mii_media_active; 748 mii_tick(mii); 749 if (mii->mii_media_status & IFM_ACTIVE && 750 active != mii->mii_media_active) 751 ate_stat_update(sc, mii->mii_media_active); 752 } 753 754 /* 755 * Update the stats as best we can. When we're done, clear 756 * the status counters and start over. We're supposed to read these 757 * registers often enough that they won't overflow. Hopefully 758 * once a second is often enough. Some don't map well to 759 * the dot3Stats mib, so for those we just count them as general 760 * errors. Stats for iframes, ibutes, oframes and obytes are 761 * collected elsewhere. These registers zero on a read to prevent 762 * races. For all the collision stats, also update the collision 763 * stats for the interface. 764 */ 765 sc->mibdata.dot3StatsAlignmentErrors += RD4(sc, ETH_ALE); 766 sc->mibdata.dot3StatsFCSErrors += RD4(sc, ETH_SEQE); 767 c = RD4(sc, ETH_SCOL); 768 ifp->if_collisions += c; 769 sc->mibdata.dot3StatsSingleCollisionFrames += c; 770 c = RD4(sc, ETH_MCOL); 771 sc->mibdata.dot3StatsMultipleCollisionFrames += c; 772 ifp->if_collisions += c; 773 sc->mibdata.dot3StatsSQETestErrors += RD4(sc, ETH_SQEE); 774 sc->mibdata.dot3StatsDeferredTransmissions += RD4(sc, ETH_DTE); 775 c = RD4(sc, ETH_LCOL); 776 sc->mibdata.dot3StatsLateCollisions += c; 777 ifp->if_collisions += c; 778 c = RD4(sc, ETH_ECOL); 779 sc->mibdata.dot3StatsExcessiveCollisions += c; 780 ifp->if_collisions += c; 781 sc->mibdata.dot3StatsCarrierSenseErrors += RD4(sc, ETH_CSE); 782 sc->mibdata.dot3StatsFrameTooLongs += RD4(sc, ETH_ELR); 783 sc->mibdata.dot3StatsInternalMacReceiveErrors += RD4(sc, ETH_DRFC); 784 785 /* 786 * Not sure where to lump these, so count them against the errors 787 * for the interface. 788 */ 789 sc->ifp->if_oerrors += RD4(sc, ETH_TUE); 790 sc->ifp->if_ierrors += RD4(sc, ETH_CDE) + RD4(sc, ETH_RJB) + 791 RD4(sc, ETH_USF); 792 793 /* Schedule another timeout one second from now. */ 794 callout_reset(&sc->tick_ch, hz, ate_tick, sc); 795} 796 797static void 798ate_set_mac(struct ate_softc *sc, u_char *eaddr) 799{ 800 801 WR4(sc, ETH_SA1L, (eaddr[3] << 24) | (eaddr[2] << 16) | 802 (eaddr[1] << 8) | eaddr[0]); 803 WR4(sc, ETH_SA1H, (eaddr[5] << 8) | (eaddr[4])); 804} 805 806static int 807ate_get_mac(struct ate_softc *sc, u_char *eaddr) 808{ 809 bus_size_t sa_low_reg[] = { ETH_SA1L, ETH_SA2L, ETH_SA3L, ETH_SA4L }; 810 bus_size_t sa_high_reg[] = { ETH_SA1H, ETH_SA2H, ETH_SA3H, ETH_SA4H }; 811 uint32_t low, high; 812 int i; 813 814 /* 815 * The boot loader may setup the MAC with an address(es), grab the 816 * first MAC address from the SA[1-4][HL] registers. 817 */ 818 for (i = 0; i < 4; i++) { 819 low = RD4(sc, sa_low_reg[i]); 820 high = RD4(sc, sa_high_reg[i]); 821 if ((low | (high & 0xffff)) != 0) { 822 eaddr[0] = low & 0xff; 823 eaddr[1] = (low >> 8) & 0xff; 824 eaddr[2] = (low >> 16) & 0xff; 825 eaddr[3] = (low >> 24) & 0xff; 826 eaddr[4] = high & 0xff; 827 eaddr[5] = (high >> 8) & 0xff; 828 return (0); 829 } 830 } 831 return (ENXIO); 832} 833 834static void 835ate_intr(void *xsc) 836{ 837 struct ate_softc *sc = xsc; 838 struct ifnet *ifp = sc->ifp; 839 struct mbuf *mb; 840 eth_rx_desc_t *rxdhead; 841 uint32_t status, reg, idx; 842 int remain, count, done; 843 844 status = RD4(sc, ETH_ISR); 845 if (status == 0) 846 return; 847 848 if (status & ETH_ISR_RCOM) { 849 bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, 850 BUS_DMASYNC_POSTREAD); 851 852 rxdhead = &sc->rx_descs[sc->rxhead]; 853 while (rxdhead->addr & ETH_CPU_OWNER) { 854 if (!sc->is_emacb) { 855 /* 856 * Simulate SAM9 FIRST/LAST bits for RM9200. 857 * RM9200 EMAC has only on Rx buffer per packet. 858 * But sometime we are handed a zero lenght packet. 859 */ 860 if ((rxdhead->status & ETH_LEN_MASK) == 0) 861 rxdhead->status = 0; /* Mark error */ 862 else 863 rxdhead->status |= ETH_BUF_FIRST | ETH_BUF_LAST; 864 } 865 866 if ((rxdhead->status & ETH_BUF_FIRST) == 0) { 867 /* Something went wrong during RX so 868 release back to EMAC all buffers of invalid packets. 869 */ 870 rxdhead->status = 0; 871 rxdhead->addr &= ~ETH_CPU_OWNER; 872 sc->rxhead = NEXT_RX_IDX(sc, sc->rxhead); 873 rxdhead = &sc->rx_descs[sc->rxhead]; 874 continue; 875 } 876 877 /* Find end of packet or start of next */ 878 idx = sc->rxhead; 879 if ((sc->rx_descs[idx].status & ETH_BUF_LAST) == 0) { 880 idx = NEXT_RX_IDX(sc, idx); 881 882 while ((sc->rx_descs[idx].addr & ETH_CPU_OWNER) && 883 ((sc->rx_descs[idx].status & 884 (ETH_BUF_FIRST|ETH_BUF_LAST))== 0)) 885 idx = NEXT_RX_IDX(sc, idx); 886 } 887 888 /* Packet NOT yet completely in memory; we are done */ 889 if ((sc->rx_descs[idx].addr & ETH_CPU_OWNER) == 0 || 890 ((sc->rx_descs[idx].status & (ETH_BUF_FIRST|ETH_BUF_LAST))== 0)) 891 break; 892 893 /* Packets with no end descriptor are invalid. */ 894 if ((sc->rx_descs[idx].status & ETH_BUF_LAST) == 0) { 895 rxdhead->status &= ~ETH_BUF_FIRST; 896 continue; 897 } 898 899 /* FCS is not coppied into mbuf. */ 900 remain = (sc->rx_descs[idx].status & ETH_LEN_MASK) - 4; 901 902 /* Get an appropriately sized mbuf. */ 903 mb = m_get2(M_NOWAIT, MT_DATA, M_PKTHDR, 904 remain + ETHER_ALIGN); 905 if (mb == NULL) { 906 sc->ifp->if_iqdrops++; 907 rxdhead->status = 0; 908 continue; 909 } 910 mb->m_data += ETHER_ALIGN; 911 mb->m_pkthdr.rcvif = ifp; 912 913 WR4(sc, ETH_RSR, RD4(sc, ETH_RSR)); /* Reset status */ 914 915 /* Now we process the buffers that make up the packet */ 916 do { 917 918 /* Last buffer may just be 1-4 bytes of FCS so remain 919 * may be zero for last decriptor. */ 920 if (remain > 0) { 921 /* Make sure we get the current bytes */ 922 bus_dmamap_sync(sc->rx_tag, sc->rx_map[sc->rxhead], 923 BUS_DMASYNC_POSTREAD); 924 925 count = MIN(remain, sc->rx_buf_size); 926 927 /* XXX Performance robbing copy. Could 928 * recieve directly to mbufs if not an 929 * RM9200. And even then we could likely 930 * copy just the protocol headers. XXX */ 931 m_append(mb, count, sc->rx_buf[sc->rxhead]); 932 remain -= count; 933 } 934 935 done = (rxdhead->status & ETH_BUF_LAST) != 0; 936 937 /* Return the descriptor to the EMAC */ 938 rxdhead->status = 0; 939 rxdhead->addr &= ~ETH_CPU_OWNER; 940 bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, 941 BUS_DMASYNC_PREWRITE); 942 943 /* Move on to next descriptor with wrap */ 944 sc->rxhead = NEXT_RX_IDX(sc, sc->rxhead); 945 rxdhead = &sc->rx_descs[sc->rxhead]; 946 947 } while (!done); 948 949 if (mb != NULL) { 950 ifp->if_ipackets++; 951 (*ifp->if_input)(ifp, mb); 952 } 953 } 954 } 955 956 957 if (status & ETH_ISR_TCOM) { 958 bus_dmamap_sync(sc->tx_desc_tag, sc->tx_desc_map, 959 BUS_DMASYNC_POSTREAD); 960 961 ATE_LOCK(sc); 962 /* XXX TSR register should be cleared */ 963 if (!sc->is_emacb) { 964 /* Simulate Transmit descriptor table */ 965 966 /* First packet done */ 967 if (sc->txtail < sc->txhead) 968 sc->tx_descs[sc->txtail].status |= ETHB_TX_USED; 969 970 /* Second Packet done */ 971 if (sc->txtail + 1 < sc->txhead && 972 RD4(sc, ETH_TSR) & ETH_TSR_IDLE) 973 sc->tx_descs[sc->txtail + 1].status |= ETHB_TX_USED; 974 } 975 976 while (sc->txtail != sc->txhead && 977 sc->tx_descs[sc->txtail].status & ETHB_TX_USED ) { 978 979 bus_dmamap_sync(sc->mtag, sc->tx_map[sc->txtail], 980 BUS_DMASYNC_POSTWRITE); 981 bus_dmamap_unload(sc->mtag, sc->tx_map[sc->txtail]); 982 m_freem(sc->sent_mbuf[sc->txtail]); 983 sc->tx_descs[sc->txtail].addr = 0; 984 sc->sent_mbuf[sc->txtail] = NULL; 985 986 ifp->if_opackets++; 987 sc->txtail = NEXT_TX_IDX(sc, sc->txtail); 988 } 989 990 /* Flush descriptors to EMAC */ 991 bus_dmamap_sync(sc->tx_desc_tag, sc->tx_desc_map, BUS_DMASYNC_PREWRITE); 992 993 /* 994 * We're no longer busy, so clear the busy flag and call the 995 * start routine to xmit more packets. 996 */ 997 sc->ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 998 atestart_locked(sc->ifp); 999 ATE_UNLOCK(sc); 1000 } 1001 1002 if (status & ETH_ISR_RBNA) { 1003 /* Workaround RM9200 Errata #11 */ 1004 if (bootverbose) 1005 device_printf(sc->dev, "RBNA workaround\n"); 1006 reg = RD4(sc, ETH_CTL); 1007 WR4(sc, ETH_CTL, reg & ~ETH_CTL_RE); 1008 BARRIER(sc, ETH_CTL, 4, BUS_SPACE_BARRIER_WRITE); 1009 WR4(sc, ETH_CTL, reg | ETH_CTL_RE); 1010 } 1011 1012 /* XXX need to work around SAM9260 errata 43.2.4.1: 1013 * disable the mac, reset tx buffer, enable mac on TUND */ 1014} 1015 1016/* 1017 * Reset and initialize the chip. 1018 */ 1019static void 1020ateinit_locked(void *xsc) 1021{ 1022 struct ate_softc *sc = xsc; 1023 struct ifnet *ifp = sc->ifp; 1024 struct mii_data *mii; 1025 uint8_t eaddr[ETHER_ADDR_LEN]; 1026 uint32_t reg; 1027 1028 ATE_ASSERT_LOCKED(sc); 1029 1030 /* 1031 * XXX TODO(3) 1032 * we need to turn on the EMAC clock in the pmc. With the 1033 * default boot loader, this is already turned on. However, we 1034 * need to think about how best to turn it on/off as the interface 1035 * is brought up/down, as well as dealing with the mii bus... 1036 * 1037 * We also need to multiplex the pins correctly (in board_xxx.c). 1038 */ 1039 1040 /* 1041 * There are two different ways that the mii bus is connected 1042 * to this chip mii or rmii. 1043 */ 1044 if (!sc->is_emacb) { 1045 /* RM9200 */ 1046 reg = RD4(sc, ETH_CFG); 1047 if (sc->use_rmii) 1048 reg |= ETH_CFG_RMII; 1049 else 1050 reg &= ~ETH_CFG_RMII; 1051 WR4(sc, ETH_CFG, reg); 1052 } else { 1053 /* SAM9 */ 1054 reg = ETHB_UIO_CLKE; 1055 reg |= (sc->use_rmii) ? ETHB_UIO_RMII : 0; 1056 WR4(sc, ETHB_UIO, reg); 1057 } 1058 1059 ate_rxfilter(sc); 1060 1061 /* 1062 * Set the chip MAC address. 1063 */ 1064 bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN); 1065 ate_set_mac(sc, eaddr); 1066 1067 /* Make sure we know state of TX queue */ 1068 sc->txhead = sc->txtail = 0; 1069 if (sc->is_emacb) { 1070 /* Write the descriptor queue address. */ 1071 WR4(sc, ETHB_TBQP, sc->tx_desc_phys); 1072 } 1073 1074 /* 1075 * Turn on MACs and interrupt processing. 1076 */ 1077 WR4(sc, ETH_CTL, RD4(sc, ETH_CTL) | ETH_CTL_TE | ETH_CTL_RE); 1078 WR4(sc, ETH_IER, ETH_ISR_RCOM | ETH_ISR_TCOM | ETH_ISR_RBNA); 1079 1080 /* Enable big packets. */ 1081 WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) | ETH_CFG_BIG); 1082 1083 /* 1084 * Set 'running' flag, and clear output active flag 1085 * and attempt to start the output. 1086 */ 1087 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1088 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1089 1090 mii = device_get_softc(sc->miibus); 1091 mii_pollstat(mii); 1092 ate_stat_update(sc, mii->mii_media_active); 1093 atestart_locked(ifp); 1094 1095 callout_reset(&sc->tick_ch, hz, ate_tick, sc); 1096} 1097 1098/* 1099 * Dequeue packets and transmit. 1100 */ 1101static void 1102atestart_locked(struct ifnet *ifp) 1103{ 1104 struct ate_softc *sc = ifp->if_softc; 1105 struct mbuf *m, *mdefrag; 1106 bus_dma_segment_t segs[1]; 1107 int nseg, e; 1108 1109 ATE_ASSERT_LOCKED(sc); 1110 if (ifp->if_drv_flags & IFF_DRV_OACTIVE) 1111 return; 1112 1113 while (sc->tx_descs[sc->txhead].status & ETHB_TX_USED) { 1114 /* 1115 * Check to see if there's room to put another packet into the 1116 * xmit queue. The old EMAC version has a ping-pong buffer for 1117 * xmit packets. We use OACTIVE to indicate "we can stuff more 1118 * into our buffers (clear) or not (set)." 1119 */ 1120 if (!sc->is_emacb) { 1121 /* RM9200 has only two hardware entries */ 1122 if (!sc->is_emacb && (RD4(sc, ETH_TSR) & ETH_TSR_BNQ) == 0) { 1123 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1124 return; 1125 } 1126 } 1127 1128 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 1129 if (m == 0) 1130 break; 1131 1132 e = bus_dmamap_load_mbuf_sg(sc->mtag, sc->tx_map[sc->txhead], m, 1133 segs, &nseg, 0); 1134 if (e == EFBIG) { 1135 mdefrag = m_defrag(m, M_NOWAIT); 1136 if (mdefrag == NULL) { 1137 IFQ_DRV_PREPEND(&ifp->if_snd, m); 1138 return; 1139 } 1140 m = mdefrag; 1141 e = bus_dmamap_load_mbuf_sg(sc->mtag, 1142 sc->tx_map[sc->txhead], m, segs, &nseg, 0); 1143 } 1144 if (e != 0) { 1145 m_freem(m); 1146 continue; 1147 } 1148 sc->sent_mbuf[sc->txhead] = m; 1149 1150 bus_dmamap_sync(sc->mtag, sc->tx_map[sc->txhead], 1151 BUS_DMASYNC_PREWRITE); 1152 1153 /* Tell the hardware to xmit the packet. */ 1154 if (!sc->is_emacb) { 1155 WR4(sc, ETH_TAR, segs[0].ds_addr); 1156 BARRIER(sc, ETH_TAR, 4, BUS_SPACE_BARRIER_WRITE); 1157 WR4(sc, ETH_TCR, segs[0].ds_len); 1158 } else { 1159 bus_dmamap_sync(sc->tx_desc_tag, sc->tx_desc_map, 1160 BUS_DMASYNC_POSTWRITE); 1161 sc->tx_descs[sc->txhead].addr = segs[0].ds_addr; 1162 sc->tx_descs[sc->txhead].status = segs[0].ds_len | 1163 (sc->tx_descs[sc->txhead].status & ETHB_TX_WRAP) | 1164 ETHB_TX_BUF_LAST; 1165 bus_dmamap_sync(sc->tx_desc_tag, sc->tx_desc_map, 1166 BUS_DMASYNC_PREWRITE); 1167 WR4(sc, ETH_CTL, RD4(sc, ETH_CTL) | ETHB_CTL_TGO); 1168 } 1169 sc->txhead = NEXT_TX_IDX(sc, sc->txhead); 1170 1171 /* Tap off here if there is a bpf listener. */ 1172 BPF_MTAP(ifp, m); 1173 } 1174 1175 if ((sc->tx_descs[sc->txhead].status & ETHB_TX_USED) == 0) 1176 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1177} 1178 1179static void 1180ateinit(void *xsc) 1181{ 1182 struct ate_softc *sc = xsc; 1183 1184 ATE_LOCK(sc); 1185 ateinit_locked(sc); 1186 ATE_UNLOCK(sc); 1187} 1188 1189static void 1190atestart(struct ifnet *ifp) 1191{ 1192 struct ate_softc *sc = ifp->if_softc; 1193 1194 ATE_LOCK(sc); 1195 atestart_locked(ifp); 1196 ATE_UNLOCK(sc); 1197} 1198 1199/* 1200 * Turn off interrupts, and stop the NIC. Can be called with sc->ifp NULL, 1201 * so be careful. 1202 */ 1203static void 1204atestop(struct ate_softc *sc) 1205{ 1206 struct ifnet *ifp; 1207 int i; 1208 1209 ATE_ASSERT_LOCKED(sc); 1210 ifp = sc->ifp; 1211 if (ifp) { 1212 //ifp->if_timer = 0; 1213 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1214 } 1215 1216 callout_stop(&sc->tick_ch); 1217 1218 /* 1219 * Enable some parts of the MAC that are needed always (like the 1220 * MII bus. This turns off the RE and TE bits, which will remain 1221 * off until ateinit() is called to turn them on. With RE and TE 1222 * turned off, there's no DMA to worry about after this write. 1223 */ 1224 WR4(sc, ETH_CTL, ETH_CTL_MPE); 1225 1226 /* 1227 * Turn off all the configured options and revert to defaults. 1228 */ 1229 1230 /* Make sure thate the MDIO clk is less than 1231 * 2.5 Mhz. Can no longer default to /32 since 1232 * SAM9 family may have MCK > 80 Mhz */ 1233 if (at91_master_clock <= 2000000) 1234 WR4(sc, ETH_CFG, ETH_CFG_CLK_8); 1235 else if (at91_master_clock <= 4000000) 1236 WR4(sc, ETH_CFG, ETH_CFG_CLK_16); 1237 else if (at91_master_clock <= 800000) 1238 WR4(sc, ETH_CFG, ETH_CFG_CLK_32); 1239 else 1240 WR4(sc, ETH_CFG, ETH_CFG_CLK_64); 1241 1242 /* 1243 * Turn off all the interrupts, and ack any pending ones by reading 1244 * the ISR. 1245 */ 1246 WR4(sc, ETH_IDR, 0xffffffff); 1247 RD4(sc, ETH_ISR); 1248 1249 /* 1250 * Clear out the Transmit and Receiver Status registers of any 1251 * errors they may be reporting 1252 */ 1253 WR4(sc, ETH_TSR, 0xffffffff); 1254 WR4(sc, ETH_RSR, 0xffffffff); 1255 1256 /* Release TX resources. */ 1257 for (i = 0; i < ATE_MAX_TX_BUFFERS; i++) { 1258 if (sc->sent_mbuf[i] != NULL) { 1259 bus_dmamap_sync(sc->mtag, sc->tx_map[i], 1260 BUS_DMASYNC_POSTWRITE); 1261 bus_dmamap_unload(sc->mtag, sc->tx_map[i]); 1262 m_freem(sc->sent_mbuf[i]); 1263 sc->sent_mbuf[i] = NULL; 1264 } 1265 } 1266 1267 /* Turn off transeiver input clock */ 1268 if (sc->is_emacb) 1269 WR4(sc, ETHB_UIO, RD4(sc, ETHB_UIO) & ~ETHB_UIO_CLKE); 1270 1271 /* 1272 * XXX we should power down the EMAC if it isn't in use, after 1273 * putting it into loopback mode. This saves about 400uA according 1274 * to the datasheet. 1275 */ 1276} 1277 1278static void 1279ate_rxfilter(struct ate_softc *sc) 1280{ 1281 struct ifnet *ifp; 1282 uint32_t reg; 1283 int enabled; 1284 1285 KASSERT(sc != NULL, ("[ate, %d]: sc is NULL!", __LINE__)); 1286 ATE_ASSERT_LOCKED(sc); 1287 ifp = sc->ifp; 1288 1289 /* Wipe out old filter settings. */ 1290 reg = RD4(sc, ETH_CFG); 1291 reg &= ~(ETH_CFG_CAF | ETH_CFG_MTI | ETH_CFG_UNI); 1292 reg |= ETH_CFG_NBC; 1293 sc->flags &= ~ATE_FLAG_MULTICAST; 1294 1295 /* Set new parameters. */ 1296 if ((ifp->if_flags & IFF_BROADCAST) != 0) 1297 reg &= ~ETH_CFG_NBC; 1298 if ((ifp->if_flags & IFF_PROMISC) != 0) { 1299 reg |= ETH_CFG_CAF; 1300 } else { 1301 enabled = ate_setmcast(sc); 1302 if (enabled != 0) { 1303 reg |= ETH_CFG_MTI; 1304 sc->flags |= ATE_FLAG_MULTICAST; 1305 } 1306 } 1307 WR4(sc, ETH_CFG, reg); 1308} 1309 1310static int 1311ateioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1312{ 1313 struct ate_softc *sc = ifp->if_softc; 1314 struct mii_data *mii; 1315 struct ifreq *ifr = (struct ifreq *)data; 1316 int drv_flags, flags; 1317 int mask, error, enabled; 1318 1319 error = 0; 1320 flags = ifp->if_flags; 1321 drv_flags = ifp->if_drv_flags; 1322 switch (cmd) { 1323 case SIOCSIFFLAGS: 1324 ATE_LOCK(sc); 1325 if ((flags & IFF_UP) != 0) { 1326 if ((drv_flags & IFF_DRV_RUNNING) != 0) { 1327 if (((flags ^ sc->if_flags) 1328 & (IFF_PROMISC | IFF_ALLMULTI)) != 0) 1329 ate_rxfilter(sc); 1330 } else { 1331 if ((sc->flags & ATE_FLAG_DETACHING) == 0) 1332 ateinit_locked(sc); 1333 } 1334 } else if ((drv_flags & IFF_DRV_RUNNING) != 0) { 1335 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1336 atestop(sc); 1337 } 1338 sc->if_flags = flags; 1339 ATE_UNLOCK(sc); 1340 break; 1341 1342 case SIOCADDMULTI: 1343 case SIOCDELMULTI: 1344 if ((drv_flags & IFF_DRV_RUNNING) != 0) { 1345 ATE_LOCK(sc); 1346 enabled = ate_setmcast(sc); 1347 if (enabled != (sc->flags & ATE_FLAG_MULTICAST)) 1348 ate_rxfilter(sc); 1349 ATE_UNLOCK(sc); 1350 } 1351 break; 1352 1353 case SIOCSIFMEDIA: 1354 case SIOCGIFMEDIA: 1355 mii = device_get_softc(sc->miibus); 1356 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 1357 break; 1358 case SIOCSIFCAP: 1359 mask = ifp->if_capenable ^ ifr->ifr_reqcap; 1360 if (mask & IFCAP_VLAN_MTU) { 1361 ATE_LOCK(sc); 1362 if (ifr->ifr_reqcap & IFCAP_VLAN_MTU) { 1363 WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) | ETH_CFG_BIG); 1364 ifp->if_capenable |= IFCAP_VLAN_MTU; 1365 } else { 1366 WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) & ~ETH_CFG_BIG); 1367 ifp->if_capenable &= ~IFCAP_VLAN_MTU; 1368 } 1369 ATE_UNLOCK(sc); 1370 } 1371 default: 1372 error = ether_ioctl(ifp, cmd, data); 1373 break; 1374 } 1375 return (error); 1376} 1377 1378static void 1379ate_child_detached(device_t dev, device_t child) 1380{ 1381 struct ate_softc *sc; 1382 1383 sc = device_get_softc(dev); 1384 if (child == sc->miibus) 1385 sc->miibus = NULL; 1386} 1387 1388/* 1389 * MII bus support routines. 1390 */ 1391static int 1392ate_miibus_readreg(device_t dev, int phy, int reg) 1393{ 1394 struct ate_softc *sc; 1395 int val; 1396 1397 /* 1398 * XXX if we implement agressive power savings, then we need 1399 * XXX to make sure that the clock to the emac is on here 1400 */ 1401 1402 sc = device_get_softc(dev); 1403 DELAY(1); /* Hangs w/o this delay really 30.5us atm */ 1404 WR4(sc, ETH_MAN, ETH_MAN_REG_RD(phy, reg)); 1405 while ((RD4(sc, ETH_SR) & ETH_SR_IDLE) == 0) 1406 continue; 1407 val = RD4(sc, ETH_MAN) & ETH_MAN_VALUE_MASK; 1408 1409 return (val); 1410} 1411 1412static int 1413ate_miibus_writereg(device_t dev, int phy, int reg, int data) 1414{ 1415 struct ate_softc *sc; 1416 1417 /* 1418 * XXX if we implement agressive power savings, then we need 1419 * XXX to make sure that the clock to the emac is on here 1420 */ 1421 1422 sc = device_get_softc(dev); 1423 WR4(sc, ETH_MAN, ETH_MAN_REG_WR(phy, reg, data)); 1424 while ((RD4(sc, ETH_SR) & ETH_SR_IDLE) == 0) 1425 continue; 1426 return (0); 1427} 1428 1429static device_method_t ate_methods[] = { 1430 /* Device interface */ 1431 DEVMETHOD(device_probe, ate_probe), 1432 DEVMETHOD(device_attach, ate_attach), 1433 DEVMETHOD(device_detach, ate_detach), 1434 1435 /* Bus interface */ 1436 DEVMETHOD(bus_child_detached, ate_child_detached), 1437 1438 /* MII interface */ 1439 DEVMETHOD(miibus_readreg, ate_miibus_readreg), 1440 DEVMETHOD(miibus_writereg, ate_miibus_writereg), 1441 1442 DEVMETHOD_END 1443}; 1444 1445static driver_t ate_driver = { 1446 "ate", 1447 ate_methods, 1448 sizeof(struct ate_softc), 1449}; 1450 1451DRIVER_MODULE(ate, atmelarm, ate_driver, ate_devclass, NULL, NULL); 1452DRIVER_MODULE(miibus, ate, miibus_driver, miibus_devclass, NULL, NULL); 1453MODULE_DEPEND(ate, miibus, 1, 1, 1); 1454MODULE_DEPEND(ate, ether, 1, 1, 1); 1455