if_ate.c revision 213251
1/*- 2 * Copyright (c) 2006 M. Warner Losh. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 */ 25 26/* TODO 27 * 28 * 1) Turn on the clock in pmc? Turn off? 29 * 2) GPIO initializtion in board setup code. 30 */ 31 32#include <sys/cdefs.h> 33__FBSDID("$FreeBSD: head/sys/arm/at91/if_ate.c 213251 2010-09-28 21:13:54Z ticso $"); 34 35#include <sys/param.h> 36#include <sys/systm.h> 37#include <sys/bus.h> 38#include <sys/kernel.h> 39#include <sys/mbuf.h> 40#include <sys/malloc.h> 41#include <sys/module.h> 42#include <sys/rman.h> 43#include <sys/socket.h> 44#include <sys/sockio.h> 45#include <sys/sysctl.h> 46#include <machine/bus.h> 47 48#include <net/ethernet.h> 49#include <net/if.h> 50#include <net/if_arp.h> 51#include <net/if_dl.h> 52#include <net/if_media.h> 53#include <net/if_mib.h> 54#include <net/if_types.h> 55 56#ifdef INET 57#include <netinet/in.h> 58#include <netinet/in_systm.h> 59#include <netinet/in_var.h> 60#include <netinet/ip.h> 61#endif 62 63#include <net/bpf.h> 64#include <net/bpfdesc.h> 65 66#include <dev/mii/mii.h> 67#include <dev/mii/miivar.h> 68#include <arm/at91/if_atereg.h> 69 70#include "miibus_if.h" 71 72#define ATE_MAX_TX_BUFFERS 2 /* We have ping-pong tx buffers */ 73#define ATE_MAX_RX_BUFFERS 64 74 75/* 76 * Driver-specific flags. 77 */ 78#define ATE_FLAG_MULTICAST 0x01 79 80struct ate_softc 81{ 82 struct ifnet *ifp; /* ifnet pointer */ 83 struct mtx sc_mtx; /* Basically a perimeter lock */ 84 device_t dev; /* Myself */ 85 device_t miibus; /* My child miibus */ 86 struct resource *irq_res; /* IRQ resource */ 87 struct resource *mem_res; /* Memory resource */ 88 struct callout tick_ch; /* Tick callout */ 89 struct ifmib_iso_8802_3 mibdata; /* Stuff for network mgmt */ 90 struct mbuf *sent_mbuf[ATE_MAX_TX_BUFFERS]; /* Sent mbufs */ 91 bus_dma_tag_t mtag; /* bus dma tag for mbufs */ 92 bus_dma_tag_t rxtag; 93 bus_dma_tag_t rx_desc_tag; 94 bus_dmamap_t rx_desc_map; 95 bus_dmamap_t rx_map[ATE_MAX_RX_BUFFERS]; 96 bus_dmamap_t tx_map[ATE_MAX_TX_BUFFERS]; 97 bus_addr_t rx_desc_phys; 98 eth_rx_desc_t *rx_descs; 99 void *rx_buf[ATE_MAX_RX_BUFFERS]; /* RX buffer space */ 100 void *intrhand; /* Interrupt handle */ 101 int flags; 102 int if_flags; 103 int rx_buf_ptr; 104 int txcur; /* Current TX map pointer */ 105 int use_rmii; 106}; 107 108static inline uint32_t 109RD4(struct ate_softc *sc, bus_size_t off) 110{ 111 112 return (bus_read_4(sc->mem_res, off)); 113} 114 115static inline void 116WR4(struct ate_softc *sc, bus_size_t off, uint32_t val) 117{ 118 119 bus_write_4(sc->mem_res, off, val); 120} 121 122static inline void 123BARRIER(struct ate_softc *sc, bus_size_t off, bus_size_t len, int flags) 124{ 125 126 bus_barrier(sc->mem_res, off, len, flags); 127} 128 129#define ATE_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 130#define ATE_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 131#define ATE_LOCK_INIT(_sc) \ 132 mtx_init(&_sc->sc_mtx, device_get_nameunit(_sc->dev), \ 133 MTX_NETWORK_LOCK, MTX_DEF) 134#define ATE_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx); 135#define ATE_ASSERT_LOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_OWNED); 136#define ATE_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_NOTOWNED); 137 138static devclass_t ate_devclass; 139 140/* 141 * ifnet entry points. 142 */ 143static void ateinit_locked(void *); 144static void atestart_locked(struct ifnet *); 145 146static void ateinit(void *); 147static void atestart(struct ifnet *); 148static void atestop(struct ate_softc *); 149static int ateioctl(struct ifnet * ifp, u_long, caddr_t); 150 151/* 152 * Bus entry points. 153 */ 154static int ate_probe(device_t dev); 155static int ate_attach(device_t dev); 156static int ate_detach(device_t dev); 157static void ate_intr(void *); 158 159/* 160 * Helper routines. 161 */ 162static int ate_activate(device_t dev); 163static void ate_deactivate(struct ate_softc *sc); 164static int ate_ifmedia_upd(struct ifnet *ifp); 165static void ate_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr); 166static int ate_get_mac(struct ate_softc *sc, u_char *eaddr); 167static void ate_set_mac(struct ate_softc *sc, u_char *eaddr); 168static void ate_rxfilter(struct ate_softc *sc); 169 170/* 171 * The AT91 family of products has the ethernet called EMAC. However, 172 * it isn't self identifying. It is anticipated that the parent bus 173 * code will take care to only add ate devices where they really are. As 174 * such, we do nothing here to identify the device and just set its name. 175 */ 176static int 177ate_probe(device_t dev) 178{ 179 180 device_set_desc(dev, "EMAC"); 181 return (0); 182} 183 184static int 185ate_attach(device_t dev) 186{ 187 struct ate_softc *sc; 188 struct ifnet *ifp = NULL; 189 struct sysctl_ctx_list *sctx; 190 struct sysctl_oid *soid; 191 u_char eaddr[ETHER_ADDR_LEN]; 192 uint32_t rnd; 193 int rid, err; 194 195 sc = device_get_softc(dev); 196 sc->dev = dev; 197 ATE_LOCK_INIT(sc); 198 callout_init_mtx(&sc->tick_ch, &sc->sc_mtx, 0); 199 200 /* 201 * Allocate resources. 202 */ 203 rid = 0; 204 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 205 RF_ACTIVE); 206 if (sc->mem_res == NULL) { 207 device_printf(dev, "could not allocate memory resources.\n"); 208 err = ENOMEM; 209 goto out; 210 } 211 rid = 0; 212 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 213 RF_ACTIVE); 214 if (sc->irq_res == NULL) { 215 device_printf(dev, "could not allocate interrupt resources.\n"); 216 err = ENOMEM; 217 goto out; 218 } 219 220 err = ate_activate(dev); 221 if (err) 222 goto out; 223 224 sc->use_rmii = (RD4(sc, ETH_CFG) & ETH_CFG_RMII) == ETH_CFG_RMII; 225 226 /* Sysctls */ 227 sctx = device_get_sysctl_ctx(dev); 228 soid = device_get_sysctl_tree(dev); 229 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "rmii", 230 CTLFLAG_RD, &sc->use_rmii, 0, "rmii in use"); 231 232 /* Calling atestop before ifp is set is OK. */ 233 ATE_LOCK(sc); 234 atestop(sc); 235 ATE_UNLOCK(sc); 236 237 if ((err = ate_get_mac(sc, eaddr)) != 0) { 238 /* 239 * No MAC address configured. Generate the random one. 240 */ 241 if (bootverbose) 242 device_printf(dev, 243 "Generating random ethernet address.\n"); 244 rnd = arc4random(); 245 246 /* 247 * Set OUI to convenient locally assigned address. 'b' 248 * is 0x62, which has the locally assigned bit set, and 249 * the broadcast/multicast bit clear. 250 */ 251 eaddr[0] = 'b'; 252 eaddr[1] = 's'; 253 eaddr[2] = 'd'; 254 eaddr[3] = (rnd >> 16) & 0xff; 255 eaddr[4] = (rnd >> 8) & 0xff; 256 eaddr[5] = rnd & 0xff; 257 } 258 259 sc->ifp = ifp = if_alloc(IFT_ETHER); 260 if (mii_phy_probe(dev, &sc->miibus, ate_ifmedia_upd, ate_ifmedia_sts)) { 261 device_printf(dev, "Cannot find my PHY.\n"); 262 err = ENXIO; 263 goto out; 264 } 265 266 ifp->if_softc = sc; 267 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 268 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 269 ifp->if_capabilities |= IFCAP_VLAN_MTU; 270 ifp->if_capenable |= IFCAP_VLAN_MTU; /* The hw bits already set. */ 271 ifp->if_start = atestart; 272 ifp->if_ioctl = ateioctl; 273 ifp->if_init = ateinit; 274 ifp->if_baudrate = 10000000; 275 IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen); 276 ifp->if_snd.ifq_drv_maxlen = ifqmaxlen; 277 IFQ_SET_READY(&ifp->if_snd); 278 ifp->if_linkmib = &sc->mibdata; 279 ifp->if_linkmiblen = sizeof(sc->mibdata); 280 sc->mibdata.dot3Compliance = DOT3COMPLIANCE_COLLS; 281 sc->if_flags = ifp->if_flags; 282 283 ether_ifattach(ifp, eaddr); 284 285 /* 286 * Activate the interrupt. 287 */ 288 err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_NET | INTR_MPSAFE, 289 NULL, ate_intr, sc, &sc->intrhand); 290 if (err) { 291 device_printf(dev, "could not establish interrupt handler.\n"); 292 ether_ifdetach(ifp); 293 goto out; 294 } 295 296out: 297 if (err) 298 ate_detach(dev); 299 return (err); 300} 301 302static int 303ate_detach(device_t dev) 304{ 305 struct ate_softc *sc; 306 struct ifnet *ifp; 307 308 sc = device_get_softc(dev); 309 KASSERT(sc != NULL, ("[ate: %d]: sc is NULL", __LINE__)); 310 ifp = sc->ifp; 311 if (device_is_attached(dev)) { 312 ether_ifdetach(ifp); 313 ATE_LOCK(sc); 314 atestop(sc); 315 ATE_UNLOCK(sc); 316 callout_drain(&sc->tick_ch); 317 } 318 if (sc->miibus != NULL) { 319 device_delete_child(dev, sc->miibus); 320 sc->miibus = NULL; 321 } 322 bus_generic_detach(sc->dev); 323 ate_deactivate(sc); 324 if (sc->intrhand != NULL) { 325 bus_teardown_intr(dev, sc->irq_res, sc->intrhand); 326 sc->intrhand = NULL; 327 } 328 if (ifp != NULL) { 329 if_free(ifp); 330 sc->ifp = NULL; 331 } 332 if (sc->mem_res != NULL) { 333 bus_release_resource(dev, SYS_RES_IOPORT, 334 rman_get_rid(sc->mem_res), sc->mem_res); 335 sc->mem_res = NULL; 336 } 337 if (sc->irq_res != NULL) { 338 bus_release_resource(dev, SYS_RES_IRQ, 339 rman_get_rid(sc->irq_res), sc->irq_res); 340 sc->irq_res = NULL; 341 } 342 ATE_LOCK_DESTROY(sc); 343 return (0); 344} 345 346static void 347ate_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 348{ 349 struct ate_softc *sc; 350 351 if (error != 0) 352 return; 353 sc = (struct ate_softc *)arg; 354 sc->rx_desc_phys = segs[0].ds_addr; 355} 356 357static void 358ate_load_rx_buf(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 359{ 360 struct ate_softc *sc; 361 int i; 362 363 if (error != 0) 364 return; 365 sc = (struct ate_softc *)arg; 366 i = sc->rx_buf_ptr; 367 368 /* 369 * For the last buffer, set the wrap bit so the controller 370 * restarts from the first descriptor. 371 */ 372 bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, BUS_DMASYNC_PREWRITE); 373 if (i == ATE_MAX_RX_BUFFERS - 1) 374 sc->rx_descs[i].addr = segs[0].ds_addr | ETH_WRAP_BIT; 375 else 376 sc->rx_descs[i].addr = segs[0].ds_addr; 377 bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, BUS_DMASYNC_POSTWRITE); 378 sc->rx_descs[i].status = 0; 379 /* Flush the memory in the mbuf */ 380 bus_dmamap_sync(sc->rxtag, sc->rx_map[i], BUS_DMASYNC_PREREAD); 381} 382 383static uint32_t 384ate_mac_hash(const uint8_t *buf) 385{ 386 uint32_t index = 0; 387 for (int i = 0; i < 48; i++) { 388 index ^= ((buf[i >> 3] >> (i & 7)) & 1) << (i % 6); 389 } 390 return (index); 391} 392 393/* 394 * Compute the multicast filter for this device. 395 */ 396static int 397ate_setmcast(struct ate_softc *sc) 398{ 399 uint32_t index; 400 uint32_t mcaf[2]; 401 u_char *af = (u_char *) mcaf; 402 struct ifmultiaddr *ifma; 403 struct ifnet *ifp; 404 405 ifp = sc->ifp; 406 407 if ((ifp->if_flags & IFF_PROMISC) != 0) 408 return (0); 409 if ((ifp->if_flags & IFF_ALLMULTI) != 0) { 410 WR4(sc, ETH_HSL, 0xffffffff); 411 WR4(sc, ETH_HSH, 0xffffffff); 412 return (1); 413 } 414 415 /* 416 * Compute the multicast hash. 417 */ 418 mcaf[0] = 0; 419 mcaf[1] = 0; 420 if_maddr_rlock(ifp); 421 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 422 if (ifma->ifma_addr->sa_family != AF_LINK) 423 continue; 424 index = ate_mac_hash(LLADDR((struct sockaddr_dl *) 425 ifma->ifma_addr)); 426 af[index >> 3] |= 1 << (index & 7); 427 } 428 if_maddr_runlock(ifp); 429 430 /* 431 * Write the hash to the hash register. This card can also 432 * accept unicast packets as well as multicast packets using this 433 * register for easier bridging operations, but we don't take 434 * advantage of that. Locks here are to avoid LOR with the 435 * if_maddr_rlock, but might not be strictly necessary. 436 */ 437 WR4(sc, ETH_HSL, mcaf[0]); 438 WR4(sc, ETH_HSH, mcaf[1]); 439 return (mcaf[0] || mcaf[1]); 440} 441 442static int 443ate_activate(device_t dev) 444{ 445 struct ate_softc *sc; 446 int err, i; 447 448 sc = device_get_softc(dev); 449 450 /* 451 * Allocate DMA tags and maps. 452 */ 453 err = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0, 454 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 455 1, MCLBYTES, 0, busdma_lock_mutex, &sc->sc_mtx, &sc->mtag); 456 if (err != 0) 457 goto errout; 458 for (i = 0; i < ATE_MAX_TX_BUFFERS; i++) { 459 err = bus_dmamap_create(sc->mtag, 0, &sc->tx_map[i]); 460 if (err != 0) 461 goto errout; 462 } 463 464 /* 465 * Allocate DMA tags and maps for RX. 466 */ 467 err = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0, 468 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 469 1, MCLBYTES, 0, busdma_lock_mutex, &sc->sc_mtx, &sc->rxtag); 470 if (err != 0) 471 goto errout; 472 473 /* 474 * DMA tag and map for the RX descriptors. 475 */ 476 err = bus_dma_tag_create(bus_get_dma_tag(dev), sizeof(eth_rx_desc_t), 477 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 478 ATE_MAX_RX_BUFFERS * sizeof(eth_rx_desc_t), 1, 479 ATE_MAX_RX_BUFFERS * sizeof(eth_rx_desc_t), 0, busdma_lock_mutex, 480 &sc->sc_mtx, &sc->rx_desc_tag); 481 if (err != 0) 482 goto errout; 483 if (bus_dmamem_alloc(sc->rx_desc_tag, (void **)&sc->rx_descs, 484 BUS_DMA_NOWAIT | BUS_DMA_COHERENT, &sc->rx_desc_map) != 0) 485 goto errout; 486 if (bus_dmamap_load(sc->rx_desc_tag, sc->rx_desc_map, 487 sc->rx_descs, ATE_MAX_RX_BUFFERS * sizeof(eth_rx_desc_t), 488 ate_getaddr, sc, 0) != 0) 489 goto errout; 490 491 /* 492 * Allocate our RX buffers. This chip has a RX structure that's filled 493 * in. 494 */ 495 for (i = 0; i < ATE_MAX_RX_BUFFERS; i++) { 496 sc->rx_buf_ptr = i; 497 if (bus_dmamem_alloc(sc->rxtag, (void **)&sc->rx_buf[i], 498 BUS_DMA_NOWAIT, &sc->rx_map[i]) != 0) 499 goto errout; 500 if (bus_dmamap_load(sc->rxtag, sc->rx_map[i], sc->rx_buf[i], 501 MCLBYTES, ate_load_rx_buf, sc, 0) != 0) 502 goto errout; 503 } 504 sc->rx_buf_ptr = 0; 505 /* Flush the memory for the EMAC rx descriptor. */ 506 bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, BUS_DMASYNC_PREWRITE); 507 /* Write the descriptor queue address. */ 508 WR4(sc, ETH_RBQP, sc->rx_desc_phys); 509 return (0); 510 511errout: 512 return (ENOMEM); 513} 514 515static void 516ate_deactivate(struct ate_softc *sc) 517{ 518 int i; 519 520 KASSERT(sc != NULL, ("[ate, %d]: sc is NULL!", __LINE__)); 521 if (sc->mtag != NULL) { 522 for (i = 0; i < ATE_MAX_TX_BUFFERS; i++) { 523 if (sc->sent_mbuf[i] != NULL) { 524 bus_dmamap_sync(sc->mtag, sc->tx_map[i], 525 BUS_DMASYNC_POSTWRITE); 526 bus_dmamap_unload(sc->mtag, sc->tx_map[i]); 527 m_freem(sc->sent_mbuf[i]); 528 } 529 bus_dmamap_destroy(sc->mtag, sc->tx_map[i]); 530 sc->sent_mbuf[i] = NULL; 531 sc->tx_map[i] = NULL; 532 } 533 bus_dma_tag_destroy(sc->mtag); 534 } 535 if (sc->rx_desc_tag != NULL) { 536 if (sc->rx_descs != NULL) { 537 if (sc->rx_desc_phys != 0) { 538 bus_dmamap_sync(sc->rx_desc_tag, 539 sc->rx_desc_map, BUS_DMASYNC_POSTREAD); 540 bus_dmamap_unload(sc->rx_desc_tag, 541 sc->rx_desc_map); 542 sc->rx_desc_phys = 0; 543 } 544 } 545 } 546 if (sc->rxtag != NULL) { 547 for (i = 0; i < ATE_MAX_RX_BUFFERS; i++) { 548 if (sc->rx_buf[i] != NULL) { 549 if (sc->rx_descs[i].addr != 0) { 550 bus_dmamap_sync(sc->rxtag, 551 sc->rx_map[i], 552 BUS_DMASYNC_POSTREAD); 553 bus_dmamap_unload(sc->rxtag, 554 sc->rx_map[i]); 555 sc->rx_descs[i].addr = 0; 556 } 557 bus_dmamem_free(sc->rxtag, sc->rx_buf[i], 558 sc->rx_map[i]); 559 sc->rx_buf[i] = NULL; 560 sc->rx_map[i] = NULL; 561 } 562 } 563 bus_dma_tag_destroy(sc->rxtag); 564 } 565 if (sc->rx_desc_tag != NULL) { 566 if (sc->rx_descs != NULL) 567 bus_dmamem_free(sc->rx_desc_tag, sc->rx_descs, 568 sc->rx_desc_map); 569 bus_dma_tag_destroy(sc->rx_desc_tag); 570 sc->rx_descs = NULL; 571 sc->rx_desc_tag = NULL; 572 } 573} 574 575/* 576 * Change media according to request. 577 */ 578static int 579ate_ifmedia_upd(struct ifnet *ifp) 580{ 581 struct ate_softc *sc = ifp->if_softc; 582 struct mii_data *mii; 583 584 mii = device_get_softc(sc->miibus); 585 ATE_LOCK(sc); 586 mii_mediachg(mii); 587 ATE_UNLOCK(sc); 588 return (0); 589} 590 591/* 592 * Notify the world which media we're using. 593 */ 594static void 595ate_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 596{ 597 struct ate_softc *sc = ifp->if_softc; 598 struct mii_data *mii; 599 600 mii = device_get_softc(sc->miibus); 601 ATE_LOCK(sc); 602 mii_pollstat(mii); 603 ifmr->ifm_active = mii->mii_media_active; 604 ifmr->ifm_status = mii->mii_media_status; 605 ATE_UNLOCK(sc); 606} 607 608static void 609ate_stat_update(struct ate_softc *sc, int active) 610{ 611 uint32_t reg; 612 613 /* 614 * The speed and full/half-duplex state needs to be reflected 615 * in the ETH_CFG register. 616 */ 617 reg = RD4(sc, ETH_CFG); 618 reg &= ~(ETH_CFG_SPD | ETH_CFG_FD); 619 if (IFM_SUBTYPE(active) != IFM_10_T) 620 reg |= ETH_CFG_SPD; 621 if (active & IFM_FDX) 622 reg |= ETH_CFG_FD; 623 WR4(sc, ETH_CFG, reg); 624} 625 626static void 627ate_tick(void *xsc) 628{ 629 struct ate_softc *sc = xsc; 630 struct ifnet *ifp = sc->ifp; 631 struct mii_data *mii; 632 int active; 633 uint32_t c; 634 635 /* 636 * The KB920x boot loader tests ETH_SR & ETH_SR_LINK and will ask 637 * the MII if there's a link if this bit is clear. Not sure if we 638 * should do the same thing here or not. 639 */ 640 ATE_ASSERT_LOCKED(sc); 641 if (sc->miibus != NULL) { 642 mii = device_get_softc(sc->miibus); 643 active = mii->mii_media_active; 644 mii_tick(mii); 645 if (mii->mii_media_status & IFM_ACTIVE && 646 active != mii->mii_media_active) 647 ate_stat_update(sc, mii->mii_media_active); 648 } 649 650 /* 651 * Update the stats as best we can. When we're done, clear 652 * the status counters and start over. We're supposed to read these 653 * registers often enough that they won't overflow. Hopefully 654 * once a second is often enough. Some don't map well to 655 * the dot3Stats mib, so for those we just count them as general 656 * errors. Stats for iframes, ibutes, oframes and obytes are 657 * collected elsewhere. These registers zero on a read to prevent 658 * races. For all the collision stats, also update the collision 659 * stats for the interface. 660 */ 661 sc->mibdata.dot3StatsAlignmentErrors += RD4(sc, ETH_ALE); 662 sc->mibdata.dot3StatsFCSErrors += RD4(sc, ETH_SEQE); 663 c = RD4(sc, ETH_SCOL); 664 ifp->if_collisions += c; 665 sc->mibdata.dot3StatsSingleCollisionFrames += c; 666 c = RD4(sc, ETH_MCOL); 667 sc->mibdata.dot3StatsMultipleCollisionFrames += c; 668 ifp->if_collisions += c; 669 sc->mibdata.dot3StatsSQETestErrors += RD4(sc, ETH_SQEE); 670 sc->mibdata.dot3StatsDeferredTransmissions += RD4(sc, ETH_DTE); 671 c = RD4(sc, ETH_LCOL); 672 sc->mibdata.dot3StatsLateCollisions += c; 673 ifp->if_collisions += c; 674 c = RD4(sc, ETH_ECOL); 675 sc->mibdata.dot3StatsExcessiveCollisions += c; 676 ifp->if_collisions += c; 677 sc->mibdata.dot3StatsCarrierSenseErrors += RD4(sc, ETH_CSE); 678 sc->mibdata.dot3StatsFrameTooLongs += RD4(sc, ETH_ELR); 679 sc->mibdata.dot3StatsInternalMacReceiveErrors += RD4(sc, ETH_DRFC); 680 681 /* 682 * Not sure where to lump these, so count them against the errors 683 * for the interface. 684 */ 685 sc->ifp->if_oerrors += RD4(sc, ETH_TUE); 686 sc->ifp->if_ierrors += RD4(sc, ETH_CDE) + RD4(sc, ETH_RJB) + 687 RD4(sc, ETH_USF); 688 689 /* 690 * Schedule another timeout one second from now. 691 */ 692 callout_reset(&sc->tick_ch, hz, ate_tick, sc); 693} 694 695static void 696ate_set_mac(struct ate_softc *sc, u_char *eaddr) 697{ 698 699 WR4(sc, ETH_SA1L, (eaddr[3] << 24) | (eaddr[2] << 16) | 700 (eaddr[1] << 8) | eaddr[0]); 701 WR4(sc, ETH_SA1H, (eaddr[5] << 8) | (eaddr[4])); 702} 703 704static int 705ate_get_mac(struct ate_softc *sc, u_char *eaddr) 706{ 707 bus_size_t sa_low_reg[] = { ETH_SA1L, ETH_SA2L, ETH_SA3L, ETH_SA4L }; 708 bus_size_t sa_high_reg[] = { ETH_SA1H, ETH_SA2H, ETH_SA3H, ETH_SA4H }; 709 uint32_t low, high; 710 int i; 711 712 /* 713 * The boot loader setup the MAC with an address, if one is set in 714 * the loader. Grab one MAC address from the SA[1-4][HL] registers. 715 */ 716 for (i = 0; i < 4; i++) { 717 low = RD4(sc, sa_low_reg[i]); 718 high = RD4(sc, sa_high_reg[i]); 719 if ((low | (high & 0xffff)) != 0) { 720 eaddr[0] = low & 0xff; 721 eaddr[1] = (low >> 8) & 0xff; 722 eaddr[2] = (low >> 16) & 0xff; 723 eaddr[3] = (low >> 24) & 0xff; 724 eaddr[4] = high & 0xff; 725 eaddr[5] = (high >> 8) & 0xff; 726 return (0); 727 } 728 } 729 return (ENXIO); 730} 731 732static void 733ate_intr(void *xsc) 734{ 735 struct ate_softc *sc = xsc; 736 struct ifnet *ifp = sc->ifp; 737 struct mbuf *mb; 738 void *bp; 739 uint32_t status, reg, rx_stat; 740 int i; 741 742 status = RD4(sc, ETH_ISR); 743 if (status == 0) 744 return; 745 if (status & ETH_ISR_RCOM) { 746 bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, 747 BUS_DMASYNC_POSTREAD); 748 while (sc->rx_descs[sc->rx_buf_ptr].addr & ETH_CPU_OWNER) { 749 i = sc->rx_buf_ptr; 750 sc->rx_buf_ptr = (i + 1) % ATE_MAX_RX_BUFFERS; 751 bp = sc->rx_buf[i]; 752 rx_stat = sc->rx_descs[i].status; 753 if ((rx_stat & ETH_LEN_MASK) == 0) { 754 if (bootverbose) 755 device_printf(sc->dev, "ignoring bogus zero-length packet\n"); 756 bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, 757 BUS_DMASYNC_PREWRITE); 758 sc->rx_descs[i].addr &= ~ETH_CPU_OWNER; 759 bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, 760 BUS_DMASYNC_POSTWRITE); 761 continue; 762 } 763 /* Flush memory for mbuf so we don't get stale bytes */ 764 bus_dmamap_sync(sc->rxtag, sc->rx_map[i], 765 BUS_DMASYNC_POSTREAD); 766 WR4(sc, ETH_RSR, RD4(sc, ETH_RSR)); 767 768 /* 769 * The length returned by the device includes the 770 * ethernet CRC calculation for the packet, but 771 * ifnet drivers are supposed to discard it. 772 */ 773 mb = m_devget(sc->rx_buf[i], 774 (rx_stat & ETH_LEN_MASK) - ETHER_CRC_LEN, 775 ETHER_ALIGN, ifp, NULL); 776 bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, 777 BUS_DMASYNC_PREWRITE); 778 sc->rx_descs[i].addr &= ~ETH_CPU_OWNER; 779 bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, 780 BUS_DMASYNC_POSTWRITE); 781 bus_dmamap_sync(sc->rxtag, sc->rx_map[i], 782 BUS_DMASYNC_PREREAD); 783 if (mb != NULL) { 784 ifp->if_ipackets++; 785 (*ifp->if_input)(ifp, mb); 786 } 787 788 } 789 } 790 if (status & ETH_ISR_TCOM) { 791 ATE_LOCK(sc); 792 /* XXX TSR register should be cleared */ 793 if (sc->sent_mbuf[0]) { 794 bus_dmamap_sync(sc->mtag, sc->tx_map[0], 795 BUS_DMASYNC_POSTWRITE); 796 bus_dmamap_unload(sc->mtag, sc->tx_map[0]); 797 m_freem(sc->sent_mbuf[0]); 798 ifp->if_opackets++; 799 sc->sent_mbuf[0] = NULL; 800 } 801 if (sc->sent_mbuf[1]) { 802 if (RD4(sc, ETH_TSR) & ETH_TSR_IDLE) { 803 bus_dmamap_sync(sc->mtag, sc->tx_map[1], 804 BUS_DMASYNC_POSTWRITE); 805 bus_dmamap_unload(sc->mtag, sc->tx_map[1]); 806 m_freem(sc->sent_mbuf[1]); 807 ifp->if_opackets++; 808 sc->txcur = 0; 809 sc->sent_mbuf[0] = sc->sent_mbuf[1] = NULL; 810 } else { 811 sc->sent_mbuf[0] = sc->sent_mbuf[1]; 812 sc->sent_mbuf[1] = NULL; 813 sc->txcur = 1; 814 } 815 } else { 816 sc->sent_mbuf[0] = NULL; 817 sc->txcur = 0; 818 } 819 /* 820 * We're no longer busy, so clear the busy flag and call the 821 * start routine to xmit more packets. 822 */ 823 sc->ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 824 atestart_locked(sc->ifp); 825 ATE_UNLOCK(sc); 826 } 827 if (status & ETH_ISR_RBNA) { 828 /* Workaround Errata #11 */ 829 if (bootverbose) 830 device_printf(sc->dev, "RBNA workaround\n"); 831 reg = RD4(sc, ETH_CTL); 832 WR4(sc, ETH_CTL, reg & ~ETH_CTL_RE); 833 BARRIER(sc, ETH_CTL, 4, BUS_SPACE_BARRIER_WRITE); 834 WR4(sc, ETH_CTL, reg | ETH_CTL_RE); 835 } 836} 837 838/* 839 * Reset and initialize the chip. 840 */ 841static void 842ateinit_locked(void *xsc) 843{ 844 struct ate_softc *sc = xsc; 845 struct ifnet *ifp = sc->ifp; 846 struct mii_data *mii; 847 uint8_t eaddr[ETHER_ADDR_LEN]; 848 uint32_t reg; 849 850 ATE_ASSERT_LOCKED(sc); 851 852 /* 853 * XXX TODO(3) 854 * we need to turn on the EMAC clock in the pmc. With the 855 * default boot loader, this is already turned on. However, we 856 * need to think about how best to turn it on/off as the interface 857 * is brought up/down, as well as dealing with the mii bus... 858 * 859 * We also need to multiplex the pins correctly. 860 */ 861 862 /* 863 * There are two different ways that the mii bus is connected 864 * to this chip. Select the right one based on a compile-time 865 * option. 866 */ 867 reg = RD4(sc, ETH_CFG); 868 if (sc->use_rmii) 869 reg |= ETH_CFG_RMII; 870 else 871 reg &= ~ETH_CFG_RMII; 872 WR4(sc, ETH_CFG, reg); 873 874 ate_rxfilter(sc); 875 876 /* 877 * Set the chip MAC address. 878 */ 879 bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN); 880 ate_set_mac(sc, eaddr); 881 882 /* 883 * Turn on MACs and interrupt processing. 884 */ 885 WR4(sc, ETH_CTL, RD4(sc, ETH_CTL) | ETH_CTL_TE | ETH_CTL_RE); 886 WR4(sc, ETH_IER, ETH_ISR_RCOM | ETH_ISR_TCOM | ETH_ISR_RBNA); 887 888 /* Enable big packets. */ 889 WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) | ETH_CFG_BIG); 890 891 /* 892 * Set 'running' flag, and clear output active flag 893 * and attempt to start the output. 894 */ 895 ifp->if_drv_flags |= IFF_DRV_RUNNING; 896 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 897 898 mii = device_get_softc(sc->miibus); 899 mii_pollstat(mii); 900 ate_stat_update(sc, mii->mii_media_active); 901 atestart_locked(ifp); 902 903 callout_reset(&sc->tick_ch, hz, ate_tick, sc); 904} 905 906/* 907 * Dequeue packets and transmit. 908 */ 909static void 910atestart_locked(struct ifnet *ifp) 911{ 912 struct ate_softc *sc = ifp->if_softc; 913 struct mbuf *m, *mdefrag; 914 bus_dma_segment_t segs[1]; 915 int nseg, e; 916 917 ATE_ASSERT_LOCKED(sc); 918 if (ifp->if_drv_flags & IFF_DRV_OACTIVE) 919 return; 920 921 while (sc->txcur < ATE_MAX_TX_BUFFERS) { 922 /* 923 * Check to see if there's room to put another packet into the 924 * xmit queue. The EMAC chip has a ping-pong buffer for xmit 925 * packets. We use OACTIVE to indicate "we can stuff more into 926 * our buffers (clear) or not (set)." 927 */ 928 if (!(RD4(sc, ETH_TSR) & ETH_TSR_BNQ)) { 929 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 930 return; 931 } 932 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 933 if (m == 0) { 934 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 935 return; 936 } 937 e = bus_dmamap_load_mbuf_sg(sc->mtag, sc->tx_map[sc->txcur], m, 938 segs, &nseg, 0); 939 if (e == EFBIG) { 940 mdefrag = m_defrag(m, M_DONTWAIT); 941 if (mdefrag == NULL) { 942 IFQ_DRV_PREPEND(&ifp->if_snd, m); 943 return; 944 } 945 m = mdefrag; 946 e = bus_dmamap_load_mbuf_sg(sc->mtag, 947 sc->tx_map[sc->txcur], m, segs, &nseg, 0); 948 } 949 if (e != 0) { 950 m_freem(m); 951 continue; 952 } 953 bus_dmamap_sync(sc->mtag, sc->tx_map[sc->txcur], 954 BUS_DMASYNC_PREWRITE); 955 956 /* 957 * Tell the hardware to xmit the packet. 958 */ 959 WR4(sc, ETH_TAR, segs[0].ds_addr); 960 BARRIER(sc, ETH_TAR, 8, BUS_SPACE_BARRIER_WRITE); 961 WR4(sc, ETH_TCR, segs[0].ds_len); 962 963 /* 964 * Tap off here if there is a bpf listener. 965 */ 966 BPF_MTAP(ifp, m); 967 968 sc->sent_mbuf[sc->txcur] = m; 969 sc->txcur++; 970 } 971} 972 973static void 974ateinit(void *xsc) 975{ 976 struct ate_softc *sc = xsc; 977 978 ATE_LOCK(sc); 979 ateinit_locked(sc); 980 ATE_UNLOCK(sc); 981} 982 983static void 984atestart(struct ifnet *ifp) 985{ 986 struct ate_softc *sc = ifp->if_softc; 987 988 ATE_LOCK(sc); 989 atestart_locked(ifp); 990 ATE_UNLOCK(sc); 991} 992 993/* 994 * Turn off interrupts, and stop the NIC. Can be called with sc->ifp NULL, 995 * so be careful. 996 */ 997static void 998atestop(struct ate_softc *sc) 999{ 1000 struct ifnet *ifp; 1001 int i; 1002 1003 ATE_ASSERT_LOCKED(sc); 1004 ifp = sc->ifp; 1005 if (ifp) { 1006 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1007 } 1008 1009 callout_stop(&sc->tick_ch); 1010 1011 /* 1012 * Enable some parts of the MAC that are needed always (like the 1013 * MII bus. This turns off the RE and TE bits, which will remain 1014 * off until ateinit() is called to turn them on. With RE and TE 1015 * turned off, there's no DMA to worry about after this write. 1016 */ 1017 WR4(sc, ETH_CTL, ETH_CTL_MPE); 1018 1019 /* 1020 * Turn off all the configured options and revert to defaults. 1021 */ 1022 WR4(sc, ETH_CFG, ETH_CFG_CLK_32); 1023 1024 /* 1025 * Turn off all the interrupts, and ack any pending ones by reading 1026 * the ISR. 1027 */ 1028 WR4(sc, ETH_IDR, 0xffffffff); 1029 RD4(sc, ETH_ISR); 1030 1031 /* 1032 * Clear out the Transmit and Receiver Status registers of any 1033 * errors they may be reporting 1034 */ 1035 WR4(sc, ETH_TSR, 0xffffffff); 1036 WR4(sc, ETH_RSR, 0xffffffff); 1037 1038 /* 1039 * Release TX resources. 1040 */ 1041 for (i = 0; i < ATE_MAX_TX_BUFFERS; i++) { 1042 if (sc->sent_mbuf[i] != NULL) { 1043 bus_dmamap_sync(sc->mtag, sc->tx_map[i], 1044 BUS_DMASYNC_POSTWRITE); 1045 bus_dmamap_unload(sc->mtag, sc->tx_map[i]); 1046 m_freem(sc->sent_mbuf[i]); 1047 sc->sent_mbuf[i] = NULL; 1048 } 1049 } 1050 1051 /* 1052 * XXX we should power down the EMAC if it isn't in use, after 1053 * putting it into loopback mode. This saves about 400uA according 1054 * to the datasheet. 1055 */ 1056} 1057 1058static void 1059ate_rxfilter(struct ate_softc *sc) 1060{ 1061 struct ifnet *ifp; 1062 uint32_t reg; 1063 int enabled; 1064 1065 KASSERT(sc != NULL, ("[ate, %d]: sc is NULL!", __LINE__)); 1066 ATE_ASSERT_LOCKED(sc); 1067 ifp = sc->ifp; 1068 1069 /* 1070 * Wipe out old filter settings. 1071 */ 1072 reg = RD4(sc, ETH_CFG); 1073 reg &= ~(ETH_CFG_CAF | ETH_CFG_MTI | ETH_CFG_UNI); 1074 reg |= ETH_CFG_NBC; 1075 sc->flags &= ~ATE_FLAG_MULTICAST; 1076 1077 /* 1078 * Set new parameters. 1079 */ 1080 if ((ifp->if_flags & IFF_BROADCAST) != 0) 1081 reg &= ~ETH_CFG_NBC; 1082 if ((ifp->if_flags & IFF_PROMISC) != 0) { 1083 reg |= ETH_CFG_CAF; 1084 } else { 1085 enabled = ate_setmcast(sc); 1086 if (enabled != 0) { 1087 reg |= ETH_CFG_MTI; 1088 sc->flags |= ATE_FLAG_MULTICAST; 1089 } 1090 } 1091 WR4(sc, ETH_CFG, reg); 1092} 1093 1094static int 1095ateioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1096{ 1097 struct ate_softc *sc = ifp->if_softc; 1098 struct mii_data *mii; 1099 struct ifreq *ifr = (struct ifreq *)data; 1100 int drv_flags, flags; 1101 int mask, error, enabled; 1102 1103 error = 0; 1104 flags = ifp->if_flags; 1105 drv_flags = ifp->if_drv_flags; 1106 switch (cmd) { 1107 case SIOCSIFFLAGS: 1108 ATE_LOCK(sc); 1109 if ((flags & IFF_UP) != 0) { 1110 if ((drv_flags & IFF_DRV_RUNNING) != 0) { 1111 if (((flags ^ sc->if_flags) 1112 & (IFF_PROMISC | IFF_ALLMULTI)) != 0) 1113 ate_rxfilter(sc); 1114 } else { 1115 ateinit_locked(sc); 1116 } 1117 } else if ((drv_flags & IFF_DRV_RUNNING) != 0) { 1118 atestop(sc); 1119 } 1120 sc->if_flags = flags; 1121 ATE_UNLOCK(sc); 1122 break; 1123 1124 case SIOCADDMULTI: 1125 case SIOCDELMULTI: 1126 if ((drv_flags & IFF_DRV_RUNNING) != 0) { 1127 ATE_LOCK(sc); 1128 enabled = ate_setmcast(sc); 1129 if (enabled != (sc->flags & ATE_FLAG_MULTICAST)) 1130 ate_rxfilter(sc); 1131 ATE_UNLOCK(sc); 1132 } 1133 break; 1134 1135 case SIOCSIFMEDIA: 1136 case SIOCGIFMEDIA: 1137 mii = device_get_softc(sc->miibus); 1138 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 1139 break; 1140 case SIOCSIFCAP: 1141 mask = ifp->if_capenable ^ ifr->ifr_reqcap; 1142 if (mask & IFCAP_VLAN_MTU) { 1143 ATE_LOCK(sc); 1144 if (ifr->ifr_reqcap & IFCAP_VLAN_MTU) { 1145 WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) | ETH_CFG_BIG); 1146 ifp->if_capenable |= IFCAP_VLAN_MTU; 1147 } else { 1148 WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) & ~ETH_CFG_BIG); 1149 ifp->if_capenable &= ~IFCAP_VLAN_MTU; 1150 } 1151 ATE_UNLOCK(sc); 1152 } 1153 default: 1154 error = ether_ioctl(ifp, cmd, data); 1155 break; 1156 } 1157 return (error); 1158} 1159 1160static void 1161ate_child_detached(device_t dev, device_t child) 1162{ 1163 struct ate_softc *sc; 1164 1165 sc = device_get_softc(dev); 1166 if (child == sc->miibus) 1167 sc->miibus = NULL; 1168} 1169 1170/* 1171 * MII bus support routines. 1172 */ 1173static int 1174ate_miibus_readreg(device_t dev, int phy, int reg) 1175{ 1176 struct ate_softc *sc; 1177 int val; 1178 1179 /* 1180 * XXX if we implement agressive power savings, then we need 1181 * XXX to make sure that the clock to the emac is on here 1182 */ 1183 1184 sc = device_get_softc(dev); 1185 DELAY(1); /* Hangs w/o this delay really 30.5us atm */ 1186 WR4(sc, ETH_MAN, ETH_MAN_REG_RD(phy, reg)); 1187 while ((RD4(sc, ETH_SR) & ETH_SR_IDLE) == 0) 1188 continue; 1189 val = RD4(sc, ETH_MAN) & ETH_MAN_VALUE_MASK; 1190 1191 return (val); 1192} 1193 1194static int 1195ate_miibus_writereg(device_t dev, int phy, int reg, int data) 1196{ 1197 struct ate_softc *sc; 1198 1199 /* 1200 * XXX if we implement agressive power savings, then we need 1201 * XXX to make sure that the clock to the emac is on here 1202 */ 1203 1204 sc = device_get_softc(dev); 1205 WR4(sc, ETH_MAN, ETH_MAN_REG_WR(phy, reg, data)); 1206 while ((RD4(sc, ETH_SR) & ETH_SR_IDLE) == 0) 1207 continue; 1208 return (0); 1209} 1210 1211static device_method_t ate_methods[] = { 1212 /* Device interface */ 1213 DEVMETHOD(device_probe, ate_probe), 1214 DEVMETHOD(device_attach, ate_attach), 1215 DEVMETHOD(device_detach, ate_detach), 1216 1217 /* Bus interface */ 1218 DEVMETHOD(bus_child_detached, ate_child_detached), 1219 1220 /* MII interface */ 1221 DEVMETHOD(miibus_readreg, ate_miibus_readreg), 1222 DEVMETHOD(miibus_writereg, ate_miibus_writereg), 1223 1224 { 0, 0 } 1225}; 1226 1227static driver_t ate_driver = { 1228 "ate", 1229 ate_methods, 1230 sizeof(struct ate_softc), 1231}; 1232 1233DRIVER_MODULE(ate, atmelarm, ate_driver, ate_devclass, 0, 0); 1234DRIVER_MODULE(miibus, ate, miibus_driver, miibus_devclass, 0, 0); 1235MODULE_DEPEND(ate, miibus, 1, 1, 1); 1236MODULE_DEPEND(ate, ether, 1, 1, 1); 1237