if_ate.c revision 204462
1/*- 2 * Copyright (c) 2006 M. Warner Losh. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 */ 25 26/* TODO 27 * 28 * 1) Turn on the clock in pmc? Turn off? 29 * 2) GPIO initializtion in board setup code. 30 */ 31 32#include <sys/cdefs.h> 33__FBSDID("$FreeBSD: head/sys/arm/at91/if_ate.c 204462 2010-02-28 16:11:13Z ticso $"); 34 35#include <sys/param.h> 36#include <sys/systm.h> 37#include <sys/bus.h> 38#include <sys/kernel.h> 39#include <sys/mbuf.h> 40#include <sys/malloc.h> 41#include <sys/module.h> 42#include <sys/rman.h> 43#include <sys/socket.h> 44#include <sys/sockio.h> 45#include <sys/sysctl.h> 46#include <machine/bus.h> 47 48#include <net/ethernet.h> 49#include <net/if.h> 50#include <net/if_arp.h> 51#include <net/if_dl.h> 52#include <net/if_media.h> 53#include <net/if_mib.h> 54#include <net/if_types.h> 55 56#ifdef INET 57#include <netinet/in.h> 58#include <netinet/in_systm.h> 59#include <netinet/in_var.h> 60#include <netinet/ip.h> 61#endif 62 63#include <net/bpf.h> 64#include <net/bpfdesc.h> 65 66#include <dev/mii/mii.h> 67#include <dev/mii/miivar.h> 68#include <arm/at91/if_atereg.h> 69 70#include "miibus_if.h" 71 72#define ATE_MAX_TX_BUFFERS 2 /* We have ping-pong tx buffers */ 73#define ATE_MAX_RX_BUFFERS 64 74 75/* 76 * Driver-specific flags. 77 */ 78#define ATE_FLAG_MULTICAST 0x01 79 80struct ate_softc 81{ 82 struct ifnet *ifp; /* ifnet pointer */ 83 struct mtx sc_mtx; /* Basically a perimeter lock */ 84 device_t dev; /* Myself */ 85 device_t miibus; /* My child miibus */ 86 struct resource *irq_res; /* IRQ resource */ 87 struct resource *mem_res; /* Memory resource */ 88 struct callout tick_ch; /* Tick callout */ 89 struct ifmib_iso_8802_3 mibdata; /* Stuff for network mgmt */ 90 struct mbuf *sent_mbuf[ATE_MAX_TX_BUFFERS]; /* Sent mbufs */ 91 bus_dma_tag_t mtag; /* bus dma tag for mbufs */ 92 bus_dma_tag_t rxtag; 93 bus_dma_tag_t rx_desc_tag; 94 bus_dmamap_t rx_desc_map; 95 bus_dmamap_t rx_map[ATE_MAX_RX_BUFFERS]; 96 bus_dmamap_t tx_map[ATE_MAX_TX_BUFFERS]; 97 bus_addr_t rx_desc_phys; 98 eth_rx_desc_t *rx_descs; 99 void *rx_buf[ATE_MAX_RX_BUFFERS]; /* RX buffer space */ 100 void *intrhand; /* Interrupt handle */ 101 int flags; 102 int if_flags; 103 int rx_buf_ptr; 104 int txcur; /* Current TX map pointer */ 105 int use_rmii; 106}; 107 108static inline uint32_t 109RD4(struct ate_softc *sc, bus_size_t off) 110{ 111 112 return (bus_read_4(sc->mem_res, off)); 113} 114 115static inline void 116WR4(struct ate_softc *sc, bus_size_t off, uint32_t val) 117{ 118 119 bus_write_4(sc->mem_res, off, val); 120} 121 122static inline void 123BARRIER(struct ate_softc *sc, bus_size_t off, bus_size_t len, int flags) 124{ 125 126 bus_barrier(sc->mem_res, off, len, flags); 127} 128 129#define ATE_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 130#define ATE_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 131#define ATE_LOCK_INIT(_sc) \ 132 mtx_init(&_sc->sc_mtx, device_get_nameunit(_sc->dev), \ 133 MTX_NETWORK_LOCK, MTX_DEF) 134#define ATE_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx); 135#define ATE_ASSERT_LOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_OWNED); 136#define ATE_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_NOTOWNED); 137 138static devclass_t ate_devclass; 139 140/* 141 * ifnet entry points. 142 */ 143static void ateinit_locked(void *); 144static void atestart_locked(struct ifnet *); 145 146static void ateinit(void *); 147static void atestart(struct ifnet *); 148static void atestop(struct ate_softc *); 149static int ateioctl(struct ifnet * ifp, u_long, caddr_t); 150 151/* 152 * Bus entry points. 153 */ 154static int ate_probe(device_t dev); 155static int ate_attach(device_t dev); 156static int ate_detach(device_t dev); 157static void ate_intr(void *); 158 159/* 160 * Helper routines. 161 */ 162static int ate_activate(device_t dev); 163static void ate_deactivate(struct ate_softc *sc); 164static int ate_ifmedia_upd(struct ifnet *ifp); 165static void ate_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr); 166static int ate_get_mac(struct ate_softc *sc, u_char *eaddr); 167static void ate_set_mac(struct ate_softc *sc, u_char *eaddr); 168static void ate_rxfilter(struct ate_softc *sc); 169 170/* 171 * The AT91 family of products has the ethernet called EMAC. However, 172 * it isn't self identifying. It is anticipated that the parent bus 173 * code will take care to only add ate devices where they really are. As 174 * such, we do nothing here to identify the device and just set its name. 175 */ 176static int 177ate_probe(device_t dev) 178{ 179 180 device_set_desc(dev, "EMAC"); 181 return (0); 182} 183 184static int 185ate_attach(device_t dev) 186{ 187 struct ate_softc *sc; 188 struct ifnet *ifp = NULL; 189 struct sysctl_ctx_list *sctx; 190 struct sysctl_oid *soid; 191 u_char eaddr[ETHER_ADDR_LEN]; 192 uint32_t rnd; 193 int rid, err; 194 195 sc = device_get_softc(dev); 196 sc->dev = dev; 197 ATE_LOCK_INIT(sc); 198 callout_init_mtx(&sc->tick_ch, &sc->sc_mtx, 0); 199 200 /* 201 * Allocate resources. 202 */ 203 rid = 0; 204 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 205 RF_ACTIVE); 206 if (sc->mem_res == NULL) { 207 device_printf(dev, "could not allocate memory resources.\n"); 208 err = ENOMEM; 209 goto out; 210 } 211 rid = 0; 212 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 213 RF_ACTIVE); 214 if (sc->irq_res == NULL) { 215 device_printf(dev, "could not allocate interrupt resources.\n"); 216 err = ENOMEM; 217 goto out; 218 } 219 220 err = ate_activate(dev); 221 if (err) 222 goto out; 223 224 sc->use_rmii = (RD4(sc, ETH_CFG) & ETH_CFG_RMII) == ETH_CFG_RMII; 225 226 /* Sysctls */ 227 sctx = device_get_sysctl_ctx(dev); 228 soid = device_get_sysctl_tree(dev); 229 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "rmii", 230 CTLFLAG_RD, &sc->use_rmii, 0, "rmii in use"); 231 232 /* Calling atestop before ifp is set is OK. */ 233 ATE_LOCK(sc); 234 atestop(sc); 235 ATE_UNLOCK(sc); 236 237 if ((err = ate_get_mac(sc, eaddr)) != 0) { 238 /* 239 * No MAC address configured. Generate the random one. 240 */ 241 if (bootverbose) 242 device_printf(dev, 243 "Generating random ethernet address.\n"); 244 rnd = arc4random(); 245 246 /* 247 * Set OUI to convenient locally assigned address. 'b' 248 * is 0x62, which has the locally assigned bit set, and 249 * the broadcast/multicast bit clear. 250 */ 251 eaddr[0] = 'b'; 252 eaddr[1] = 's'; 253 eaddr[2] = 'd'; 254 eaddr[3] = (rnd >> 16) & 0xff; 255 eaddr[4] = (rnd >> 8) & 0xff; 256 eaddr[5] = rnd & 0xff; 257 } 258 259 sc->ifp = ifp = if_alloc(IFT_ETHER); 260 if (mii_phy_probe(dev, &sc->miibus, ate_ifmedia_upd, ate_ifmedia_sts)) { 261 device_printf(dev, "Cannot find my PHY.\n"); 262 err = ENXIO; 263 goto out; 264 } 265 266 ifp->if_softc = sc; 267 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 268 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 269 ifp->if_capabilities |= IFCAP_VLAN_MTU; 270 ifp->if_capenable |= IFCAP_VLAN_MTU; /* The hw bits already set. */ 271 ifp->if_start = atestart; 272 ifp->if_ioctl = ateioctl; 273 ifp->if_init = ateinit; 274 ifp->if_baudrate = 10000000; 275 IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN); 276 ifp->if_snd.ifq_drv_maxlen = IFQ_MAXLEN; 277 IFQ_SET_READY(&ifp->if_snd); 278 ifp->if_linkmib = &sc->mibdata; 279 ifp->if_linkmiblen = sizeof(sc->mibdata); 280 sc->mibdata.dot3Compliance = DOT3COMPLIANCE_COLLS; 281 sc->if_flags = ifp->if_flags; 282 283 ether_ifattach(ifp, eaddr); 284 285 /* 286 * Activate the interrupt. 287 */ 288 err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_NET | INTR_MPSAFE, 289 NULL, ate_intr, sc, &sc->intrhand); 290 if (err) { 291 device_printf(dev, "could not establish interrupt handler.\n"); 292 ether_ifdetach(ifp); 293 goto out; 294 } 295 296out: 297 if (err) 298 ate_detach(dev); 299 return (err); 300} 301 302static int 303ate_detach(device_t dev) 304{ 305 struct ate_softc *sc; 306 struct ifnet *ifp; 307 308 sc = device_get_softc(dev); 309 KASSERT(sc != NULL, ("[ate: %d]: sc is NULL", __LINE__)); 310 ifp = sc->ifp; 311 if (device_is_attached(dev)) { 312 ether_ifdetach(ifp); 313 ATE_LOCK(sc); 314 atestop(sc); 315 ATE_UNLOCK(sc); 316 callout_drain(&sc->tick_ch); 317 } 318 if (sc->miibus != NULL) { 319 device_delete_child(dev, sc->miibus); 320 sc->miibus = NULL; 321 } 322 bus_generic_detach(sc->dev); 323 ate_deactivate(sc); 324 if (sc->intrhand != NULL) { 325 bus_teardown_intr(dev, sc->irq_res, sc->intrhand); 326 sc->intrhand = NULL; 327 } 328 if (ifp != NULL) { 329 if_free(ifp); 330 sc->ifp = NULL; 331 } 332 if (sc->mem_res != NULL) { 333 bus_release_resource(dev, SYS_RES_IOPORT, 334 rman_get_rid(sc->mem_res), sc->mem_res); 335 sc->mem_res = NULL; 336 } 337 if (sc->irq_res != NULL) { 338 bus_release_resource(dev, SYS_RES_IRQ, 339 rman_get_rid(sc->irq_res), sc->irq_res); 340 sc->irq_res = NULL; 341 } 342 ATE_LOCK_DESTROY(sc); 343 return (0); 344} 345 346static void 347ate_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 348{ 349 struct ate_softc *sc; 350 351 if (error != 0) 352 return; 353 sc = (struct ate_softc *)arg; 354 sc->rx_desc_phys = segs[0].ds_addr; 355} 356 357static void 358ate_load_rx_buf(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 359{ 360 struct ate_softc *sc; 361 int i; 362 363 if (error != 0) 364 return; 365 sc = (struct ate_softc *)arg; 366 i = sc->rx_buf_ptr; 367 368 /* 369 * For the last buffer, set the wrap bit so the controller 370 * restarts from the first descriptor. 371 */ 372 bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, BUS_DMASYNC_PREWRITE); 373 if (i == ATE_MAX_RX_BUFFERS - 1) 374 sc->rx_descs[i].addr = segs[0].ds_addr | ETH_WRAP_BIT; 375 else 376 sc->rx_descs[i].addr = segs[0].ds_addr; 377 bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, BUS_DMASYNC_POSTWRITE); 378 sc->rx_descs[i].status = 0; 379 /* Flush the memory in the mbuf */ 380 bus_dmamap_sync(sc->rxtag, sc->rx_map[i], BUS_DMASYNC_PREREAD); 381} 382 383static uint32_t 384ate_mac_hash(const uint8_t *buf) 385{ 386 uint32_t index = 0; 387 uint8_t bit; 388 uint8_t bitshift; 389 for (int i = 0; i < 48; i++) { 390 bit = i / 6; 391 bitshift = i - bit * 6; 392 index ^= ((buf[i >> 3] >> (i & 7)) & 1) << bitshift; 393 } 394 return (index); 395} 396 397/* 398 * Compute the multicast filter for this device using the standard 399 * algorithm. I wonder why this isn't in ether somewhere as a lot 400 * of different MAC chips use this method (or the reverse the bits) 401 * method. 402 */ 403static int 404ate_setmcast(struct ate_softc *sc) 405{ 406 uint32_t index; 407 uint32_t mcaf[2]; 408 u_char *af = (u_char *) mcaf; 409 struct ifmultiaddr *ifma; 410 struct ifnet *ifp; 411 412 ifp = sc->ifp; 413 414 if ((ifp->if_flags & IFF_PROMISC) != 0) 415 return (0); 416 if ((ifp->if_flags & IFF_ALLMULTI) != 0) { 417 WR4(sc, ETH_HSL, 0xffffffff); 418 WR4(sc, ETH_HSH, 0xffffffff); 419 return (1); 420 } 421 422 /* 423 * Compute the multicast hash. 424 */ 425 mcaf[0] = 0; 426 mcaf[1] = 0; 427 if_maddr_rlock(ifp); 428 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 429 if (ifma->ifma_addr->sa_family != AF_LINK) 430 continue; 431 index = 0; 432 index = ate_mac_hash(LLADDR((struct sockaddr_dl *) 433 ifma->ifma_addr)); 434 af[index >> 3] |= 1 << (index & 7); 435 } 436 if_maddr_runlock(ifp); 437 438 /* 439 * Write the hash to the hash register. This card can also 440 * accept unicast packets as well as multicast packets using this 441 * register for easier bridging operations, but we don't take 442 * advantage of that. Locks here are to avoid LOR with the 443 * if_maddr_rlock, but might not be strictly necessary. 444 */ 445 WR4(sc, ETH_HSL, mcaf[0]); 446 WR4(sc, ETH_HSH, mcaf[1]); 447 return (mcaf[0] || mcaf[1]); 448} 449 450static int 451ate_activate(device_t dev) 452{ 453 struct ate_softc *sc; 454 int err, i; 455 456 sc = device_get_softc(dev); 457 458 /* 459 * Allocate DMA tags and maps. 460 */ 461 err = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0, 462 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 463 1, MCLBYTES, 0, busdma_lock_mutex, &sc->sc_mtx, &sc->mtag); 464 if (err != 0) 465 goto errout; 466 for (i = 0; i < ATE_MAX_TX_BUFFERS; i++) { 467 err = bus_dmamap_create(sc->mtag, 0, &sc->tx_map[i]); 468 if (err != 0) 469 goto errout; 470 } 471 472 /* 473 * Allocate DMA tags and maps for RX. 474 */ 475 err = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0, 476 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 477 1, MCLBYTES, 0, busdma_lock_mutex, &sc->sc_mtx, &sc->rxtag); 478 if (err != 0) 479 goto errout; 480 481 /* 482 * DMA tag and map for the RX descriptors. 483 */ 484 err = bus_dma_tag_create(bus_get_dma_tag(dev), sizeof(eth_rx_desc_t), 485 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 486 ATE_MAX_RX_BUFFERS * sizeof(eth_rx_desc_t), 1, 487 ATE_MAX_RX_BUFFERS * sizeof(eth_rx_desc_t), 0, busdma_lock_mutex, 488 &sc->sc_mtx, &sc->rx_desc_tag); 489 if (err != 0) 490 goto errout; 491 if (bus_dmamem_alloc(sc->rx_desc_tag, (void **)&sc->rx_descs, 492 BUS_DMA_NOWAIT | BUS_DMA_COHERENT, &sc->rx_desc_map) != 0) 493 goto errout; 494 if (bus_dmamap_load(sc->rx_desc_tag, sc->rx_desc_map, 495 sc->rx_descs, ATE_MAX_RX_BUFFERS * sizeof(eth_rx_desc_t), 496 ate_getaddr, sc, 0) != 0) 497 goto errout; 498 499 /* 500 * Allocate our RX buffers. This chip has a RX structure that's filled 501 * in. 502 */ 503 for (i = 0; i < ATE_MAX_RX_BUFFERS; i++) { 504 sc->rx_buf_ptr = i; 505 if (bus_dmamem_alloc(sc->rxtag, (void **)&sc->rx_buf[i], 506 BUS_DMA_NOWAIT, &sc->rx_map[i]) != 0) 507 goto errout; 508 if (bus_dmamap_load(sc->rxtag, sc->rx_map[i], sc->rx_buf[i], 509 MCLBYTES, ate_load_rx_buf, sc, 0) != 0) 510 goto errout; 511 } 512 sc->rx_buf_ptr = 0; 513 /* Flush the memory for the EMAC rx descriptor. */ 514 bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, BUS_DMASYNC_PREWRITE); 515 /* Write the descriptor queue address. */ 516 WR4(sc, ETH_RBQP, sc->rx_desc_phys); 517 return (0); 518 519errout: 520 return (ENOMEM); 521} 522 523static void 524ate_deactivate(struct ate_softc *sc) 525{ 526 int i; 527 528 KASSERT(sc != NULL, ("[ate, %d]: sc is NULL!", __LINE__)); 529 if (sc->mtag != NULL) { 530 for (i = 0; i < ATE_MAX_TX_BUFFERS; i++) { 531 if (sc->sent_mbuf[i] != NULL) { 532 bus_dmamap_sync(sc->mtag, sc->tx_map[i], 533 BUS_DMASYNC_POSTWRITE); 534 bus_dmamap_unload(sc->mtag, sc->tx_map[i]); 535 m_freem(sc->sent_mbuf[i]); 536 } 537 bus_dmamap_destroy(sc->mtag, sc->tx_map[i]); 538 sc->sent_mbuf[i] = NULL; 539 sc->tx_map[i] = NULL; 540 } 541 bus_dma_tag_destroy(sc->mtag); 542 } 543 if (sc->rx_desc_tag != NULL) { 544 if (sc->rx_descs != NULL) { 545 if (sc->rx_desc_phys != 0) { 546 bus_dmamap_sync(sc->rx_desc_tag, 547 sc->rx_desc_map, BUS_DMASYNC_POSTREAD); 548 bus_dmamap_unload(sc->rx_desc_tag, 549 sc->rx_desc_map); 550 sc->rx_desc_phys = 0; 551 } 552 } 553 } 554 if (sc->rxtag != NULL) { 555 for (i = 0; i < ATE_MAX_RX_BUFFERS; i++) { 556 if (sc->rx_buf[i] != NULL) { 557 if (sc->rx_descs[i].addr != 0) { 558 bus_dmamap_sync(sc->rxtag, 559 sc->rx_map[i], 560 BUS_DMASYNC_POSTREAD); 561 bus_dmamap_unload(sc->rxtag, 562 sc->rx_map[i]); 563 sc->rx_descs[i].addr = 0; 564 } 565 bus_dmamem_free(sc->rxtag, sc->rx_buf[i], 566 sc->rx_map[i]); 567 sc->rx_buf[i] = NULL; 568 sc->rx_map[i] = NULL; 569 } 570 } 571 bus_dma_tag_destroy(sc->rxtag); 572 } 573 if (sc->rx_desc_tag != NULL) { 574 if (sc->rx_descs != NULL) 575 bus_dmamem_free(sc->rx_desc_tag, sc->rx_descs, 576 sc->rx_desc_map); 577 bus_dma_tag_destroy(sc->rx_desc_tag); 578 sc->rx_descs = NULL; 579 sc->rx_desc_tag = NULL; 580 } 581} 582 583/* 584 * Change media according to request. 585 */ 586static int 587ate_ifmedia_upd(struct ifnet *ifp) 588{ 589 struct ate_softc *sc = ifp->if_softc; 590 struct mii_data *mii; 591 592 mii = device_get_softc(sc->miibus); 593 ATE_LOCK(sc); 594 mii_mediachg(mii); 595 ATE_UNLOCK(sc); 596 return (0); 597} 598 599/* 600 * Notify the world which media we're using. 601 */ 602static void 603ate_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 604{ 605 struct ate_softc *sc = ifp->if_softc; 606 struct mii_data *mii; 607 608 mii = device_get_softc(sc->miibus); 609 ATE_LOCK(sc); 610 mii_pollstat(mii); 611 ifmr->ifm_active = mii->mii_media_active; 612 ifmr->ifm_status = mii->mii_media_status; 613 ATE_UNLOCK(sc); 614} 615 616static void 617ate_stat_update(struct ate_softc *sc, int active) 618{ 619 uint32_t reg; 620 621 /* 622 * The speed and full/half-duplex state needs to be reflected 623 * in the ETH_CFG register. 624 */ 625 reg = RD4(sc, ETH_CFG); 626 reg &= ~(ETH_CFG_SPD | ETH_CFG_FD); 627 if (IFM_SUBTYPE(active) != IFM_10_T) 628 reg |= ETH_CFG_SPD; 629 if (active & IFM_FDX) 630 reg |= ETH_CFG_FD; 631 WR4(sc, ETH_CFG, reg); 632} 633 634static void 635ate_tick(void *xsc) 636{ 637 struct ate_softc *sc = xsc; 638 struct ifnet *ifp = sc->ifp; 639 struct mii_data *mii; 640 int active; 641 uint32_t c; 642 643 /* 644 * The KB920x boot loader tests ETH_SR & ETH_SR_LINK and will ask 645 * the MII if there's a link if this bit is clear. Not sure if we 646 * should do the same thing here or not. 647 */ 648 ATE_ASSERT_LOCKED(sc); 649 if (sc->miibus != NULL) { 650 mii = device_get_softc(sc->miibus); 651 active = mii->mii_media_active; 652 mii_tick(mii); 653 if (mii->mii_media_status & IFM_ACTIVE && 654 active != mii->mii_media_active) 655 ate_stat_update(sc, mii->mii_media_active); 656 } 657 658 /* 659 * Update the stats as best we can. When we're done, clear 660 * the status counters and start over. We're supposed to read these 661 * registers often enough that they won't overflow. Hopefully 662 * once a second is often enough. Some don't map well to 663 * the dot3Stats mib, so for those we just count them as general 664 * errors. Stats for iframes, ibutes, oframes and obytes are 665 * collected elsewhere. These registers zero on a read to prevent 666 * races. For all the collision stats, also update the collision 667 * stats for the interface. 668 */ 669 sc->mibdata.dot3StatsAlignmentErrors += RD4(sc, ETH_ALE); 670 sc->mibdata.dot3StatsFCSErrors += RD4(sc, ETH_SEQE); 671 c = RD4(sc, ETH_SCOL); 672 ifp->if_collisions += c; 673 sc->mibdata.dot3StatsSingleCollisionFrames += c; 674 c = RD4(sc, ETH_MCOL); 675 sc->mibdata.dot3StatsMultipleCollisionFrames += c; 676 ifp->if_collisions += c; 677 sc->mibdata.dot3StatsSQETestErrors += RD4(sc, ETH_SQEE); 678 sc->mibdata.dot3StatsDeferredTransmissions += RD4(sc, ETH_DTE); 679 c = RD4(sc, ETH_LCOL); 680 sc->mibdata.dot3StatsLateCollisions += c; 681 ifp->if_collisions += c; 682 c = RD4(sc, ETH_ECOL); 683 sc->mibdata.dot3StatsExcessiveCollisions += c; 684 ifp->if_collisions += c; 685 sc->mibdata.dot3StatsCarrierSenseErrors += RD4(sc, ETH_CSE); 686 sc->mibdata.dot3StatsFrameTooLongs += RD4(sc, ETH_ELR); 687 sc->mibdata.dot3StatsInternalMacReceiveErrors += RD4(sc, ETH_DRFC); 688 689 /* 690 * Not sure where to lump these, so count them against the errors 691 * for the interface. 692 */ 693 sc->ifp->if_oerrors += RD4(sc, ETH_TUE); 694 sc->ifp->if_ierrors += RD4(sc, ETH_CDE) + RD4(sc, ETH_RJB) + 695 RD4(sc, ETH_USF); 696 697 /* 698 * Schedule another timeout one second from now. 699 */ 700 callout_reset(&sc->tick_ch, hz, ate_tick, sc); 701} 702 703static void 704ate_set_mac(struct ate_softc *sc, u_char *eaddr) 705{ 706 707 WR4(sc, ETH_SA1L, (eaddr[3] << 24) | (eaddr[2] << 16) | 708 (eaddr[1] << 8) | eaddr[0]); 709 WR4(sc, ETH_SA1H, (eaddr[5] << 8) | (eaddr[4])); 710} 711 712static int 713ate_get_mac(struct ate_softc *sc, u_char *eaddr) 714{ 715 bus_size_t sa_low_reg[] = { ETH_SA1L, ETH_SA2L, ETH_SA3L, ETH_SA4L }; 716 bus_size_t sa_high_reg[] = { ETH_SA1H, ETH_SA2H, ETH_SA3H, ETH_SA4H }; 717 uint32_t low, high; 718 int i; 719 720 /* 721 * The boot loader setup the MAC with an address, if one is set in 722 * the loader. Grab one MAC address from the SA[1-4][HL] registers. 723 */ 724 for (i = 0; i < 4; i++) { 725 low = RD4(sc, sa_low_reg[i]); 726 high = RD4(sc, sa_high_reg[i]); 727 if ((low | (high & 0xffff)) != 0) { 728 eaddr[0] = low & 0xff; 729 eaddr[1] = (low >> 8) & 0xff; 730 eaddr[2] = (low >> 16) & 0xff; 731 eaddr[3] = (low >> 24) & 0xff; 732 eaddr[4] = high & 0xff; 733 eaddr[5] = (high >> 8) & 0xff; 734 return (0); 735 } 736 } 737 return (ENXIO); 738} 739 740static void 741ate_intr(void *xsc) 742{ 743 struct ate_softc *sc = xsc; 744 struct ifnet *ifp = sc->ifp; 745 struct mbuf *mb; 746 void *bp; 747 uint32_t status, reg, rx_stat; 748 int i; 749 750 status = RD4(sc, ETH_ISR); 751 if (status == 0) 752 return; 753 if (status & ETH_ISR_RCOM) { 754 bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, 755 BUS_DMASYNC_POSTREAD); 756 while (sc->rx_descs[sc->rx_buf_ptr].addr & ETH_CPU_OWNER) { 757 i = sc->rx_buf_ptr; 758 sc->rx_buf_ptr = (i + 1) % ATE_MAX_RX_BUFFERS; 759 bp = sc->rx_buf[i]; 760 rx_stat = sc->rx_descs[i].status; 761 if ((rx_stat & ETH_LEN_MASK) == 0) { 762 if (bootverbose) 763 device_printf(sc->dev, "ignoring bogus zero-length packet\n"); 764 bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, 765 BUS_DMASYNC_PREWRITE); 766 sc->rx_descs[i].addr &= ~ETH_CPU_OWNER; 767 bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, 768 BUS_DMASYNC_POSTWRITE); 769 continue; 770 } 771 /* Flush memory for mbuf so we don't get stale bytes */ 772 bus_dmamap_sync(sc->rxtag, sc->rx_map[i], 773 BUS_DMASYNC_POSTREAD); 774 WR4(sc, ETH_RSR, RD4(sc, ETH_RSR)); 775 776 /* 777 * The length returned by the device includes the 778 * ethernet CRC calculation for the packet, but 779 * ifnet drivers are supposed to discard it. 780 */ 781 mb = m_devget(sc->rx_buf[i], 782 (rx_stat & ETH_LEN_MASK) - ETHER_CRC_LEN, 783 ETHER_ALIGN, ifp, NULL); 784 bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, 785 BUS_DMASYNC_PREWRITE); 786 sc->rx_descs[i].addr &= ~ETH_CPU_OWNER; 787 bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, 788 BUS_DMASYNC_POSTWRITE); 789 bus_dmamap_sync(sc->rxtag, sc->rx_map[i], 790 BUS_DMASYNC_PREREAD); 791 if (mb != NULL) { 792 ifp->if_ipackets++; 793 (*ifp->if_input)(ifp, mb); 794 } 795 796 } 797 } 798 if (status & ETH_ISR_TCOM) { 799 ATE_LOCK(sc); 800 /* XXX TSR register should be cleared */ 801 if (sc->sent_mbuf[0]) { 802 bus_dmamap_sync(sc->mtag, sc->tx_map[0], 803 BUS_DMASYNC_POSTWRITE); 804 bus_dmamap_unload(sc->mtag, sc->tx_map[0]); 805 m_freem(sc->sent_mbuf[0]); 806 ifp->if_opackets++; 807 sc->sent_mbuf[0] = NULL; 808 } 809 if (sc->sent_mbuf[1]) { 810 if (RD4(sc, ETH_TSR) & ETH_TSR_IDLE) { 811 bus_dmamap_sync(sc->mtag, sc->tx_map[1], 812 BUS_DMASYNC_POSTWRITE); 813 bus_dmamap_unload(sc->mtag, sc->tx_map[1]); 814 m_freem(sc->sent_mbuf[1]); 815 ifp->if_opackets++; 816 sc->txcur = 0; 817 sc->sent_mbuf[0] = sc->sent_mbuf[1] = NULL; 818 } else { 819 sc->sent_mbuf[0] = sc->sent_mbuf[1]; 820 sc->sent_mbuf[1] = NULL; 821 sc->txcur = 1; 822 } 823 } else { 824 sc->sent_mbuf[0] = NULL; 825 sc->txcur = 0; 826 } 827 /* 828 * We're no longer busy, so clear the busy flag and call the 829 * start routine to xmit more packets. 830 */ 831 sc->ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 832 atestart_locked(sc->ifp); 833 ATE_UNLOCK(sc); 834 } 835 if (status & ETH_ISR_RBNA) { 836 /* Workaround Errata #11 */ 837 if (bootverbose) 838 device_printf(sc->dev, "RBNA workaround\n"); 839 reg = RD4(sc, ETH_CTL); 840 WR4(sc, ETH_CTL, reg & ~ETH_CTL_RE); 841 BARRIER(sc, ETH_CTL, 4, BUS_SPACE_BARRIER_WRITE); 842 WR4(sc, ETH_CTL, reg | ETH_CTL_RE); 843 } 844} 845 846/* 847 * Reset and initialize the chip. 848 */ 849static void 850ateinit_locked(void *xsc) 851{ 852 struct ate_softc *sc = xsc; 853 struct ifnet *ifp = sc->ifp; 854 struct mii_data *mii; 855 uint8_t eaddr[ETHER_ADDR_LEN]; 856 uint32_t reg; 857 858 ATE_ASSERT_LOCKED(sc); 859 860 /* 861 * XXX TODO(3) 862 * we need to turn on the EMAC clock in the pmc. With the 863 * default boot loader, this is already turned on. However, we 864 * need to think about how best to turn it on/off as the interface 865 * is brought up/down, as well as dealing with the mii bus... 866 * 867 * We also need to multiplex the pins correctly. 868 */ 869 870 /* 871 * There are two different ways that the mii bus is connected 872 * to this chip. Select the right one based on a compile-time 873 * option. 874 */ 875 reg = RD4(sc, ETH_CFG); 876 if (sc->use_rmii) 877 reg |= ETH_CFG_RMII; 878 else 879 reg &= ~ETH_CFG_RMII; 880 WR4(sc, ETH_CFG, reg); 881 882 ate_rxfilter(sc); 883 884 /* 885 * Set the chip MAC address. 886 */ 887 bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN); 888 ate_set_mac(sc, eaddr); 889 890 /* 891 * Turn on MACs and interrupt processing. 892 */ 893 WR4(sc, ETH_CTL, RD4(sc, ETH_CTL) | ETH_CTL_TE | ETH_CTL_RE); 894 WR4(sc, ETH_IER, ETH_ISR_RCOM | ETH_ISR_TCOM | ETH_ISR_RBNA); 895 896 /* Enable big packets. */ 897 WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) | ETH_CFG_BIG); 898 899 /* 900 * Set 'running' flag, and clear output active flag 901 * and attempt to start the output. 902 */ 903 ifp->if_drv_flags |= IFF_DRV_RUNNING; 904 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 905 906 mii = device_get_softc(sc->miibus); 907 mii_pollstat(mii); 908 ate_stat_update(sc, mii->mii_media_active); 909 atestart_locked(ifp); 910 911 callout_reset(&sc->tick_ch, hz, ate_tick, sc); 912} 913 914/* 915 * Dequeue packets and transmit. 916 */ 917static void 918atestart_locked(struct ifnet *ifp) 919{ 920 struct ate_softc *sc = ifp->if_softc; 921 struct mbuf *m, *mdefrag; 922 bus_dma_segment_t segs[1]; 923 int nseg, e; 924 925 ATE_ASSERT_LOCKED(sc); 926 if (ifp->if_drv_flags & IFF_DRV_OACTIVE) 927 return; 928 929 while (sc->txcur < ATE_MAX_TX_BUFFERS) { 930 /* 931 * Check to see if there's room to put another packet into the 932 * xmit queue. The EMAC chip has a ping-pong buffer for xmit 933 * packets. We use OACTIVE to indicate "we can stuff more into 934 * our buffers (clear) or not (set)." 935 */ 936 if (!(RD4(sc, ETH_TSR) & ETH_TSR_BNQ)) { 937 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 938 return; 939 } 940 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 941 if (m == 0) { 942 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 943 return; 944 } 945 e = bus_dmamap_load_mbuf_sg(sc->mtag, sc->tx_map[sc->txcur], m, 946 segs, &nseg, 0); 947 if (e == EFBIG) { 948 mdefrag = m_defrag(m, M_DONTWAIT); 949 if (mdefrag == NULL) { 950 IFQ_DRV_PREPEND(&ifp->if_snd, m); 951 return; 952 } 953 m = mdefrag; 954 e = bus_dmamap_load_mbuf_sg(sc->mtag, 955 sc->tx_map[sc->txcur], m, segs, &nseg, 0); 956 } 957 if (e != 0) { 958 m_freem(m); 959 continue; 960 } 961 bus_dmamap_sync(sc->mtag, sc->tx_map[sc->txcur], 962 BUS_DMASYNC_PREWRITE); 963 964 /* 965 * Tell the hardware to xmit the packet. 966 */ 967 WR4(sc, ETH_TAR, segs[0].ds_addr); 968 BARRIER(sc, ETH_TAR, 8, BUS_SPACE_BARRIER_WRITE); 969 WR4(sc, ETH_TCR, segs[0].ds_len); 970 971 /* 972 * Tap off here if there is a bpf listener. 973 */ 974 BPF_MTAP(ifp, m); 975 976 sc->sent_mbuf[sc->txcur] = m; 977 sc->txcur++; 978 } 979} 980 981static void 982ateinit(void *xsc) 983{ 984 struct ate_softc *sc = xsc; 985 986 ATE_LOCK(sc); 987 ateinit_locked(sc); 988 ATE_UNLOCK(sc); 989} 990 991static void 992atestart(struct ifnet *ifp) 993{ 994 struct ate_softc *sc = ifp->if_softc; 995 996 ATE_LOCK(sc); 997 atestart_locked(ifp); 998 ATE_UNLOCK(sc); 999} 1000 1001/* 1002 * Turn off interrupts, and stop the NIC. Can be called with sc->ifp NULL, 1003 * so be careful. 1004 */ 1005static void 1006atestop(struct ate_softc *sc) 1007{ 1008 struct ifnet *ifp; 1009 int i; 1010 1011 ATE_ASSERT_LOCKED(sc); 1012 ifp = sc->ifp; 1013 if (ifp) { 1014 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1015 } 1016 1017 callout_stop(&sc->tick_ch); 1018 1019 /* 1020 * Enable some parts of the MAC that are needed always (like the 1021 * MII bus. This turns off the RE and TE bits, which will remain 1022 * off until ateinit() is called to turn them on. With RE and TE 1023 * turned off, there's no DMA to worry about after this write. 1024 */ 1025 WR4(sc, ETH_CTL, ETH_CTL_MPE); 1026 1027 /* 1028 * Turn off all the configured options and revert to defaults. 1029 */ 1030 WR4(sc, ETH_CFG, ETH_CFG_CLK_32); 1031 1032 /* 1033 * Turn off all the interrupts, and ack any pending ones by reading 1034 * the ISR. 1035 */ 1036 WR4(sc, ETH_IDR, 0xffffffff); 1037 RD4(sc, ETH_ISR); 1038 1039 /* 1040 * Clear out the Transmit and Receiver Status registers of any 1041 * errors they may be reporting 1042 */ 1043 WR4(sc, ETH_TSR, 0xffffffff); 1044 WR4(sc, ETH_RSR, 0xffffffff); 1045 1046 /* 1047 * Release TX resources. 1048 */ 1049 for (i = 0; i < ATE_MAX_TX_BUFFERS; i++) { 1050 if (sc->sent_mbuf[i] != NULL) { 1051 bus_dmamap_sync(sc->mtag, sc->tx_map[i], 1052 BUS_DMASYNC_POSTWRITE); 1053 bus_dmamap_unload(sc->mtag, sc->tx_map[i]); 1054 m_freem(sc->sent_mbuf[i]); 1055 sc->sent_mbuf[i] = NULL; 1056 } 1057 } 1058 1059 /* 1060 * XXX we should power down the EMAC if it isn't in use, after 1061 * putting it into loopback mode. This saves about 400uA according 1062 * to the datasheet. 1063 */ 1064} 1065 1066static void 1067ate_rxfilter(struct ate_softc *sc) 1068{ 1069 struct ifnet *ifp; 1070 uint32_t reg; 1071 int enabled; 1072 1073 KASSERT(sc != NULL, ("[ate, %d]: sc is NULL!", __LINE__)); 1074 ATE_ASSERT_LOCKED(sc); 1075 ifp = sc->ifp; 1076 1077 /* 1078 * Wipe out old filter settings. 1079 */ 1080 reg = RD4(sc, ETH_CFG); 1081 reg &= ~(ETH_CFG_CAF | ETH_CFG_MTI | ETH_CFG_UNI); 1082 reg |= ETH_CFG_NBC; 1083 sc->flags &= ~ATE_FLAG_MULTICAST; 1084 1085 /* 1086 * Set new parameters. 1087 */ 1088 if ((ifp->if_flags & IFF_BROADCAST) != 0) 1089 reg &= ~ETH_CFG_NBC; 1090 if ((ifp->if_flags & IFF_PROMISC) != 0) { 1091 reg |= ETH_CFG_CAF; 1092 } else { 1093 enabled = ate_setmcast(sc); 1094 if (enabled != 0) { 1095 reg |= ETH_CFG_MTI; 1096 sc->flags |= ATE_FLAG_MULTICAST; 1097 } 1098 } 1099 WR4(sc, ETH_CFG, reg); 1100} 1101 1102static int 1103ateioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1104{ 1105 struct ate_softc *sc = ifp->if_softc; 1106 struct mii_data *mii; 1107 struct ifreq *ifr = (struct ifreq *)data; 1108 int drv_flags, flags; 1109 int mask, error, enabled; 1110 1111 error = 0; 1112 flags = ifp->if_flags; 1113 drv_flags = ifp->if_drv_flags; 1114 switch (cmd) { 1115 case SIOCSIFFLAGS: 1116 ATE_LOCK(sc); 1117 if ((flags & IFF_UP) != 0) { 1118 if ((drv_flags & IFF_DRV_RUNNING) != 0) { 1119 if (((flags ^ sc->if_flags) 1120 & (IFF_PROMISC | IFF_ALLMULTI)) != 0) 1121 ate_rxfilter(sc); 1122 } else { 1123 ateinit_locked(sc); 1124 } 1125 } else if ((drv_flags & IFF_DRV_RUNNING) != 0) { 1126 atestop(sc); 1127 } 1128 sc->if_flags = flags; 1129 ATE_UNLOCK(sc); 1130 break; 1131 1132 case SIOCADDMULTI: 1133 case SIOCDELMULTI: 1134 if ((drv_flags & IFF_DRV_RUNNING) != 0) { 1135 ATE_LOCK(sc); 1136 enabled = ate_setmcast(sc); 1137 if (enabled != (sc->flags & ATE_FLAG_MULTICAST)) 1138 ate_rxfilter(sc); 1139 ATE_UNLOCK(sc); 1140 } 1141 break; 1142 1143 case SIOCSIFMEDIA: 1144 case SIOCGIFMEDIA: 1145 mii = device_get_softc(sc->miibus); 1146 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 1147 break; 1148 case SIOCSIFCAP: 1149 mask = ifp->if_capenable ^ ifr->ifr_reqcap; 1150 if (mask & IFCAP_VLAN_MTU) { 1151 ATE_LOCK(sc); 1152 if (ifr->ifr_reqcap & IFCAP_VLAN_MTU) { 1153 WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) | ETH_CFG_BIG); 1154 ifp->if_capenable |= IFCAP_VLAN_MTU; 1155 } else { 1156 WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) & ~ETH_CFG_BIG); 1157 ifp->if_capenable &= ~IFCAP_VLAN_MTU; 1158 } 1159 ATE_UNLOCK(sc); 1160 } 1161 default: 1162 error = ether_ioctl(ifp, cmd, data); 1163 break; 1164 } 1165 return (error); 1166} 1167 1168static void 1169ate_child_detached(device_t dev, device_t child) 1170{ 1171 struct ate_softc *sc; 1172 1173 sc = device_get_softc(dev); 1174 if (child == sc->miibus) 1175 sc->miibus = NULL; 1176} 1177 1178/* 1179 * MII bus support routines. 1180 */ 1181static int 1182ate_miibus_readreg(device_t dev, int phy, int reg) 1183{ 1184 struct ate_softc *sc; 1185 int val; 1186 1187 /* 1188 * XXX if we implement agressive power savings, then we need 1189 * XXX to make sure that the clock to the emac is on here 1190 */ 1191 1192 sc = device_get_softc(dev); 1193 DELAY(1); /* Hangs w/o this delay really 30.5us atm */ 1194 WR4(sc, ETH_MAN, ETH_MAN_REG_RD(phy, reg)); 1195 while ((RD4(sc, ETH_SR) & ETH_SR_IDLE) == 0) 1196 continue; 1197 val = RD4(sc, ETH_MAN) & ETH_MAN_VALUE_MASK; 1198 1199 return (val); 1200} 1201 1202static int 1203ate_miibus_writereg(device_t dev, int phy, int reg, int data) 1204{ 1205 struct ate_softc *sc; 1206 1207 /* 1208 * XXX if we implement agressive power savings, then we need 1209 * XXX to make sure that the clock to the emac is on here 1210 */ 1211 1212 sc = device_get_softc(dev); 1213 WR4(sc, ETH_MAN, ETH_MAN_REG_WR(phy, reg, data)); 1214 while ((RD4(sc, ETH_SR) & ETH_SR_IDLE) == 0) 1215 continue; 1216 return (0); 1217} 1218 1219static device_method_t ate_methods[] = { 1220 /* Device interface */ 1221 DEVMETHOD(device_probe, ate_probe), 1222 DEVMETHOD(device_attach, ate_attach), 1223 DEVMETHOD(device_detach, ate_detach), 1224 1225 /* Bus interface */ 1226 DEVMETHOD(bus_child_detached, ate_child_detached), 1227 1228 /* MII interface */ 1229 DEVMETHOD(miibus_readreg, ate_miibus_readreg), 1230 DEVMETHOD(miibus_writereg, ate_miibus_writereg), 1231 1232 { 0, 0 } 1233}; 1234 1235static driver_t ate_driver = { 1236 "ate", 1237 ate_methods, 1238 sizeof(struct ate_softc), 1239}; 1240 1241DRIVER_MODULE(ate, atmelarm, ate_driver, ate_devclass, 0, 0); 1242DRIVER_MODULE(miibus, ate, miibus_driver, miibus_devclass, 0, 0); 1243MODULE_DEPEND(ate, miibus, 1, 1, 1); 1244MODULE_DEPEND(ate, ether, 1, 1, 1); 1245