if_ate.c revision 199537
1/*- 2 * Copyright (c) 2006 M. Warner Losh. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 */ 25 26/* TODO 27 * 28 * 1) Turn on the clock in pmc? Turn off? 29 * 2) GPIO initializtion in board setup code. 30 */ 31 32#include <sys/cdefs.h> 33__FBSDID("$FreeBSD: head/sys/arm/at91/if_ate.c 199537 2009-11-19 18:11:23Z jhb $"); 34 35#include <sys/param.h> 36#include <sys/systm.h> 37#include <sys/bus.h> 38#include <sys/kernel.h> 39#include <sys/mbuf.h> 40#include <sys/malloc.h> 41#include <sys/module.h> 42#include <sys/rman.h> 43#include <sys/socket.h> 44#include <sys/sockio.h> 45#include <sys/sysctl.h> 46#include <machine/bus.h> 47 48#include <net/ethernet.h> 49#include <net/if.h> 50#include <net/if_arp.h> 51#include <net/if_dl.h> 52#include <net/if_media.h> 53#include <net/if_mib.h> 54#include <net/if_types.h> 55 56#ifdef INET 57#include <netinet/in.h> 58#include <netinet/in_systm.h> 59#include <netinet/in_var.h> 60#include <netinet/ip.h> 61#endif 62 63#include <net/bpf.h> 64#include <net/bpfdesc.h> 65 66#include <dev/mii/mii.h> 67#include <dev/mii/miivar.h> 68#include <arm/at91/if_atereg.h> 69 70#include "miibus_if.h" 71 72#define ATE_MAX_TX_BUFFERS 2 /* We have ping-pong tx buffers */ 73#define ATE_MAX_RX_BUFFERS 64 74 75/* 76 * Driver-specific flags. 77 */ 78#define ATE_FLAG_DETACHING 0x01 79#define ATE_FLAG_MULTICAST 0x02 80 81struct ate_softc 82{ 83 struct ifnet *ifp; /* ifnet pointer */ 84 struct mtx sc_mtx; /* Basically a perimeter lock */ 85 device_t dev; /* Myself */ 86 device_t miibus; /* My child miibus */ 87 struct resource *irq_res; /* IRQ resource */ 88 struct resource *mem_res; /* Memory resource */ 89 struct callout tick_ch; /* Tick callout */ 90 struct ifmib_iso_8802_3 mibdata; /* Stuff for network mgmt */ 91 struct mbuf *sent_mbuf[ATE_MAX_TX_BUFFERS]; /* Sent mbufs */ 92 bus_dma_tag_t mtag; /* bus dma tag for mbufs */ 93 bus_dma_tag_t rxtag; 94 bus_dma_tag_t rx_desc_tag; 95 bus_dmamap_t rx_desc_map; 96 bus_dmamap_t rx_map[ATE_MAX_RX_BUFFERS]; 97 bus_dmamap_t tx_map[ATE_MAX_TX_BUFFERS]; 98 bus_addr_t rx_desc_phys; 99 eth_rx_desc_t *rx_descs; 100 void *rx_buf[ATE_MAX_RX_BUFFERS]; /* RX buffer space */ 101 void *intrhand; /* Interrupt handle */ 102 int flags; 103 int if_flags; 104 int rx_buf_ptr; 105 int txcur; /* Current TX map pointer */ 106 int use_rmii; 107}; 108 109static inline uint32_t 110RD4(struct ate_softc *sc, bus_size_t off) 111{ 112 113 return (bus_read_4(sc->mem_res, off)); 114} 115 116static inline void 117WR4(struct ate_softc *sc, bus_size_t off, uint32_t val) 118{ 119 120 bus_write_4(sc->mem_res, off, val); 121} 122 123static inline void 124BARRIER(struct ate_softc *sc, bus_size_t off, bus_size_t len, int flags) 125{ 126 127 bus_barrier(sc->mem_res, off, len, flags); 128} 129 130#define ATE_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 131#define ATE_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 132#define ATE_LOCK_INIT(_sc) \ 133 mtx_init(&_sc->sc_mtx, device_get_nameunit(_sc->dev), \ 134 MTX_NETWORK_LOCK, MTX_DEF) 135#define ATE_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx); 136#define ATE_ASSERT_LOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_OWNED); 137#define ATE_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_NOTOWNED); 138 139static devclass_t ate_devclass; 140 141/* 142 * ifnet entry points. 143 */ 144static void ateinit_locked(void *); 145static void atestart_locked(struct ifnet *); 146 147static void ateinit(void *); 148static void atestart(struct ifnet *); 149static void atestop(struct ate_softc *); 150static int ateioctl(struct ifnet * ifp, u_long, caddr_t); 151 152/* 153 * Bus entry points. 154 */ 155static int ate_probe(device_t dev); 156static int ate_attach(device_t dev); 157static int ate_detach(device_t dev); 158static void ate_intr(void *); 159 160/* 161 * Helper routines. 162 */ 163static int ate_activate(device_t dev); 164static void ate_deactivate(struct ate_softc *sc); 165static int ate_ifmedia_upd(struct ifnet *ifp); 166static void ate_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr); 167static int ate_get_mac(struct ate_softc *sc, u_char *eaddr); 168static void ate_set_mac(struct ate_softc *sc, u_char *eaddr); 169static void ate_rxfilter(struct ate_softc *sc); 170 171/* 172 * The AT91 family of products has the ethernet called EMAC. However, 173 * it isn't self identifying. It is anticipated that the parent bus 174 * code will take care to only add ate devices where they really are. As 175 * such, we do nothing here to identify the device and just set its name. 176 */ 177static int 178ate_probe(device_t dev) 179{ 180 181 device_set_desc(dev, "EMAC"); 182 return (0); 183} 184 185static int 186ate_attach(device_t dev) 187{ 188 struct ate_softc *sc; 189 struct ifnet *ifp = NULL; 190 struct sysctl_ctx_list *sctx; 191 struct sysctl_oid *soid; 192 u_char eaddr[ETHER_ADDR_LEN]; 193 uint32_t rnd; 194 int rid, err; 195 196 sc = device_get_softc(dev); 197 sc->dev = dev; 198 ATE_LOCK_INIT(sc); 199 200 /* 201 * Allocate resources. 202 */ 203 rid = 0; 204 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 205 RF_ACTIVE); 206 if (sc->mem_res == NULL) { 207 device_printf(dev, "could not allocate memory resources.\n"); 208 err = ENOMEM; 209 goto out; 210 } 211 rid = 0; 212 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 213 RF_ACTIVE); 214 if (sc->irq_res == NULL) { 215 device_printf(dev, "could not allocate interrupt resources.\n"); 216 err = ENOMEM; 217 goto out; 218 } 219 220 err = ate_activate(dev); 221 if (err) 222 goto out; 223 224 sc->use_rmii = (RD4(sc, ETH_CFG) & ETH_CFG_RMII) == ETH_CFG_RMII; 225 226 /* Sysctls */ 227 sctx = device_get_sysctl_ctx(dev); 228 soid = device_get_sysctl_tree(dev); 229 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "rmii", 230 CTLFLAG_RD, &sc->use_rmii, 0, "rmii in use"); 231 232 /* Calling atestop before ifp is set is OK. */ 233 ATE_LOCK(sc); 234 atestop(sc); 235 ATE_UNLOCK(sc); 236 callout_init_mtx(&sc->tick_ch, &sc->sc_mtx, 0); 237 238 if ((err = ate_get_mac(sc, eaddr)) != 0) { 239 /* 240 * No MAC address configured. Generate the random one. 241 */ 242 if (bootverbose) 243 device_printf(dev, 244 "Generating random ethernet address.\n"); 245 rnd = arc4random(); 246 247 /* 248 * Set OUI to convenient locally assigned address. 'b' 249 * is 0x62, which has the locally assigned bit set, and 250 * the broadcast/multicast bit clear. 251 */ 252 eaddr[0] = 'b'; 253 eaddr[1] = 's'; 254 eaddr[2] = 'd'; 255 eaddr[3] = (rnd >> 16) & 0xff; 256 eaddr[4] = (rnd >> 8) & 0xff; 257 eaddr[5] = rnd & 0xff; 258 } 259 260 sc->ifp = ifp = if_alloc(IFT_ETHER); 261 if (mii_phy_probe(dev, &sc->miibus, ate_ifmedia_upd, ate_ifmedia_sts)) { 262 device_printf(dev, "Cannot find my PHY.\n"); 263 err = ENXIO; 264 goto out; 265 } 266 267 ifp->if_softc = sc; 268 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 269 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 270 ifp->if_capabilities |= IFCAP_VLAN_MTU; 271 ifp->if_capenable |= IFCAP_VLAN_MTU; /* The hw bits already set. */ 272 ifp->if_start = atestart; 273 ifp->if_ioctl = ateioctl; 274 ifp->if_init = ateinit; 275 ifp->if_baudrate = 10000000; 276 IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN); 277 ifp->if_snd.ifq_drv_maxlen = IFQ_MAXLEN; 278 IFQ_SET_READY(&ifp->if_snd); 279 ifp->if_linkmib = &sc->mibdata; 280 ifp->if_linkmiblen = sizeof(sc->mibdata); 281 sc->mibdata.dot3Compliance = DOT3COMPLIANCE_COLLS; 282 sc->if_flags = ifp->if_flags; 283 284 ether_ifattach(ifp, eaddr); 285 286 /* 287 * Activate the interrupt. 288 */ 289 err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_NET | INTR_MPSAFE, 290 NULL, ate_intr, sc, &sc->intrhand); 291 if (err) { 292 device_printf(dev, "could not establish interrupt handler.\n"); 293 ether_ifdetach(ifp); 294 goto out; 295 } 296 297out: 298 if (err) 299 ate_detach(dev); 300 return (err); 301} 302 303static int 304ate_detach(device_t dev) 305{ 306 struct ate_softc *sc; 307 struct ifnet *ifp; 308 309 sc = device_get_softc(dev); 310 KASSERT(sc != NULL, ("[ate: %d]: sc is NULL", __LINE__)); 311 ifp = sc->ifp; 312 if (device_is_attached(dev)) { 313 ATE_LOCK(sc); 314 sc->flags |= ATE_FLAG_DETACHING; 315 atestop(sc); 316 ATE_UNLOCK(sc); 317 callout_drain(&sc->tick_ch); 318 ether_ifdetach(ifp); 319 } 320 if (sc->miibus != NULL) { 321 device_delete_child(dev, sc->miibus); 322 sc->miibus = NULL; 323 } 324 bus_generic_detach(sc->dev); 325 ate_deactivate(sc); 326 if (sc->intrhand != NULL) { 327 bus_teardown_intr(dev, sc->irq_res, sc->intrhand); 328 sc->intrhand = NULL; 329 } 330 if (ifp != NULL) { 331 if_free(ifp); 332 sc->ifp = NULL; 333 } 334 if (sc->mem_res != NULL) { 335 bus_release_resource(dev, SYS_RES_IOPORT, 336 rman_get_rid(sc->mem_res), sc->mem_res); 337 sc->mem_res = NULL; 338 } 339 if (sc->irq_res != NULL) { 340 bus_release_resource(dev, SYS_RES_IRQ, 341 rman_get_rid(sc->irq_res), sc->irq_res); 342 sc->irq_res = NULL; 343 } 344 ATE_LOCK_DESTROY(sc); 345 return (0); 346} 347 348static void 349ate_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 350{ 351 struct ate_softc *sc; 352 353 if (error != 0) 354 return; 355 sc = (struct ate_softc *)arg; 356 sc->rx_desc_phys = segs[0].ds_addr; 357} 358 359static void 360ate_load_rx_buf(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 361{ 362 struct ate_softc *sc; 363 int i; 364 365 if (error != 0) 366 return; 367 sc = (struct ate_softc *)arg; 368 i = sc->rx_buf_ptr; 369 370 /* 371 * For the last buffer, set the wrap bit so the controller 372 * restarts from the first descriptor. 373 */ 374 bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, BUS_DMASYNC_PREWRITE); 375 if (i == ATE_MAX_RX_BUFFERS - 1) 376 sc->rx_descs[i].addr = segs[0].ds_addr | ETH_WRAP_BIT; 377 else 378 sc->rx_descs[i].addr = segs[0].ds_addr; 379 bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, BUS_DMASYNC_POSTWRITE); 380 sc->rx_descs[i].status = 0; 381 /* Flush the memory in the mbuf */ 382 bus_dmamap_sync(sc->rxtag, sc->rx_map[i], BUS_DMASYNC_PREREAD); 383} 384 385/* 386 * Compute the multicast filter for this device using the standard 387 * algorithm. I wonder why this isn't in ether somewhere as a lot 388 * of different MAC chips use this method (or the reverse the bits) 389 * method. 390 */ 391static int 392ate_setmcast(struct ate_softc *sc) 393{ 394 uint32_t index; 395 uint32_t mcaf[2]; 396 u_char *af = (u_char *) mcaf; 397 struct ifmultiaddr *ifma; 398 struct ifnet *ifp; 399 400 ifp = sc->ifp; 401 402 if ((ifp->if_flags & IFF_PROMISC) != 0) 403 return (0); 404 if ((ifp->if_flags & IFF_ALLMULTI) != 0) { 405 WR4(sc, ETH_HSL, 0xffffffff); 406 WR4(sc, ETH_HSH, 0xffffffff); 407 return (1); 408 } 409 410 /* 411 * Compute the multicast hash. 412 */ 413 mcaf[0] = 0; 414 mcaf[1] = 0; 415 if_maddr_rlock(ifp); 416 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 417 if (ifma->ifma_addr->sa_family != AF_LINK) 418 continue; 419 index = ether_crc32_be(LLADDR((struct sockaddr_dl *) 420 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 421 af[index >> 3] |= 1 << (index & 7); 422 } 423 if_maddr_runlock(ifp); 424 425 /* 426 * Write the hash to the hash register. This card can also 427 * accept unicast packets as well as multicast packets using this 428 * register for easier bridging operations, but we don't take 429 * advantage of that. Locks here are to avoid LOR with the 430 * if_maddr_rlock, but might not be strictly necessary. 431 */ 432 WR4(sc, ETH_HSL, mcaf[0]); 433 WR4(sc, ETH_HSH, mcaf[1]); 434 return (mcaf[0] || mcaf[1]); 435} 436 437static int 438ate_activate(device_t dev) 439{ 440 struct ate_softc *sc; 441 int err, i; 442 443 sc = device_get_softc(dev); 444 445 /* 446 * Allocate DMA tags and maps. 447 */ 448 err = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0, 449 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 450 1, MCLBYTES, 0, busdma_lock_mutex, &sc->sc_mtx, &sc->mtag); 451 if (err != 0) 452 goto errout; 453 for (i = 0; i < ATE_MAX_TX_BUFFERS; i++) { 454 err = bus_dmamap_create(sc->mtag, 0, &sc->tx_map[i]); 455 if (err != 0) 456 goto errout; 457 } 458 459 /* 460 * Allocate DMA tags and maps for RX. 461 */ 462 err = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0, 463 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 464 1, MCLBYTES, 0, busdma_lock_mutex, &sc->sc_mtx, &sc->rxtag); 465 if (err != 0) 466 goto errout; 467 468 /* 469 * DMA tag and map for the RX descriptors. 470 */ 471 err = bus_dma_tag_create(bus_get_dma_tag(dev), sizeof(eth_rx_desc_t), 472 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 473 ATE_MAX_RX_BUFFERS * sizeof(eth_rx_desc_t), 1, 474 ATE_MAX_RX_BUFFERS * sizeof(eth_rx_desc_t), 0, busdma_lock_mutex, 475 &sc->sc_mtx, &sc->rx_desc_tag); 476 if (err != 0) 477 goto errout; 478 if (bus_dmamem_alloc(sc->rx_desc_tag, (void **)&sc->rx_descs, 479 BUS_DMA_NOWAIT | BUS_DMA_COHERENT, &sc->rx_desc_map) != 0) 480 goto errout; 481 if (bus_dmamap_load(sc->rx_desc_tag, sc->rx_desc_map, 482 sc->rx_descs, ATE_MAX_RX_BUFFERS * sizeof(eth_rx_desc_t), 483 ate_getaddr, sc, 0) != 0) 484 goto errout; 485 486 /* 487 * Allocate our RX buffers. This chip has a RX structure that's filled 488 * in. 489 */ 490 for (i = 0; i < ATE_MAX_RX_BUFFERS; i++) { 491 sc->rx_buf_ptr = i; 492 if (bus_dmamem_alloc(sc->rxtag, (void **)&sc->rx_buf[i], 493 BUS_DMA_NOWAIT, &sc->rx_map[i]) != 0) 494 goto errout; 495 if (bus_dmamap_load(sc->rxtag, sc->rx_map[i], sc->rx_buf[i], 496 MCLBYTES, ate_load_rx_buf, sc, 0) != 0) 497 goto errout; 498 } 499 sc->rx_buf_ptr = 0; 500 /* Flush the memory for the EMAC rx descriptor. */ 501 bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, BUS_DMASYNC_PREWRITE); 502 /* Write the descriptor queue address. */ 503 WR4(sc, ETH_RBQP, sc->rx_desc_phys); 504 return (0); 505 506errout: 507 return (ENOMEM); 508} 509 510static void 511ate_deactivate(struct ate_softc *sc) 512{ 513 int i; 514 515 KASSERT(sc != NULL, ("[ate, %d]: sc is NULL!", __LINE__)); 516 if (sc->mtag != NULL) { 517 for (i = 0; i < ATE_MAX_TX_BUFFERS; i++) { 518 if (sc->sent_mbuf[i] != NULL) { 519 bus_dmamap_sync(sc->mtag, sc->tx_map[i], 520 BUS_DMASYNC_POSTWRITE); 521 bus_dmamap_unload(sc->mtag, sc->tx_map[i]); 522 m_freem(sc->sent_mbuf[i]); 523 } 524 bus_dmamap_destroy(sc->mtag, sc->tx_map[i]); 525 sc->sent_mbuf[i] = NULL; 526 sc->tx_map[i] = NULL; 527 } 528 bus_dma_tag_destroy(sc->mtag); 529 } 530 if (sc->rx_desc_tag != NULL) { 531 if (sc->rx_descs != NULL) { 532 if (sc->rx_desc_phys != 0) { 533 bus_dmamap_sync(sc->rx_desc_tag, 534 sc->rx_desc_map, BUS_DMASYNC_POSTREAD); 535 bus_dmamap_unload(sc->rx_desc_tag, 536 sc->rx_desc_map); 537 sc->rx_desc_phys = 0; 538 } 539 } 540 } 541 if (sc->rxtag != NULL) { 542 for (i = 0; i < ATE_MAX_RX_BUFFERS; i++) { 543 if (sc->rx_buf[i] != NULL) { 544 if (sc->rx_descs[i].addr != 0) { 545 bus_dmamap_sync(sc->rxtag, 546 sc->rx_map[i], 547 BUS_DMASYNC_POSTREAD); 548 bus_dmamap_unload(sc->rxtag, 549 sc->rx_map[i]); 550 sc->rx_descs[i].addr = 0; 551 } 552 bus_dmamem_free(sc->rxtag, sc->rx_buf[i], 553 sc->rx_map[i]); 554 sc->rx_buf[i] = NULL; 555 sc->rx_map[i] = NULL; 556 } 557 } 558 bus_dma_tag_destroy(sc->rxtag); 559 } 560 if (sc->rx_desc_tag != NULL) { 561 if (sc->rx_descs != NULL) 562 bus_dmamem_free(sc->rx_desc_tag, sc->rx_descs, 563 sc->rx_desc_map); 564 bus_dma_tag_destroy(sc->rx_desc_tag); 565 sc->rx_descs = NULL; 566 sc->rx_desc_tag = NULL; 567 } 568} 569 570/* 571 * Change media according to request. 572 */ 573static int 574ate_ifmedia_upd(struct ifnet *ifp) 575{ 576 struct ate_softc *sc = ifp->if_softc; 577 struct mii_data *mii; 578 579 mii = device_get_softc(sc->miibus); 580 ATE_LOCK(sc); 581 mii_mediachg(mii); 582 ATE_UNLOCK(sc); 583 return (0); 584} 585 586/* 587 * Notify the world which media we're using. 588 */ 589static void 590ate_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 591{ 592 struct ate_softc *sc = ifp->if_softc; 593 struct mii_data *mii; 594 595 mii = device_get_softc(sc->miibus); 596 ATE_LOCK(sc); 597 mii_pollstat(mii); 598 ifmr->ifm_active = mii->mii_media_active; 599 ifmr->ifm_status = mii->mii_media_status; 600 ATE_UNLOCK(sc); 601} 602 603static void 604ate_stat_update(struct ate_softc *sc, int active) 605{ 606 uint32_t reg; 607 608 /* 609 * The speed and full/half-duplex state needs to be reflected 610 * in the ETH_CFG register. 611 */ 612 reg = RD4(sc, ETH_CFG); 613 reg &= ~(ETH_CFG_SPD | ETH_CFG_FD); 614 if (IFM_SUBTYPE(active) != IFM_10_T) 615 reg |= ETH_CFG_SPD; 616 if (active & IFM_FDX) 617 reg |= ETH_CFG_FD; 618 WR4(sc, ETH_CFG, reg); 619} 620 621static void 622ate_tick(void *xsc) 623{ 624 struct ate_softc *sc = xsc; 625 struct ifnet *ifp = sc->ifp; 626 struct mii_data *mii; 627 int active; 628 uint32_t c; 629 630 /* 631 * The KB920x boot loader tests ETH_SR & ETH_SR_LINK and will ask 632 * the MII if there's a link if this bit is clear. Not sure if we 633 * should do the same thing here or not. 634 */ 635 ATE_ASSERT_LOCKED(sc); 636 if (sc->miibus != NULL) { 637 mii = device_get_softc(sc->miibus); 638 active = mii->mii_media_active; 639 mii_tick(mii); 640 if (mii->mii_media_status & IFM_ACTIVE && 641 active != mii->mii_media_active) 642 ate_stat_update(sc, mii->mii_media_active); 643 } 644 645 /* 646 * Update the stats as best we can. When we're done, clear 647 * the status counters and start over. We're supposed to read these 648 * registers often enough that they won't overflow. Hopefully 649 * once a second is often enough. Some don't map well to 650 * the dot3Stats mib, so for those we just count them as general 651 * errors. Stats for iframes, ibutes, oframes and obytes are 652 * collected elsewhere. These registers zero on a read to prevent 653 * races. For all the collision stats, also update the collision 654 * stats for the interface. 655 */ 656 sc->mibdata.dot3StatsAlignmentErrors += RD4(sc, ETH_ALE); 657 sc->mibdata.dot3StatsFCSErrors += RD4(sc, ETH_SEQE); 658 c = RD4(sc, ETH_SCOL); 659 ifp->if_collisions += c; 660 sc->mibdata.dot3StatsSingleCollisionFrames += c; 661 c = RD4(sc, ETH_MCOL); 662 sc->mibdata.dot3StatsMultipleCollisionFrames += c; 663 ifp->if_collisions += c; 664 sc->mibdata.dot3StatsSQETestErrors += RD4(sc, ETH_SQEE); 665 sc->mibdata.dot3StatsDeferredTransmissions += RD4(sc, ETH_DTE); 666 c = RD4(sc, ETH_LCOL); 667 sc->mibdata.dot3StatsLateCollisions += c; 668 ifp->if_collisions += c; 669 c = RD4(sc, ETH_ECOL); 670 sc->mibdata.dot3StatsExcessiveCollisions += c; 671 ifp->if_collisions += c; 672 sc->mibdata.dot3StatsCarrierSenseErrors += RD4(sc, ETH_CSE); 673 sc->mibdata.dot3StatsFrameTooLongs += RD4(sc, ETH_ELR); 674 sc->mibdata.dot3StatsInternalMacReceiveErrors += RD4(sc, ETH_DRFC); 675 676 /* 677 * Not sure where to lump these, so count them against the errors 678 * for the interface. 679 */ 680 sc->ifp->if_oerrors += RD4(sc, ETH_TUE); 681 sc->ifp->if_ierrors += RD4(sc, ETH_CDE) + RD4(sc, ETH_RJB) + 682 RD4(sc, ETH_USF); 683 684 /* 685 * Schedule another timeout one second from now. 686 */ 687 callout_reset(&sc->tick_ch, hz, ate_tick, sc); 688} 689 690static void 691ate_set_mac(struct ate_softc *sc, u_char *eaddr) 692{ 693 694 WR4(sc, ETH_SA1L, (eaddr[3] << 24) | (eaddr[2] << 16) | 695 (eaddr[1] << 8) | eaddr[0]); 696 WR4(sc, ETH_SA1H, (eaddr[5] << 8) | (eaddr[4])); 697} 698 699static int 700ate_get_mac(struct ate_softc *sc, u_char *eaddr) 701{ 702 bus_size_t sa_low_reg[] = { ETH_SA1L, ETH_SA2L, ETH_SA3L, ETH_SA4L }; 703 bus_size_t sa_high_reg[] = { ETH_SA1H, ETH_SA2H, ETH_SA3H, ETH_SA4H }; 704 uint32_t low, high; 705 int i; 706 707 /* 708 * The boot loader setup the MAC with an address, if one is set in 709 * the loader. Grab one MAC address from the SA[1-4][HL] registers. 710 */ 711 for (i = 0; i < 4; i++) { 712 low = RD4(sc, sa_low_reg[i]); 713 high = RD4(sc, sa_high_reg[i]); 714 if ((low | (high & 0xffff)) != 0) { 715 eaddr[0] = low & 0xff; 716 eaddr[1] = (low >> 8) & 0xff; 717 eaddr[2] = (low >> 16) & 0xff; 718 eaddr[3] = (low >> 24) & 0xff; 719 eaddr[4] = high & 0xff; 720 eaddr[5] = (high >> 8) & 0xff; 721 return (0); 722 } 723 } 724 return (ENXIO); 725} 726 727static void 728ate_intr(void *xsc) 729{ 730 struct ate_softc *sc = xsc; 731 struct ifnet *ifp = sc->ifp; 732 struct mbuf *mb; 733 void *bp; 734 uint32_t status, reg, rx_stat; 735 int i; 736 737 status = RD4(sc, ETH_ISR); 738 if (status == 0) 739 return; 740 if (status & ETH_ISR_RCOM) { 741 bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, 742 BUS_DMASYNC_POSTREAD); 743 while (sc->rx_descs[sc->rx_buf_ptr].addr & ETH_CPU_OWNER) { 744 i = sc->rx_buf_ptr; 745 sc->rx_buf_ptr = (i + 1) % ATE_MAX_RX_BUFFERS; 746 bp = sc->rx_buf[i]; 747 rx_stat = sc->rx_descs[i].status; 748 if ((rx_stat & ETH_LEN_MASK) == 0) { 749 if (bootverbose) 750 device_printf(sc->dev, "ignoring bogus zero-length packet\n"); 751 bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, 752 BUS_DMASYNC_PREWRITE); 753 sc->rx_descs[i].addr &= ~ETH_CPU_OWNER; 754 bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, 755 BUS_DMASYNC_POSTWRITE); 756 continue; 757 } 758 /* Flush memory for mbuf so we don't get stale bytes */ 759 bus_dmamap_sync(sc->rxtag, sc->rx_map[i], 760 BUS_DMASYNC_POSTREAD); 761 WR4(sc, ETH_RSR, RD4(sc, ETH_RSR)); 762 763 /* 764 * The length returned by the device includes the 765 * ethernet CRC calculation for the packet, but 766 * ifnet drivers are supposed to discard it. 767 */ 768 mb = m_devget(sc->rx_buf[i], 769 (rx_stat & ETH_LEN_MASK) - ETHER_CRC_LEN, 770 ETHER_ALIGN, ifp, NULL); 771 bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, 772 BUS_DMASYNC_PREWRITE); 773 sc->rx_descs[i].addr &= ~ETH_CPU_OWNER; 774 bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, 775 BUS_DMASYNC_POSTWRITE); 776 bus_dmamap_sync(sc->rxtag, sc->rx_map[i], 777 BUS_DMASYNC_PREREAD); 778 if (mb != NULL) { 779 ifp->if_ipackets++; 780 (*ifp->if_input)(ifp, mb); 781 } 782 783 } 784 } 785 if (status & ETH_ISR_TCOM) { 786 ATE_LOCK(sc); 787 /* XXX TSR register should be cleared */ 788 if (sc->sent_mbuf[0]) { 789 bus_dmamap_sync(sc->mtag, sc->tx_map[0], 790 BUS_DMASYNC_POSTWRITE); 791 bus_dmamap_unload(sc->mtag, sc->tx_map[0]); 792 m_freem(sc->sent_mbuf[0]); 793 ifp->if_opackets++; 794 sc->sent_mbuf[0] = NULL; 795 } 796 if (sc->sent_mbuf[1]) { 797 if (RD4(sc, ETH_TSR) & ETH_TSR_IDLE) { 798 bus_dmamap_sync(sc->mtag, sc->tx_map[1], 799 BUS_DMASYNC_POSTWRITE); 800 bus_dmamap_unload(sc->mtag, sc->tx_map[1]); 801 m_freem(sc->sent_mbuf[1]); 802 ifp->if_opackets++; 803 sc->txcur = 0; 804 sc->sent_mbuf[0] = sc->sent_mbuf[1] = NULL; 805 } else { 806 sc->sent_mbuf[0] = sc->sent_mbuf[1]; 807 sc->sent_mbuf[1] = NULL; 808 sc->txcur = 1; 809 } 810 } else { 811 sc->sent_mbuf[0] = NULL; 812 sc->txcur = 0; 813 } 814 /* 815 * We're no longer busy, so clear the busy flag and call the 816 * start routine to xmit more packets. 817 */ 818 sc->ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 819 atestart_locked(sc->ifp); 820 ATE_UNLOCK(sc); 821 } 822 if (status & ETH_ISR_RBNA) { 823 /* Workaround Errata #11 */ 824 if (bootverbose) 825 device_printf(sc->dev, "RBNA workaround\n"); 826 reg = RD4(sc, ETH_CTL); 827 WR4(sc, ETH_CTL, reg & ~ETH_CTL_RE); 828 BARRIER(sc, ETH_CTL, 4, BUS_SPACE_BARRIER_WRITE); 829 WR4(sc, ETH_CTL, reg | ETH_CTL_RE); 830 } 831} 832 833/* 834 * Reset and initialize the chip. 835 */ 836static void 837ateinit_locked(void *xsc) 838{ 839 struct ate_softc *sc = xsc; 840 struct ifnet *ifp = sc->ifp; 841 struct mii_data *mii; 842 uint8_t eaddr[ETHER_ADDR_LEN]; 843 uint32_t reg; 844 845 ATE_ASSERT_LOCKED(sc); 846 847 /* 848 * XXX TODO(3) 849 * we need to turn on the EMAC clock in the pmc. With the 850 * default boot loader, this is already turned on. However, we 851 * need to think about how best to turn it on/off as the interface 852 * is brought up/down, as well as dealing with the mii bus... 853 * 854 * We also need to multiplex the pins correctly. 855 */ 856 857 /* 858 * There are two different ways that the mii bus is connected 859 * to this chip. Select the right one based on a compile-time 860 * option. 861 */ 862 reg = RD4(sc, ETH_CFG); 863 if (sc->use_rmii) 864 reg |= ETH_CFG_RMII; 865 else 866 reg &= ~ETH_CFG_RMII; 867 WR4(sc, ETH_CFG, reg); 868 869 ate_rxfilter(sc); 870 871 /* 872 * Set the chip MAC address. 873 */ 874 bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN); 875 ate_set_mac(sc, eaddr); 876 877 /* 878 * Turn on MACs and interrupt processing. 879 */ 880 WR4(sc, ETH_CTL, RD4(sc, ETH_CTL) | ETH_CTL_TE | ETH_CTL_RE); 881 WR4(sc, ETH_IER, ETH_ISR_RCOM | ETH_ISR_TCOM | ETH_ISR_RBNA); 882 883 /* Enable big packets. */ 884 WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) | ETH_CFG_BIG); 885 886 /* 887 * Set 'running' flag, and clear output active flag 888 * and attempt to start the output. 889 */ 890 ifp->if_drv_flags |= IFF_DRV_RUNNING; 891 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 892 893 mii = device_get_softc(sc->miibus); 894 mii_pollstat(mii); 895 ate_stat_update(sc, mii->mii_media_active); 896 atestart_locked(ifp); 897 898 callout_reset(&sc->tick_ch, hz, ate_tick, sc); 899} 900 901/* 902 * Dequeue packets and transmit. 903 */ 904static void 905atestart_locked(struct ifnet *ifp) 906{ 907 struct ate_softc *sc = ifp->if_softc; 908 struct mbuf *m, *mdefrag; 909 bus_dma_segment_t segs[1]; 910 int nseg, e; 911 912 ATE_ASSERT_LOCKED(sc); 913 if (ifp->if_drv_flags & IFF_DRV_OACTIVE) 914 return; 915 916 while (sc->txcur < ATE_MAX_TX_BUFFERS) { 917 /* 918 * Check to see if there's room to put another packet into the 919 * xmit queue. The EMAC chip has a ping-pong buffer for xmit 920 * packets. We use OACTIVE to indicate "we can stuff more into 921 * our buffers (clear) or not (set)." 922 */ 923 if (!(RD4(sc, ETH_TSR) & ETH_TSR_BNQ)) { 924 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 925 return; 926 } 927 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 928 if (m == 0) { 929 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 930 return; 931 } 932 e = bus_dmamap_load_mbuf_sg(sc->mtag, sc->tx_map[sc->txcur], m, 933 segs, &nseg, 0); 934 if (e == EFBIG) { 935 mdefrag = m_defrag(m, M_DONTWAIT); 936 if (mdefrag == NULL) { 937 IFQ_DRV_PREPEND(&ifp->if_snd, m); 938 return; 939 } 940 m = mdefrag; 941 e = bus_dmamap_load_mbuf_sg(sc->mtag, 942 sc->tx_map[sc->txcur], m, segs, &nseg, 0); 943 } 944 if (e != 0) { 945 m_freem(m); 946 continue; 947 } 948 bus_dmamap_sync(sc->mtag, sc->tx_map[sc->txcur], 949 BUS_DMASYNC_PREWRITE); 950 951 /* 952 * Tell the hardware to xmit the packet. 953 */ 954 WR4(sc, ETH_TAR, segs[0].ds_addr); 955 BARRIER(sc, ETH_TAR, 8, BUS_SPACE_BARRIER_WRITE); 956 WR4(sc, ETH_TCR, segs[0].ds_len); 957 958 /* 959 * Tap off here if there is a bpf listener. 960 */ 961 BPF_MTAP(ifp, m); 962 963 sc->sent_mbuf[sc->txcur] = m; 964 sc->txcur++; 965 } 966} 967 968static void 969ateinit(void *xsc) 970{ 971 struct ate_softc *sc = xsc; 972 973 ATE_LOCK(sc); 974 ateinit_locked(sc); 975 ATE_UNLOCK(sc); 976} 977 978static void 979atestart(struct ifnet *ifp) 980{ 981 struct ate_softc *sc = ifp->if_softc; 982 983 ATE_LOCK(sc); 984 atestart_locked(ifp); 985 ATE_UNLOCK(sc); 986} 987 988/* 989 * Turn off interrupts, and stop the NIC. Can be called with sc->ifp NULL, 990 * so be careful. 991 */ 992static void 993atestop(struct ate_softc *sc) 994{ 995 struct ifnet *ifp; 996 int i; 997 998 ATE_ASSERT_LOCKED(sc); 999 ifp = sc->ifp; 1000 if (ifp) { 1001 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1002 } 1003 1004 callout_stop(&sc->tick_ch); 1005 1006 /* 1007 * Enable some parts of the MAC that are needed always (like the 1008 * MII bus. This turns off the RE and TE bits, which will remain 1009 * off until ateinit() is called to turn them on. With RE and TE 1010 * turned off, there's no DMA to worry about after this write. 1011 */ 1012 WR4(sc, ETH_CTL, ETH_CTL_MPE); 1013 1014 /* 1015 * Turn off all the configured options and revert to defaults. 1016 */ 1017 WR4(sc, ETH_CFG, ETH_CFG_CLK_32); 1018 1019 /* 1020 * Turn off all the interrupts, and ack any pending ones by reading 1021 * the ISR. 1022 */ 1023 WR4(sc, ETH_IDR, 0xffffffff); 1024 RD4(sc, ETH_ISR); 1025 1026 /* 1027 * Clear out the Transmit and Receiver Status registers of any 1028 * errors they may be reporting 1029 */ 1030 WR4(sc, ETH_TSR, 0xffffffff); 1031 WR4(sc, ETH_RSR, 0xffffffff); 1032 1033 /* 1034 * Release TX resources. 1035 */ 1036 for (i = 0; i < ATE_MAX_TX_BUFFERS; i++) { 1037 if (sc->sent_mbuf[i] != NULL) { 1038 bus_dmamap_sync(sc->mtag, sc->tx_map[i], 1039 BUS_DMASYNC_POSTWRITE); 1040 bus_dmamap_unload(sc->mtag, sc->tx_map[i]); 1041 m_freem(sc->sent_mbuf[i]); 1042 sc->sent_mbuf[i] = NULL; 1043 } 1044 } 1045 1046 /* 1047 * XXX we should power down the EMAC if it isn't in use, after 1048 * putting it into loopback mode. This saves about 400uA according 1049 * to the datasheet. 1050 */ 1051} 1052 1053static void 1054ate_rxfilter(struct ate_softc *sc) 1055{ 1056 struct ifnet *ifp; 1057 uint32_t reg; 1058 int enabled; 1059 1060 KASSERT(sc != NULL, ("[ate, %d]: sc is NULL!", __LINE__)); 1061 ATE_ASSERT_LOCKED(sc); 1062 ifp = sc->ifp; 1063 1064 /* 1065 * Wipe out old filter settings. 1066 */ 1067 reg = RD4(sc, ETH_CFG); 1068 reg &= ~(ETH_CFG_CAF | ETH_CFG_MTI | ETH_CFG_UNI); 1069 reg |= ETH_CFG_NBC; 1070 sc->flags &= ~ATE_FLAG_MULTICAST; 1071 1072 /* 1073 * Set new parameters. 1074 */ 1075 if ((ifp->if_flags & IFF_BROADCAST) != 0) 1076 reg &= ~ETH_CFG_NBC; 1077 if ((ifp->if_flags & IFF_PROMISC) != 0) { 1078 reg |= ETH_CFG_CAF; 1079 } else { 1080 enabled = ate_setmcast(sc); 1081 if (enabled != 0) { 1082 reg |= ETH_CFG_MTI; 1083 sc->flags |= ATE_FLAG_MULTICAST; 1084 } 1085 } 1086 WR4(sc, ETH_CFG, reg); 1087} 1088 1089static int 1090ateioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1091{ 1092 struct ate_softc *sc = ifp->if_softc; 1093 struct mii_data *mii; 1094 struct ifreq *ifr = (struct ifreq *)data; 1095 int drv_flags, flags; 1096 int mask, error, enabled; 1097 1098 error = 0; 1099 flags = ifp->if_flags; 1100 drv_flags = ifp->if_drv_flags; 1101 switch (cmd) { 1102 case SIOCSIFFLAGS: 1103 ATE_LOCK(sc); 1104 if ((flags & IFF_UP) != 0) { 1105 if ((drv_flags & IFF_DRV_RUNNING) != 0) { 1106 if (((flags ^ sc->if_flags) 1107 & (IFF_PROMISC | IFF_ALLMULTI)) != 0) 1108 ate_rxfilter(sc); 1109 } else { 1110 if ((sc->flags & ATE_FLAG_DETACHING) == 0) 1111 ateinit_locked(sc); 1112 } 1113 } else if ((drv_flags & IFF_DRV_RUNNING) != 0) { 1114 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1115 atestop(sc); 1116 } 1117 sc->if_flags = flags; 1118 ATE_UNLOCK(sc); 1119 break; 1120 1121 case SIOCADDMULTI: 1122 case SIOCDELMULTI: 1123 if ((drv_flags & IFF_DRV_RUNNING) != 0) { 1124 ATE_LOCK(sc); 1125 enabled = ate_setmcast(sc); 1126 if (enabled != (sc->flags & ATE_FLAG_MULTICAST)) 1127 ate_rxfilter(sc); 1128 ATE_UNLOCK(sc); 1129 } 1130 break; 1131 1132 case SIOCSIFMEDIA: 1133 case SIOCGIFMEDIA: 1134 mii = device_get_softc(sc->miibus); 1135 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 1136 break; 1137 case SIOCSIFCAP: 1138 mask = ifp->if_capenable ^ ifr->ifr_reqcap; 1139 if (mask & IFCAP_VLAN_MTU) { 1140 ATE_LOCK(sc); 1141 if (ifr->ifr_reqcap & IFCAP_VLAN_MTU) { 1142 WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) | ETH_CFG_BIG); 1143 ifp->if_capenable |= IFCAP_VLAN_MTU; 1144 } else { 1145 WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) & ~ETH_CFG_BIG); 1146 ifp->if_capenable &= ~IFCAP_VLAN_MTU; 1147 } 1148 ATE_UNLOCK(sc); 1149 } 1150 default: 1151 error = ether_ioctl(ifp, cmd, data); 1152 break; 1153 } 1154 return (error); 1155} 1156 1157static void 1158ate_child_detached(device_t dev, device_t child) 1159{ 1160 struct ate_softc *sc; 1161 1162 sc = device_get_softc(dev); 1163 if (child == sc->miibus) 1164 sc->miibus = NULL; 1165} 1166 1167/* 1168 * MII bus support routines. 1169 */ 1170static int 1171ate_miibus_readreg(device_t dev, int phy, int reg) 1172{ 1173 struct ate_softc *sc; 1174 int val; 1175 1176 /* 1177 * XXX if we implement agressive power savings, then we need 1178 * XXX to make sure that the clock to the emac is on here 1179 */ 1180 1181 sc = device_get_softc(dev); 1182 DELAY(1); /* Hangs w/o this delay really 30.5us atm */ 1183 WR4(sc, ETH_MAN, ETH_MAN_REG_RD(phy, reg)); 1184 while ((RD4(sc, ETH_SR) & ETH_SR_IDLE) == 0) 1185 continue; 1186 val = RD4(sc, ETH_MAN) & ETH_MAN_VALUE_MASK; 1187 1188 return (val); 1189} 1190 1191static int 1192ate_miibus_writereg(device_t dev, int phy, int reg, int data) 1193{ 1194 struct ate_softc *sc; 1195 1196 /* 1197 * XXX if we implement agressive power savings, then we need 1198 * XXX to make sure that the clock to the emac is on here 1199 */ 1200 1201 sc = device_get_softc(dev); 1202 WR4(sc, ETH_MAN, ETH_MAN_REG_WR(phy, reg, data)); 1203 while ((RD4(sc, ETH_SR) & ETH_SR_IDLE) == 0) 1204 continue; 1205 return (0); 1206} 1207 1208static device_method_t ate_methods[] = { 1209 /* Device interface */ 1210 DEVMETHOD(device_probe, ate_probe), 1211 DEVMETHOD(device_attach, ate_attach), 1212 DEVMETHOD(device_detach, ate_detach), 1213 1214 /* Bus interface */ 1215 DEVMETHOD(bus_child_detached, ate_child_detached), 1216 1217 /* MII interface */ 1218 DEVMETHOD(miibus_readreg, ate_miibus_readreg), 1219 DEVMETHOD(miibus_writereg, ate_miibus_writereg), 1220 1221 { 0, 0 } 1222}; 1223 1224static driver_t ate_driver = { 1225 "ate", 1226 ate_methods, 1227 sizeof(struct ate_softc), 1228}; 1229 1230DRIVER_MODULE(ate, atmelarm, ate_driver, ate_devclass, 0, 0); 1231DRIVER_MODULE(miibus, ate, miibus_driver, miibus_devclass, 0, 0); 1232MODULE_DEPEND(ate, miibus, 1, 1, 1); 1233MODULE_DEPEND(ate, ether, 1, 1, 1); 1234