if_ate.c revision 166454
1/*- 2 * Copyright (c) 2006 M. Warner Losh. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 14 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 15 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 16 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 19 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 20 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 23 */ 24 25/* TODO: (in no order) 26 * 27 * 8) Need to sync busdma goo in atestop 28 * 9) atestop should maybe free the mbufs? 29 * 30 * 1) detach 31 * 2) Free dma setup 32 * 3) Turn on the clock in pmc? Turn off? 33 */ 34 35#include <sys/cdefs.h> 36__FBSDID("$FreeBSD: head/sys/arm/at91/if_ate.c 166454 2007-02-03 07:46:26Z kevlo $"); 37 38#include <sys/param.h> 39#include <sys/systm.h> 40#include <sys/bus.h> 41#include <sys/kernel.h> 42#include <sys/mbuf.h> 43#include <sys/malloc.h> 44#include <sys/module.h> 45#include <sys/rman.h> 46#include <sys/socket.h> 47#include <sys/sockio.h> 48#include <sys/sysctl.h> 49#include <machine/bus.h> 50 51#include <net/ethernet.h> 52#include <net/if.h> 53#include <net/if_arp.h> 54#include <net/if_dl.h> 55#include <net/if_media.h> 56#include <net/if_mib.h> 57#include <net/if_types.h> 58 59#ifdef INET 60#include <netinet/in.h> 61#include <netinet/in_systm.h> 62#include <netinet/in_var.h> 63#include <netinet/ip.h> 64#endif 65 66#include <net/bpf.h> 67#include <net/bpfdesc.h> 68 69#include <dev/mii/mii.h> 70#include <dev/mii/miivar.h> 71#include <arm/at91/if_atereg.h> 72 73#include "miibus_if.h" 74 75#define ATE_MAX_TX_BUFFERS 2 /* We have ping-pong tx buffers */ 76#define ATE_MAX_RX_BUFFERS 64 77 78struct ate_softc 79{ 80 struct ifnet *ifp; /* ifnet pointer */ 81 struct mtx sc_mtx; /* basically a perimeter lock */ 82 device_t dev; /* Myself */ 83 device_t miibus; /* My child miibus */ 84 void *intrhand; /* Interrupt handle */ 85 struct resource *irq_res; /* IRQ resource */ 86 struct resource *mem_res; /* Memory resource */ 87 struct callout tick_ch; /* Tick callout */ 88 bus_dma_tag_t mtag; /* bus dma tag for mbufs */ 89 bus_dmamap_t tx_map[ATE_MAX_TX_BUFFERS]; 90 struct mbuf *sent_mbuf[ATE_MAX_TX_BUFFERS]; /* Sent mbufs */ 91 bus_dma_tag_t rxtag; 92 bus_dmamap_t rx_map[ATE_MAX_RX_BUFFERS]; 93 void *rx_buf[ATE_MAX_RX_BUFFERS]; /* RX buffer space */ 94 int rx_buf_ptr; 95 bus_dma_tag_t rx_desc_tag; 96 bus_dmamap_t rx_desc_map; 97 int txcur; /* current tx map pointer */ 98 bus_addr_t rx_desc_phys; 99 eth_rx_desc_t *rx_descs; 100 int use_rmii; 101 struct ifmib_iso_8802_3 mibdata; /* stuff for network mgmt */ 102}; 103 104static inline uint32_t 105RD4(struct ate_softc *sc, bus_size_t off) 106{ 107 return bus_read_4(sc->mem_res, off); 108} 109 110static inline void 111WR4(struct ate_softc *sc, bus_size_t off, uint32_t val) 112{ 113 bus_write_4(sc->mem_res, off, val); 114} 115 116#define ATE_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 117#define ATE_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 118#define ATE_LOCK_INIT(_sc) \ 119 mtx_init(&_sc->sc_mtx, device_get_nameunit(_sc->dev), \ 120 MTX_NETWORK_LOCK, MTX_DEF) 121#define ATE_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx); 122#define ATE_ASSERT_LOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_OWNED); 123#define ATE_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_NOTOWNED); 124 125static devclass_t ate_devclass; 126 127/* ifnet entry points */ 128 129static void ateinit_locked(void *); 130static void atestart_locked(struct ifnet *); 131 132static void ateinit(void *); 133static void atestart(struct ifnet *); 134static void atestop(struct ate_softc *); 135static int ateioctl(struct ifnet * ifp, u_long, caddr_t); 136 137/* bus entry points */ 138 139static int ate_probe(device_t dev); 140static int ate_attach(device_t dev); 141static int ate_detach(device_t dev); 142static void ate_intr(void *); 143 144/* helper routines */ 145static int ate_activate(device_t dev); 146static void ate_deactivate(device_t dev); 147static int ate_ifmedia_upd(struct ifnet *ifp); 148static void ate_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr); 149static void ate_get_mac(struct ate_softc *sc, u_char *eaddr); 150static void ate_set_mac(struct ate_softc *sc, u_char *eaddr); 151 152/* 153 * The AT91 family of products has the ethernet called EMAC. However, 154 * it isn't self identifying. It is anticipated that the parent bus 155 * code will take care to only add ate devices where they really are. As 156 * such, we do nothing here to identify the device and just set its name. 157 */ 158static int 159ate_probe(device_t dev) 160{ 161 device_set_desc(dev, "EMAC"); 162 return (0); 163} 164 165static int 166ate_attach(device_t dev) 167{ 168 struct ate_softc *sc = device_get_softc(dev); 169 struct ifnet *ifp = NULL; 170 struct sysctl_ctx_list *sctx; 171 struct sysctl_oid *soid; 172 int err; 173 u_char eaddr[6]; 174 175 sc->dev = dev; 176 err = ate_activate(dev); 177 if (err) 178 goto out; 179 180 sc->use_rmii = (RD4(sc, ETH_CFG) & ETH_CFG_RMII) == ETH_CFG_RMII; 181 182 183 /*Sysctls*/ 184 sctx = device_get_sysctl_ctx(dev); 185 soid = device_get_sysctl_tree(dev); 186 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "rmii", 187 CTLFLAG_RD, &sc->use_rmii, 0, "rmii in use"); 188 189 /* calling atestop before ifp is set is OK */ 190 atestop(sc); 191 ATE_LOCK_INIT(sc); 192 callout_init_mtx(&sc->tick_ch, &sc->sc_mtx, 0); 193 194 ate_get_mac(sc, eaddr); 195 ate_set_mac(sc, eaddr); 196 197 sc->ifp = ifp = if_alloc(IFT_ETHER); 198 if (mii_phy_probe(dev, &sc->miibus, ate_ifmedia_upd, ate_ifmedia_sts)) { 199 device_printf(dev, "Cannot find my PHY.\n"); 200 err = ENXIO; 201 goto out; 202 } 203 204 ifp->if_softc = sc; 205 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 206 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 207 ifp->if_capabilities |= IFCAP_VLAN_MTU; 208 ifp->if_capenable |= IFCAP_VLAN_MTU; /* the hw bits already set */ 209 ifp->if_start = atestart; 210 ifp->if_ioctl = ateioctl; 211 ifp->if_init = ateinit; 212 ifp->if_baudrate = 10000000; 213 IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN); 214 ifp->if_snd.ifq_maxlen = IFQ_MAXLEN; 215 IFQ_SET_READY(&ifp->if_snd); 216 ifp->if_timer = 0; 217 ifp->if_linkmib = &sc->mibdata; 218 ifp->if_linkmiblen = sizeof(sc->mibdata); 219 sc->mibdata.dot3Compliance = DOT3COMPLIANCE_COLLS; 220 221 ether_ifattach(ifp, eaddr); 222 223 /* 224 * Activate the interrupt 225 */ 226 err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_NET | INTR_MPSAFE, 227 ate_intr, sc, &sc->intrhand); 228 if (err) { 229 ether_ifdetach(ifp); 230 ATE_LOCK_DESTROY(sc); 231 } 232out:; 233 if (err) 234 ate_deactivate(dev); 235 if (err && ifp) 236 if_free(ifp); 237 return (err); 238} 239 240static int 241ate_detach(device_t dev) 242{ 243 return EBUSY; /* XXX TODO(1) */ 244} 245 246static void 247ate_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 248{ 249 struct ate_softc *sc; 250 251 if (error != 0) 252 return; 253 sc = (struct ate_softc *)arg; 254 sc->rx_desc_phys = segs[0].ds_addr; 255} 256 257static void 258ate_load_rx_buf(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 259{ 260 struct ate_softc *sc; 261 int i; 262 263 if (error != 0) 264 return; 265 sc = (struct ate_softc *)arg; 266 i = sc->rx_buf_ptr; 267 268 /* 269 * For the last buffer, set the wrap bit so the controller 270 * restarts from the first descriptor. 271 */ 272 bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, BUS_DMASYNC_PREWRITE); 273 if (i == ATE_MAX_RX_BUFFERS - 1) 274 sc->rx_descs[i].addr = segs[0].ds_addr | ETH_WRAP_BIT; 275 else 276 sc->rx_descs[i].addr = segs[0].ds_addr; 277 bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, BUS_DMASYNC_POSTWRITE); 278 sc->rx_descs[i].status = 0; 279 /* Flush the memory in the mbuf */ 280 bus_dmamap_sync(sc->rxtag, sc->rx_map[i], BUS_DMASYNC_PREREAD); 281} 282 283/* 284 * Compute the multicast filter for this device using the standard 285 * algorithm. I wonder why this isn't in ether somewhere as a lot 286 * of different MAC chips use this method (or the reverse the bits) 287 * method. 288 */ 289static void 290ate_setmcast(struct ate_softc *sc) 291{ 292 uint32_t index; 293 uint32_t mcaf[2]; 294 u_char *af = (u_char *) mcaf; 295 struct ifmultiaddr *ifma; 296 297 mcaf[0] = 0; 298 mcaf[1] = 0; 299 300 IF_ADDR_LOCK(sc->ifp); 301 TAILQ_FOREACH(ifma, &sc->ifp->if_multiaddrs, ifma_link) { 302 if (ifma->ifma_addr->sa_family != AF_LINK) 303 continue; 304 index = ether_crc32_be(LLADDR((struct sockaddr_dl *) 305 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 306 af[index >> 3] |= 1 << (index & 7); 307 } 308 IF_ADDR_UNLOCK(sc->ifp); 309 310 /* 311 * Write the hash to the hash register. This card can also 312 * accept unicast packets as well as multicast packets using this 313 * register for easier bridging operations, but we don't take 314 * advantage of that. Locks here are to avoid LOR with the 315 * IF_ADDR_LOCK, but might not be strictly necessary. 316 */ 317 WR4(sc, ETH_HSL, mcaf[0]); 318 WR4(sc, ETH_HSH, mcaf[1]); 319} 320 321static int 322ate_activate(device_t dev) 323{ 324 struct ate_softc *sc; 325 int rid, err, i; 326 327 sc = device_get_softc(dev); 328 rid = 0; 329 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 330 RF_ACTIVE); 331 if (sc->mem_res == NULL) 332 goto errout; 333 rid = 0; 334 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 335 RF_ACTIVE); 336 if (sc->irq_res == NULL) 337 goto errout; 338 339 /* 340 * Allocate DMA tags and maps 341 */ 342 err = bus_dma_tag_create(NULL, 1, 0, BUS_SPACE_MAXADDR_32BIT, 343 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 1, MCLBYTES, 0, 344 busdma_lock_mutex, &sc->sc_mtx, &sc->mtag); 345 if (err != 0) 346 goto errout; 347 for (i = 0; i < ATE_MAX_TX_BUFFERS; i++) { 348 err = bus_dmamap_create(sc->mtag, 0, &sc->tx_map[i]); 349 if (err != 0) 350 goto errout; 351 } 352 /* 353 * Allocate our Rx buffers. This chip has a rx structure that's filled 354 * in 355 */ 356 357 /* 358 * Allocate DMA tags and maps for RX. 359 */ 360 err = bus_dma_tag_create(NULL, 1, 0, BUS_SPACE_MAXADDR_32BIT, 361 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 1, MCLBYTES, 0, 362 busdma_lock_mutex, &sc->sc_mtx, &sc->rxtag); 363 if (err != 0) 364 goto errout; 365 366 /* Dma TAG and MAP for the rx descriptors. */ 367 err = bus_dma_tag_create(NULL, sizeof(eth_rx_desc_t), 0, 368 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 369 ATE_MAX_RX_BUFFERS * sizeof(eth_rx_desc_t), 1, 370 ATE_MAX_RX_BUFFERS * sizeof(eth_rx_desc_t), 0, busdma_lock_mutex, 371 &sc->sc_mtx, &sc->rx_desc_tag); 372 if (err != 0) 373 goto errout; 374 if (bus_dmamem_alloc(sc->rx_desc_tag, (void **)&sc->rx_descs, 375 BUS_DMA_NOWAIT | BUS_DMA_COHERENT, &sc->rx_desc_map) != 0) 376 goto errout; 377 if (bus_dmamap_load(sc->rx_desc_tag, sc->rx_desc_map, 378 sc->rx_descs, ATE_MAX_RX_BUFFERS * sizeof(eth_rx_desc_t), 379 ate_getaddr, sc, 0) != 0) 380 goto errout; 381 /* XXX TODO(5) Put this in ateinit_locked? */ 382 for (i = 0; i < ATE_MAX_RX_BUFFERS; i++) { 383 sc->rx_buf_ptr = i; 384 if (bus_dmamem_alloc(sc->rxtag, (void **)&sc->rx_buf[i], 385 BUS_DMA_NOWAIT, &sc->rx_map[i]) != 0) 386 goto errout; 387 if (bus_dmamap_load(sc->rxtag, sc->rx_map[i], sc->rx_buf[i], 388 MCLBYTES, ate_load_rx_buf, sc, 0) != 0) 389 goto errout; 390 } 391 sc->rx_buf_ptr = 0; 392 /* Flush the memory for the EMAC rx descriptor */ 393 bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, BUS_DMASYNC_PREWRITE); 394 /* Write the descriptor queue address. */ 395 WR4(sc, ETH_RBQP, sc->rx_desc_phys); 396 return (0); 397errout: 398 ate_deactivate(dev); 399 return (ENOMEM); 400} 401 402static void 403ate_deactivate(device_t dev) 404{ 405 struct ate_softc *sc; 406 407 sc = device_get_softc(dev); 408 /* XXX TODO(2) teardown busdma junk, below from fxp -- customize */ 409#if 0 410 if (sc->fxp_mtag) { 411 for (i = 0; i < FXP_NRFABUFS; i++) { 412 rxp = &sc->fxp_desc.rx_list[i]; 413 if (rxp->rx_mbuf != NULL) { 414 bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map, 415 BUS_DMASYNC_POSTREAD); 416 bus_dmamap_unload(sc->fxp_mtag, rxp->rx_map); 417 m_freem(rxp->rx_mbuf); 418 } 419 bus_dmamap_destroy(sc->fxp_mtag, rxp->rx_map); 420 } 421 bus_dmamap_destroy(sc->fxp_mtag, sc->spare_map); 422 for (i = 0; i < FXP_NTXCB; i++) { 423 txp = &sc->fxp_desc.tx_list[i]; 424 if (txp->tx_mbuf != NULL) { 425 bus_dmamap_sync(sc->fxp_mtag, txp->tx_map, 426 BUS_DMASYNC_POSTWRITE); 427 bus_dmamap_unload(sc->fxp_mtag, txp->tx_map); 428 m_freem(txp->tx_mbuf); 429 } 430 bus_dmamap_destroy(sc->fxp_mtag, txp->tx_map); 431 } 432 bus_dma_tag_destroy(sc->fxp_mtag); 433 } 434 if (sc->fxp_stag) 435 bus_dma_tag_destroy(sc->fxp_stag); 436 if (sc->cbl_tag) 437 bus_dma_tag_destroy(sc->cbl_tag); 438 if (sc->mcs_tag) 439 bus_dma_tag_destroy(sc->mcs_tag); 440#endif 441 if (sc->intrhand) 442 bus_teardown_intr(dev, sc->irq_res, sc->intrhand); 443 sc->intrhand = 0; 444 bus_generic_detach(sc->dev); 445 if (sc->miibus) 446 device_delete_child(sc->dev, sc->miibus); 447 if (sc->mem_res) 448 bus_release_resource(dev, SYS_RES_IOPORT, 449 rman_get_rid(sc->mem_res), sc->mem_res); 450 sc->mem_res = 0; 451 if (sc->irq_res) 452 bus_release_resource(dev, SYS_RES_IRQ, 453 rman_get_rid(sc->irq_res), sc->irq_res); 454 sc->irq_res = 0; 455 return; 456} 457 458/* 459 * Change media according to request. 460 */ 461static int 462ate_ifmedia_upd(struct ifnet *ifp) 463{ 464 struct ate_softc *sc = ifp->if_softc; 465 struct mii_data *mii; 466 467 mii = device_get_softc(sc->miibus); 468 ATE_LOCK(sc); 469 mii_mediachg(mii); 470 ATE_UNLOCK(sc); 471 return (0); 472} 473 474/* 475 * Notify the world which media we're using. 476 */ 477static void 478ate_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 479{ 480 struct ate_softc *sc = ifp->if_softc; 481 struct mii_data *mii; 482 483 mii = device_get_softc(sc->miibus); 484 ATE_LOCK(sc); 485 mii_pollstat(mii); 486 ifmr->ifm_active = mii->mii_media_active; 487 ifmr->ifm_status = mii->mii_media_status; 488 ATE_UNLOCK(sc); 489} 490 491static void 492ate_stat_update(struct ate_softc *sc, int active) 493{ 494 /* 495 * The speed and full/half-duplex state needs to be reflected 496 * in the ETH_CFG register. 497 */ 498 if (IFM_SUBTYPE(active) == IFM_10_T) 499 WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) & ~ETH_CFG_SPD); 500 else 501 WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) | ETH_CFG_SPD); 502 if (active & IFM_FDX) 503 WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) | ETH_CFG_FD); 504 else 505 WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) & ~ETH_CFG_FD); 506} 507 508static void 509ate_tick(void *xsc) 510{ 511 struct ate_softc *sc = xsc; 512 struct ifnet *ifp = sc->ifp; 513 struct mii_data *mii; 514 int active; 515 uint32_t c; 516 517 /* 518 * The KB920x boot loader tests ETH_SR & ETH_SR_LINK and will ask 519 * the MII if there's a link if this bit is clear. Not sure if we 520 * should do the same thing here or not. 521 */ 522 ATE_ASSERT_LOCKED(sc); 523 if (sc->miibus != NULL) { 524 mii = device_get_softc(sc->miibus); 525 active = mii->mii_media_active; 526 mii_tick(mii); 527 if (mii->mii_media_status & IFM_ACTIVE && 528 active != mii->mii_media_active) 529 ate_stat_update(sc, mii->mii_media_active); 530 } 531 532 /* 533 * Update the stats as best we can. When we're done, clear 534 * the status counters and start over. We're supposed to read these 535 * registers often enough that they won't overflow. Hopefully 536 * once a second is often enough. Some don't map well to 537 * the dot3Stats mib, so for those we just count them as general 538 * errors. Stats for iframes, ibutes, oframes and obytes are 539 * collected elsewhere. These registers zero on a read to prevent 540 * races. For all the collision stats, also update the collision 541 * stats for the interface. 542 */ 543 sc->mibdata.dot3StatsAlignmentErrors += RD4(sc, ETH_ALE); 544 sc->mibdata.dot3StatsFCSErrors += RD4(sc, ETH_SEQE); 545 c = RD4(sc, ETH_SCOL); 546 ifp->if_collisions += c; 547 sc->mibdata.dot3StatsSingleCollisionFrames += c; 548 c = RD4(sc, ETH_MCOL); 549 sc->mibdata.dot3StatsMultipleCollisionFrames += c; 550 ifp->if_collisions += c; 551 sc->mibdata.dot3StatsSQETestErrors += RD4(sc, ETH_SQEE); 552 sc->mibdata.dot3StatsDeferredTransmissions += RD4(sc, ETH_DTE); 553 c = RD4(sc, ETH_LCOL); 554 sc->mibdata.dot3StatsLateCollisions += c; 555 ifp->if_collisions += c; 556 c = RD4(sc, ETH_ECOL); 557 sc->mibdata.dot3StatsExcessiveCollisions += c; 558 ifp->if_collisions += c; 559 sc->mibdata.dot3StatsCarrierSenseErrors += RD4(sc, ETH_CSE); 560 sc->mibdata.dot3StatsFrameTooLongs += RD4(sc, ETH_ELR); 561 sc->mibdata.dot3StatsInternalMacReceiveErrors += RD4(sc, ETH_DRFC); 562 /* 563 * not sure where to lump these, so count them against the errors 564 * for the interface. 565 */ 566 sc->ifp->if_oerrors += RD4(sc, ETH_TUE); 567 sc->ifp->if_ierrors += RD4(sc, ETH_CDE) + RD4(sc, ETH_RJB) + 568 RD4(sc, ETH_USF); 569 570 /* 571 * Schedule another timeout one second from now. 572 */ 573 callout_reset(&sc->tick_ch, hz, ate_tick, sc); 574} 575 576static void 577ate_set_mac(struct ate_softc *sc, u_char *eaddr) 578{ 579 WR4(sc, ETH_SA1L, (eaddr[3] << 24) | (eaddr[2] << 16) | 580 (eaddr[1] << 8) | eaddr[0]); 581 WR4(sc, ETH_SA1H, (eaddr[5] << 8) | (eaddr[4])); 582 583} 584 585static void 586ate_get_mac(struct ate_softc *sc, u_char *eaddr) 587{ 588 uint32_t low, high; 589 590 /* 591 * The boot loader setup the MAC with an address, if one is set in 592 * the loader. The TSC loader will also set the MAC address in a 593 * similar way. Grab the MAC address from the SA1[HL] registers. 594 */ 595 low = RD4(sc, ETH_SA1L); 596 high = RD4(sc, ETH_SA1H); 597 eaddr[0] = (high >> 8) & 0xff; 598 eaddr[1] = high & 0xff; 599 eaddr[2] = (low >> 24) & 0xff; 600 eaddr[3] = (low >> 16) & 0xff; 601 eaddr[4] = (low >> 8) & 0xff; 602 eaddr[5] = low & 0xff; 603} 604 605static void 606ate_intr(void *xsc) 607{ 608 struct ate_softc *sc = xsc; 609 struct ifnet *ifp = sc->ifp; 610 int status; 611 int i; 612 void *bp; 613 struct mbuf *mb; 614 uint32_t rx_stat; 615 616 status = RD4(sc, ETH_ISR); 617 if (status == 0) 618 return; 619 if (status & ETH_ISR_RCOM) { 620 bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, 621 BUS_DMASYNC_POSTREAD); 622 while (sc->rx_descs[sc->rx_buf_ptr].addr & ETH_CPU_OWNER) { 623 i = sc->rx_buf_ptr; 624 sc->rx_buf_ptr = (i + 1) % ATE_MAX_RX_BUFFERS; 625 bp = sc->rx_buf[i]; 626 rx_stat = sc->rx_descs[i].status; 627 if ((rx_stat & ETH_LEN_MASK) == 0) { 628 printf("ignoring bogus 0 len packet\n"); 629 bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, 630 BUS_DMASYNC_PREWRITE); 631 sc->rx_descs[i].addr &= ~ETH_CPU_OWNER; 632 bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, 633 BUS_DMASYNC_POSTWRITE); 634 continue; 635 } 636 /* Flush memory for mbuf so we don't get stale bytes */ 637 bus_dmamap_sync(sc->rxtag, sc->rx_map[i], 638 BUS_DMASYNC_POSTREAD); 639 WR4(sc, ETH_RSR, RD4(sc, ETH_RSR)); 640 641 /* 642 * The length returned by the device includes the 643 * ethernet CRC calculation for the packet, but 644 * ifnet drivers are supposed to discard it. 645 */ 646 mb = m_devget(sc->rx_buf[i], 647 (rx_stat & ETH_LEN_MASK) - ETHER_CRC_LEN, 648 ETHER_ALIGN, ifp, NULL); 649 bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, 650 BUS_DMASYNC_PREWRITE); 651 sc->rx_descs[i].addr &= ~ETH_CPU_OWNER; 652 bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, 653 BUS_DMASYNC_POSTWRITE); 654 bus_dmamap_sync(sc->rxtag, sc->rx_map[i], 655 BUS_DMASYNC_PREREAD); 656 if (mb != NULL) { 657 ifp->if_ipackets++; 658 (*ifp->if_input)(ifp, mb); 659 } 660 661 } 662 } 663 if (status & ETH_ISR_TCOM) { 664 ATE_LOCK(sc); 665 /* XXX TSR register should be cleared */ 666 if (sc->sent_mbuf[0]) { 667 bus_dmamap_sync(sc->rxtag, sc->tx_map[0], 668 BUS_DMASYNC_POSTWRITE); 669 m_freem(sc->sent_mbuf[0]); 670 ifp->if_opackets++; 671 sc->sent_mbuf[0] = NULL; 672 } 673 if (sc->sent_mbuf[1]) { 674 if (RD4(sc, ETH_TSR) & ETH_TSR_IDLE) { 675 bus_dmamap_sync(sc->rxtag, sc->tx_map[1], 676 BUS_DMASYNC_POSTWRITE); 677 m_freem(sc->sent_mbuf[1]); 678 ifp->if_opackets++; 679 sc->txcur = 0; 680 sc->sent_mbuf[0] = sc->sent_mbuf[1] = NULL; 681 } else { 682 sc->sent_mbuf[0] = sc->sent_mbuf[1]; 683 sc->sent_mbuf[1] = NULL; 684 sc->txcur = 1; 685 } 686 } else { 687 sc->sent_mbuf[0] = NULL; 688 sc->txcur = 0; 689 } 690 /* 691 * We're no longer busy, so clear the busy flag and call the 692 * start routine to xmit more packets. 693 */ 694 sc->ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 695 atestart_locked(sc->ifp); 696 ATE_UNLOCK(sc); 697 } 698 if (status & ETH_ISR_RBNA) { 699 printf("RBNA workaround\n"); 700 /* Workaround Errata #11 */ 701 WR4(sc, ETH_CTL, RD4(sc, ETH_CTL) &~ ETH_CTL_RE); 702 WR4(sc, ETH_CTL, RD4(sc, ETH_CTL) | ETH_CTL_RE); 703 } 704} 705 706/* 707 * Reset and initialize the chip 708 */ 709static void 710ateinit_locked(void *xsc) 711{ 712 struct ate_softc *sc = xsc; 713 struct ifnet *ifp = sc->ifp; 714 struct mii_data *mii; 715 716 ATE_ASSERT_LOCKED(sc); 717 718 /* 719 * XXX TODO(3) 720 * we need to turn on the EMAC clock in the pmc. With the 721 * default boot loader, this is already turned on. However, we 722 * need to think about how best to turn it on/off as the interface 723 * is brought up/down, as well as dealing with the mii bus... 724 * 725 * We also need to multiplex the pins correctly. 726 */ 727 728 /* 729 * There are two different ways that the mii bus is connected 730 * to this chip. Select the right one based on a compile-time 731 * option. 732 */ 733 if (sc->use_rmii) 734 WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) | ETH_CFG_RMII); 735 else 736 WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) & ~ETH_CFG_RMII); 737 738 /* 739 * Turn on the multicast hash, and write 0's to it. 740 */ 741 WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) | ETH_CFG_MTI); 742 WR4(sc, ETH_HSH, 0); 743 WR4(sc, ETH_HSL, 0); 744 745 WR4(sc, ETH_CTL, RD4(sc, ETH_CTL) | ETH_CTL_TE | ETH_CTL_RE); 746 WR4(sc, ETH_IER, ETH_ISR_RCOM | ETH_ISR_TCOM | ETH_ISR_RBNA); 747 748 /* 749 * Boot loader fills in MAC address. If that's not the case, then 750 * we should set SA1L and SA1H here to the appropriate value. Note: 751 * the byte order is big endian, not little endian, so we have some 752 * swapping to do. Again, if we need it (which I don't think we do). 753 */ 754 ate_setmcast(sc); 755 756 /* enable big packets */ 757 WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) | ETH_CFG_BIG); 758 759 /* 760 * Set 'running' flag, and clear output active flag 761 * and attempt to start the output 762 */ 763 ifp->if_drv_flags |= IFF_DRV_RUNNING; 764 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 765 766 mii = device_get_softc(sc->miibus); 767 mii_pollstat(mii); 768 ate_stat_update(sc, mii->mii_media_active); 769 atestart_locked(ifp); 770 771 callout_reset(&sc->tick_ch, hz, ate_tick, sc); 772} 773 774/* 775 * dequeu packets and transmit 776 */ 777static void 778atestart_locked(struct ifnet *ifp) 779{ 780 struct ate_softc *sc = ifp->if_softc; 781 struct mbuf *m, *mdefrag; 782 bus_dma_segment_t segs[1]; 783 int nseg, e; 784 785 ATE_ASSERT_LOCKED(sc); 786 if (ifp->if_drv_flags & IFF_DRV_OACTIVE) 787 return; 788 789 while (sc->txcur < ATE_MAX_TX_BUFFERS) { 790 /* 791 * check to see if there's room to put another packet into the 792 * xmit queue. The EMAC chip has a ping-pong buffer for xmit 793 * packets. We use OACTIVE to indicate "we can stuff more into 794 * our buffers (clear) or not (set)." 795 */ 796 if (!(RD4(sc, ETH_TSR) & ETH_TSR_BNQ)) { 797 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 798 return; 799 } 800 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 801 if (m == 0) { 802 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 803 return; 804 } 805 e = bus_dmamap_load_mbuf_sg(sc->mtag, sc->tx_map[sc->txcur], m, 806 segs, &nseg, 0); 807 if (e == EFBIG) { 808 mdefrag = m_defrag(m, M_DONTWAIT); 809 if (mdefrag == NULL) { 810 IFQ_DRV_PREPEND(&ifp->if_snd, m); 811 return; 812 } 813 m = mdefrag; 814 e = bus_dmamap_load_mbuf_sg(sc->mtag, 815 sc->tx_map[sc->txcur], m, segs, &nseg, 0); 816 } 817 if (e != 0) { 818 m_freem(m); 819 continue; 820 } 821 bus_dmamap_sync(sc->mtag, sc->tx_map[sc->txcur], 822 BUS_DMASYNC_PREWRITE); 823 824 /* 825 * tell the hardware to xmit the packet. 826 */ 827 WR4(sc, ETH_TAR, segs[0].ds_addr); 828 WR4(sc, ETH_TCR, segs[0].ds_len); 829 830 /* 831 * Tap off here if there is a bpf listener. 832 */ 833 BPF_MTAP(ifp, m); 834 835 sc->sent_mbuf[sc->txcur] = m; 836 sc->txcur++; 837 } 838} 839 840static void 841ateinit(void *xsc) 842{ 843 struct ate_softc *sc = xsc; 844 ATE_LOCK(sc); 845 ateinit_locked(sc); 846 ATE_UNLOCK(sc); 847} 848 849static void 850atestart(struct ifnet *ifp) 851{ 852 struct ate_softc *sc = ifp->if_softc; 853 ATE_LOCK(sc); 854 atestart_locked(ifp); 855 ATE_UNLOCK(sc); 856} 857 858/* 859 * Turn off interrupts, and stop the nic. Can be called with sc->ifp NULL 860 * so be careful. 861 */ 862static void 863atestop(struct ate_softc *sc) 864{ 865 struct ifnet *ifp = sc->ifp; 866 867 if (ifp) { 868 ifp->if_timer = 0; 869 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 870 } 871 872 callout_stop(&sc->tick_ch); 873 874 /* 875 * Enable some parts of the MAC that are needed always (like the 876 * MII bus. This turns off the RE and TE bits, which will remain 877 * off until ateinit() is called to turn them on. With RE and TE 878 * turned off, there's no DMA to worry about after this write. 879 */ 880 WR4(sc, ETH_CTL, ETH_CTL_MPE); 881 882 /* 883 * Turn off all the configured options and revert to defaults. 884 */ 885 WR4(sc, ETH_CFG, ETH_CFG_CLK_32); 886 887 /* 888 * Turn off all the interrupts, and ack any pending ones by reading 889 * the ISR. 890 */ 891 WR4(sc, ETH_IDR, 0xffffffff); 892 RD4(sc, ETH_ISR); 893 894 /* 895 * Clear out the Transmit and Receiver Status registers of any 896 * errors they may be reporting 897 */ 898 WR4(sc, ETH_TSR, 0xffffffff); 899 WR4(sc, ETH_RSR, 0xffffffff); 900 901 /* 902 * XXX TODO(8) 903 * need to worry about the busdma resources? Yes, I think we need 904 * to sync and unload them. We may also need to release the mbufs 905 * that are assocaited with RX and TX operations. 906 */ 907 908 /* 909 * XXX we should power down the EMAC if it isn't in use, after 910 * putting it into loopback mode. This saves about 400uA according 911 * to the datasheet. 912 */ 913} 914 915static int 916ateioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 917{ 918 struct ate_softc *sc = ifp->if_softc; 919 struct mii_data *mii; 920 struct ifreq *ifr = (struct ifreq *)data; 921 int mask, error = 0; 922 923 switch (cmd) { 924 case SIOCSIFFLAGS: 925 ATE_LOCK(sc); 926 if ((ifp->if_flags & IFF_UP) == 0 && 927 ifp->if_drv_flags & IFF_DRV_RUNNING) { 928 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 929 atestop(sc); 930 } else { 931 /* reinitialize card on any parameter change */ 932 ateinit_locked(sc); 933 } 934 ATE_UNLOCK(sc); 935 break; 936 937 case SIOCADDMULTI: 938 case SIOCDELMULTI: 939 /* update multicast filter list. */ 940 ATE_LOCK(sc); 941 ate_setmcast(sc); 942 ATE_UNLOCK(sc); 943 error = 0; 944 break; 945 946 case SIOCSIFMEDIA: 947 case SIOCGIFMEDIA: 948 mii = device_get_softc(sc->miibus); 949 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 950 break; 951 case SIOCSIFCAP: 952 mask = ifp->if_capenable ^ ifr->ifr_reqcap; 953 if (mask & IFCAP_VLAN_MTU) { 954 ATE_LOCK(sc); 955 if (ifr->ifr_reqcap & IFCAP_VLAN_MTU) { 956 WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) | ETH_CFG_BIG); 957 ifp->if_capenable |= IFCAP_VLAN_MTU; 958 } else { 959 WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) & ~ETH_CFG_BIG); 960 ifp->if_capenable &= ~IFCAP_VLAN_MTU; 961 } 962 ATE_UNLOCK(sc); 963 } 964 default: 965 error = ether_ioctl(ifp, cmd, data); 966 break; 967 } 968 return (error); 969} 970 971static void 972ate_child_detached(device_t dev, device_t child) 973{ 974 struct ate_softc *sc; 975 976 sc = device_get_softc(dev); 977 if (child == sc->miibus) 978 sc->miibus = NULL; 979} 980 981/* 982 * MII bus support routines. 983 */ 984static int 985ate_miibus_readreg(device_t dev, int phy, int reg) 986{ 987 struct ate_softc *sc; 988 int val; 989 990 /* 991 * XXX if we implement agressive power savings, then we need 992 * XXX to make sure that the clock to the emac is on here 993 */ 994 995 if (phy != 0) 996 return (0xffff); 997 sc = device_get_softc(dev); 998 DELAY(1); /* Hangs w/o this delay really 30.5us atm */ 999 WR4(sc, ETH_MAN, ETH_MAN_REG_RD(phy, reg)); 1000 while ((RD4(sc, ETH_SR) & ETH_SR_IDLE) == 0) 1001 continue; 1002 val = RD4(sc, ETH_MAN) & ETH_MAN_VALUE_MASK; 1003 1004 return (val); 1005} 1006 1007static void 1008ate_miibus_writereg(device_t dev, int phy, int reg, int data) 1009{ 1010 struct ate_softc *sc; 1011 1012 /* 1013 * XXX if we implement agressive power savings, then we need 1014 * XXX to make sure that the clock to the emac is on here 1015 */ 1016 1017 sc = device_get_softc(dev); 1018 WR4(sc, ETH_MAN, ETH_MAN_REG_WR(phy, reg, data)); 1019 while ((RD4(sc, ETH_SR) & ETH_SR_IDLE) == 0) 1020 continue; 1021 return; 1022} 1023 1024static device_method_t ate_methods[] = { 1025 /* Device interface */ 1026 DEVMETHOD(device_probe, ate_probe), 1027 DEVMETHOD(device_attach, ate_attach), 1028 DEVMETHOD(device_detach, ate_detach), 1029 1030 /* Bus interface */ 1031 DEVMETHOD(bus_child_detached, ate_child_detached), 1032 1033 /* MII interface */ 1034 DEVMETHOD(miibus_readreg, ate_miibus_readreg), 1035 DEVMETHOD(miibus_writereg, ate_miibus_writereg), 1036 1037 { 0, 0 } 1038}; 1039 1040static driver_t ate_driver = { 1041 "ate", 1042 ate_methods, 1043 sizeof(struct ate_softc), 1044}; 1045 1046DRIVER_MODULE(ate, atmelarm, ate_driver, ate_devclass, 0, 0); 1047DRIVER_MODULE(miibus, ate, miibus_driver, miibus_devclass, 0, 0); 1048MODULE_DEPEND(ate, miibus, 1, 1, 1); 1049MODULE_DEPEND(ate, ether, 1, 1, 1); 1050