if_ate.c revision 165712
1/*- 2 * Copyright (c) 2006 M. Warner Losh. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 14 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 15 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 16 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 19 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 20 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 23 */ 24 25/* TODO: (in no order) 26 * 27 * 8) Need to sync busdma goo in atestop 28 * 9) atestop should maybe free the mbufs? 29 * 30 * 1) detach 31 * 2) Free dma setup 32 * 3) Turn on the clock in pmc? Turn off? 33 */ 34 35#include <sys/cdefs.h> 36__FBSDID("$FreeBSD: head/sys/arm/at91/if_ate.c 165712 2007-01-01 00:48:25Z imp $"); 37 38#include <sys/param.h> 39#include <sys/systm.h> 40#include <sys/bus.h> 41#include <sys/kernel.h> 42#include <sys/mbuf.h> 43#include <sys/malloc.h> 44#include <sys/module.h> 45#include <sys/rman.h> 46#include <sys/socket.h> 47#include <sys/sockio.h> 48#include <sys/sysctl.h> 49#include <machine/bus.h> 50 51#include <net/ethernet.h> 52#include <net/if.h> 53#include <net/if_arp.h> 54#include <net/if_dl.h> 55#include <net/if_media.h> 56#include <net/if_mib.h> 57#include <net/if_types.h> 58 59#ifdef INET 60#include <netinet/in.h> 61#include <netinet/in_systm.h> 62#include <netinet/in_var.h> 63#include <netinet/ip.h> 64#endif 65 66#include <net/bpf.h> 67#include <net/bpfdesc.h> 68 69#include <dev/mii/mii.h> 70#include <dev/mii/miivar.h> 71#include <arm/at91/if_atereg.h> 72 73#include "miibus_if.h" 74 75#define ATE_MAX_TX_BUFFERS 64 /* We have ping-pong tx buffers */ 76#define ATE_MAX_RX_BUFFERS 64 77 78struct ate_softc 79{ 80 struct ifnet *ifp; /* ifnet pointer */ 81 struct mtx sc_mtx; /* basically a perimeter lock */ 82 device_t dev; /* Myself */ 83 device_t miibus; /* My child miibus */ 84 void *intrhand; /* Interrupt handle */ 85 struct resource *irq_res; /* IRQ resource */ 86 struct resource *mem_res; /* Memory resource */ 87 struct callout tick_ch; /* Tick callout */ 88 bus_dma_tag_t mtag; /* bus dma tag for mbufs */ 89 bus_dmamap_t tx_map[ATE_MAX_TX_BUFFERS]; 90 struct mbuf *sent_mbuf[ATE_MAX_TX_BUFFERS]; /* Sent mbufs */ 91 bus_dma_tag_t rxtag; 92 bus_dmamap_t rx_map[ATE_MAX_RX_BUFFERS]; 93 void *rx_buf[ATE_MAX_RX_BUFFERS]; /* RX buffer space */ 94 int rx_buf_ptr; 95 bus_dma_tag_t rx_desc_tag; 96 bus_dmamap_t rx_desc_map; 97 int txcur; /* current tx map pointer */ 98 bus_addr_t rx_desc_phys; 99 eth_rx_desc_t *rx_descs; 100 int use_rmii; 101 struct ifmib_iso_8802_3 mibdata; /* stuff for network mgmt */ 102}; 103 104static inline uint32_t 105RD4(struct ate_softc *sc, bus_size_t off) 106{ 107 return bus_read_4(sc->mem_res, off); 108} 109 110static inline void 111WR4(struct ate_softc *sc, bus_size_t off, uint32_t val) 112{ 113 bus_write_4(sc->mem_res, off, val); 114} 115 116#define ATE_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 117#define ATE_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 118#define ATE_LOCK_INIT(_sc) \ 119 mtx_init(&_sc->sc_mtx, device_get_nameunit(_sc->dev), \ 120 MTX_NETWORK_LOCK, MTX_DEF) 121#define ATE_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx); 122#define ATE_ASSERT_LOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_OWNED); 123#define ATE_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_NOTOWNED); 124 125static devclass_t ate_devclass; 126 127/* ifnet entry points */ 128 129static void ateinit_locked(void *); 130static void atestart_locked(struct ifnet *); 131 132static void ateinit(void *); 133static void atestart(struct ifnet *); 134static void atestop(struct ate_softc *); 135static int ateioctl(struct ifnet * ifp, u_long, caddr_t); 136 137/* bus entry points */ 138 139static int ate_probe(device_t dev); 140static int ate_attach(device_t dev); 141static int ate_detach(device_t dev); 142static void ate_intr(void *); 143 144/* helper routines */ 145static int ate_activate(device_t dev); 146static void ate_deactivate(device_t dev); 147static int ate_ifmedia_upd(struct ifnet *ifp); 148static void ate_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr); 149static void ate_get_mac(struct ate_softc *sc, u_char *eaddr); 150static void ate_set_mac(struct ate_softc *sc, u_char *eaddr); 151 152/* 153 * The AT91 family of products has the ethernet called EMAC. However, 154 * it isn't self identifying. It is anticipated that the parent bus 155 * code will take care to only add ate devices where they really are. As 156 * such, we do nothing here to identify the device and just set its name. 157 */ 158static int 159ate_probe(device_t dev) 160{ 161 device_set_desc(dev, "EMAC"); 162 return (0); 163} 164 165static int 166ate_attach(device_t dev) 167{ 168 struct ate_softc *sc = device_get_softc(dev); 169 struct ifnet *ifp = NULL; 170 struct sysctl_ctx_list *sctx; 171 struct sysctl_oid *soid; 172 int err; 173 u_char eaddr[6]; 174 175 sc->dev = dev; 176 err = ate_activate(dev); 177 if (err) 178 goto out; 179 180 sc->use_rmii = (RD4(sc, ETH_CFG) & ETH_CFG_RMII) == ETH_CFG_RMII; 181 182 183 /*Sysctls*/ 184 sctx = device_get_sysctl_ctx(dev); 185 soid = device_get_sysctl_tree(dev); 186 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "rmii", 187 CTLFLAG_RD, &sc->use_rmii, 0, "rmii in use"); 188 189 /* calling atestop before ifp is set is OK */ 190 atestop(sc); 191 ATE_LOCK_INIT(sc); 192 callout_init_mtx(&sc->tick_ch, &sc->sc_mtx, 0); 193 194 ate_get_mac(sc, eaddr); 195 ate_set_mac(sc, eaddr); 196 197 sc->ifp = ifp = if_alloc(IFT_ETHER); 198 if (mii_phy_probe(dev, &sc->miibus, ate_ifmedia_upd, ate_ifmedia_sts)) { 199 device_printf(dev, "Cannot find my PHY.\n"); 200 err = ENXIO; 201 goto out; 202 } 203 204 ifp->if_softc = sc; 205 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 206 ifp->if_mtu = ETHERMTU; 207 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 208 ifp->if_start = atestart; 209 ifp->if_ioctl = ateioctl; 210 ifp->if_init = ateinit; 211 ifp->if_baudrate = 10000000; 212 IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN); 213 ifp->if_snd.ifq_maxlen = IFQ_MAXLEN; 214 IFQ_SET_READY(&ifp->if_snd); 215 ifp->if_timer = 0; 216 ifp->if_linkmib = &sc->mibdata; 217 ifp->if_linkmiblen = sizeof(sc->mibdata); 218 sc->mibdata.dot3Compliance = DOT3COMPLIANCE_COLLS; 219 220 ether_ifattach(ifp, eaddr); 221 222 /* 223 * Activate the interrupt 224 */ 225 err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_NET | INTR_MPSAFE, 226 ate_intr, sc, &sc->intrhand); 227 if (err) { 228 ether_ifdetach(ifp); 229 ATE_LOCK_DESTROY(sc); 230 } 231out:; 232 if (err) 233 ate_deactivate(dev); 234 if (err && ifp) 235 if_free(ifp); 236 return (err); 237} 238 239static int 240ate_detach(device_t dev) 241{ 242 return EBUSY; /* XXX TODO(1) */ 243} 244 245static void 246ate_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 247{ 248 struct ate_softc *sc; 249 250 if (error != 0) 251 return; 252 sc = (struct ate_softc *)arg; 253 sc->rx_desc_phys = segs[0].ds_addr; 254} 255 256static void 257ate_load_rx_buf(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 258{ 259 struct ate_softc *sc; 260 int i; 261 262 if (error != 0) 263 return; 264 sc = (struct ate_softc *)arg; 265 i = sc->rx_buf_ptr; 266 267 /* 268 * For the last buffer, set the wrap bit so the controller 269 * restarts from the first descriptor. 270 */ 271 bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, BUS_DMASYNC_PREWRITE); 272 if (i == ATE_MAX_RX_BUFFERS - 1) 273 sc->rx_descs[i].addr = segs[0].ds_addr | ETH_WRAP_BIT; 274 else 275 sc->rx_descs[i].addr = segs[0].ds_addr; 276 bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, BUS_DMASYNC_POSTWRITE); 277 sc->rx_descs[i].status = 0; 278 /* Flush the memory in the mbuf */ 279 bus_dmamap_sync(sc->rxtag, sc->rx_map[i], BUS_DMASYNC_PREREAD); 280} 281 282/* 283 * Compute the multicast filter for this device using the standard 284 * algorithm. I wonder why this isn't in ether somewhere as a lot 285 * of different MAC chips use this method (or the reverse the bits) 286 * method. 287 */ 288static void 289ate_setmcast(struct ate_softc *sc) 290{ 291 uint32_t index; 292 uint32_t mcaf[2]; 293 u_char *af = (u_char *) mcaf; 294 struct ifmultiaddr *ifma; 295 296 mcaf[0] = 0; 297 mcaf[1] = 0; 298 299 IF_ADDR_LOCK(sc->ifp); 300 TAILQ_FOREACH(ifma, &sc->ifp->if_multiaddrs, ifma_link) { 301 if (ifma->ifma_addr->sa_family != AF_LINK) 302 continue; 303 index = ether_crc32_be(LLADDR((struct sockaddr_dl *) 304 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 305 af[index >> 3] |= 1 << (index & 7); 306 } 307 IF_ADDR_UNLOCK(sc->ifp); 308 309 /* 310 * Write the hash to the hash register. This card can also 311 * accept unicast packets as well as multicast packets using this 312 * register for easier bridging operations, but we don't take 313 * advantage of that. Locks here are to avoid LOR with the 314 * IF_ADDR_LOCK, but might not be strictly necessary. 315 */ 316 WR4(sc, ETH_HSL, mcaf[0]); 317 WR4(sc, ETH_HSH, mcaf[1]); 318} 319 320static int 321ate_activate(device_t dev) 322{ 323 struct ate_softc *sc; 324 int rid, err, i; 325 326 sc = device_get_softc(dev); 327 rid = 0; 328 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 329 RF_ACTIVE); 330 if (sc->mem_res == NULL) 331 goto errout; 332 rid = 0; 333 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 334 RF_ACTIVE); 335 if (sc->irq_res == NULL) 336 goto errout; 337 338 /* 339 * Allocate DMA tags and maps 340 */ 341 err = bus_dma_tag_create(NULL, 1, 0, BUS_SPACE_MAXADDR_32BIT, 342 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 1, MCLBYTES, 0, 343 busdma_lock_mutex, &sc->sc_mtx, &sc->mtag); 344 if (err != 0) 345 goto errout; 346 for (i = 0; i < ATE_MAX_TX_BUFFERS; i++) { 347 err = bus_dmamap_create(sc->mtag, 0, &sc->tx_map[i]); 348 if (err != 0) 349 goto errout; 350 } 351 /* 352 * Allocate our Rx buffers. This chip has a rx structure that's filled 353 * in 354 */ 355 356 /* 357 * Allocate DMA tags and maps for RX. 358 */ 359 err = bus_dma_tag_create(NULL, 1, 0, BUS_SPACE_MAXADDR_32BIT, 360 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 1, MCLBYTES, 0, 361 busdma_lock_mutex, &sc->sc_mtx, &sc->rxtag); 362 if (err != 0) 363 goto errout; 364 365 /* Dma TAG and MAP for the rx descriptors. */ 366 err = bus_dma_tag_create(NULL, sizeof(eth_rx_desc_t), 0, 367 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 368 ATE_MAX_RX_BUFFERS * sizeof(eth_rx_desc_t), 1, 369 ATE_MAX_RX_BUFFERS * sizeof(eth_rx_desc_t), 0, busdma_lock_mutex, 370 &sc->sc_mtx, &sc->rx_desc_tag); 371 if (err != 0) 372 goto errout; 373 if (bus_dmamem_alloc(sc->rx_desc_tag, (void **)&sc->rx_descs, 374 BUS_DMA_NOWAIT | BUS_DMA_COHERENT, &sc->rx_desc_map) != 0) 375 goto errout; 376 if (bus_dmamap_load(sc->rx_desc_tag, sc->rx_desc_map, 377 sc->rx_descs, ATE_MAX_RX_BUFFERS * sizeof(eth_rx_desc_t), 378 ate_getaddr, sc, 0) != 0) 379 goto errout; 380 /* XXX TODO(5) Put this in ateinit_locked? */ 381 for (i = 0; i < ATE_MAX_RX_BUFFERS; i++) { 382 sc->rx_buf_ptr = i; 383 if (bus_dmamem_alloc(sc->rxtag, (void **)&sc->rx_buf[i], 384 BUS_DMA_NOWAIT, &sc->rx_map[i]) != 0) 385 goto errout; 386 if (bus_dmamap_load(sc->rxtag, sc->rx_map[i], sc->rx_buf[i], 387 MCLBYTES, ate_load_rx_buf, sc, 0) != 0) 388 goto errout; 389 } 390 sc->rx_buf_ptr = 0; 391 /* Flush the memory for the EMAC rx descriptor */ 392 bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, BUS_DMASYNC_PREWRITE); 393 /* Write the descriptor queue address. */ 394 WR4(sc, ETH_RBQP, sc->rx_desc_phys); 395 return (0); 396errout: 397 ate_deactivate(dev); 398 return (ENOMEM); 399} 400 401static void 402ate_deactivate(device_t dev) 403{ 404 struct ate_softc *sc; 405 406 sc = device_get_softc(dev); 407 /* XXX TODO(2) teardown busdma junk, below from fxp -- customize */ 408#if 0 409 if (sc->fxp_mtag) { 410 for (i = 0; i < FXP_NRFABUFS; i++) { 411 rxp = &sc->fxp_desc.rx_list[i]; 412 if (rxp->rx_mbuf != NULL) { 413 bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map, 414 BUS_DMASYNC_POSTREAD); 415 bus_dmamap_unload(sc->fxp_mtag, rxp->rx_map); 416 m_freem(rxp->rx_mbuf); 417 } 418 bus_dmamap_destroy(sc->fxp_mtag, rxp->rx_map); 419 } 420 bus_dmamap_destroy(sc->fxp_mtag, sc->spare_map); 421 for (i = 0; i < FXP_NTXCB; i++) { 422 txp = &sc->fxp_desc.tx_list[i]; 423 if (txp->tx_mbuf != NULL) { 424 bus_dmamap_sync(sc->fxp_mtag, txp->tx_map, 425 BUS_DMASYNC_POSTWRITE); 426 bus_dmamap_unload(sc->fxp_mtag, txp->tx_map); 427 m_freem(txp->tx_mbuf); 428 } 429 bus_dmamap_destroy(sc->fxp_mtag, txp->tx_map); 430 } 431 bus_dma_tag_destroy(sc->fxp_mtag); 432 } 433 if (sc->fxp_stag) 434 bus_dma_tag_destroy(sc->fxp_stag); 435 if (sc->cbl_tag) 436 bus_dma_tag_destroy(sc->cbl_tag); 437 if (sc->mcs_tag) 438 bus_dma_tag_destroy(sc->mcs_tag); 439#endif 440 if (sc->intrhand) 441 bus_teardown_intr(dev, sc->irq_res, sc->intrhand); 442 sc->intrhand = 0; 443 bus_generic_detach(sc->dev); 444 if (sc->miibus) 445 device_delete_child(sc->dev, sc->miibus); 446 if (sc->mem_res) 447 bus_release_resource(dev, SYS_RES_IOPORT, 448 rman_get_rid(sc->mem_res), sc->mem_res); 449 sc->mem_res = 0; 450 if (sc->irq_res) 451 bus_release_resource(dev, SYS_RES_IRQ, 452 rman_get_rid(sc->irq_res), sc->irq_res); 453 sc->irq_res = 0; 454 return; 455} 456 457/* 458 * Change media according to request. 459 */ 460static int 461ate_ifmedia_upd(struct ifnet *ifp) 462{ 463 struct ate_softc *sc = ifp->if_softc; 464 struct mii_data *mii; 465 466 mii = device_get_softc(sc->miibus); 467 ATE_LOCK(sc); 468 mii_mediachg(mii); 469 ATE_UNLOCK(sc); 470 return (0); 471} 472 473/* 474 * Notify the world which media we're using. 475 */ 476static void 477ate_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 478{ 479 struct ate_softc *sc = ifp->if_softc; 480 struct mii_data *mii; 481 482 mii = device_get_softc(sc->miibus); 483 ATE_LOCK(sc); 484 mii_pollstat(mii); 485 ifmr->ifm_active = mii->mii_media_active; 486 ifmr->ifm_status = mii->mii_media_status; 487 ATE_UNLOCK(sc); 488} 489 490static void 491ate_stat_update(struct ate_softc *sc, int active) 492{ 493 /* 494 * The speed and full/half-duplex state needs to be reflected 495 * in the ETH_CFG register. 496 */ 497 if (IFM_SUBTYPE(active) == IFM_10_T) 498 WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) & ~ETH_CFG_SPD); 499 else 500 WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) | ETH_CFG_SPD); 501 if (active & IFM_FDX) 502 WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) | ETH_CFG_FD); 503 else 504 WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) & ~ETH_CFG_FD); 505} 506 507static void 508ate_tick(void *xsc) 509{ 510 struct ate_softc *sc = xsc; 511 struct ifnet *ifp = sc->ifp; 512 struct mii_data *mii; 513 int active; 514 uint32_t c; 515 516 /* 517 * The KB920x boot loader tests ETH_SR & ETH_SR_LINK and will ask 518 * the MII if there's a link if this bit is clear. Not sure if we 519 * should do the same thing here or not. 520 */ 521 ATE_ASSERT_LOCKED(sc); 522 if (sc->miibus != NULL) { 523 mii = device_get_softc(sc->miibus); 524 active = mii->mii_media_active; 525 mii_tick(mii); 526 if (mii->mii_media_status & IFM_ACTIVE && 527 active != mii->mii_media_active) 528 ate_stat_update(sc, mii->mii_media_active); 529 } 530 531 /* 532 * Update the stats as best we can. When we're done, clear 533 * the status counters and start over. We're supposed to read these 534 * registers often enough that they won't overflow. Hopefully 535 * once a second is often enough. Some don't map well to 536 * the dot3Stats mib, so for those we just count them as general 537 * errors. Stats for iframes, ibutes, oframes and obytes are 538 * collected elsewhere. These registers zero on a read to prevent 539 * races. For all the collision stats, also update the collision 540 * stats for the interface. 541 */ 542 sc->mibdata.dot3StatsAlignmentErrors += RD4(sc, ETH_ALE); 543 sc->mibdata.dot3StatsFCSErrors += RD4(sc, ETH_SEQE); 544 c = RD4(sc, ETH_SCOL); 545 ifp->if_collisions += c; 546 sc->mibdata.dot3StatsSingleCollisionFrames += c; 547 c = RD4(sc, ETH_MCOL); 548 sc->mibdata.dot3StatsMultipleCollisionFrames += c; 549 ifp->if_collisions += c; 550 sc->mibdata.dot3StatsSQETestErrors += RD4(sc, ETH_SQEE); 551 sc->mibdata.dot3StatsDeferredTransmissions += RD4(sc, ETH_DTE); 552 c = RD4(sc, ETH_LCOL); 553 sc->mibdata.dot3StatsLateCollisions += c; 554 ifp->if_collisions += c; 555 c = RD4(sc, ETH_ECOL); 556 sc->mibdata.dot3StatsExcessiveCollisions += c; 557 ifp->if_collisions += c; 558 sc->mibdata.dot3StatsCarrierSenseErrors += RD4(sc, ETH_CSE); 559 sc->mibdata.dot3StatsFrameTooLongs += RD4(sc, ETH_ELR); 560 sc->mibdata.dot3StatsInternalMacReceiveErrors += RD4(sc, ETH_DRFC); 561 /* 562 * not sure where to lump these, so count them against the errors 563 * for the interface. 564 */ 565 sc->ifp->if_oerrors += RD4(sc, ETH_TUE); 566 sc->ifp->if_ierrors += RD4(sc, ETH_CDE) + RD4(sc, ETH_RJB) + 567 RD4(sc, ETH_USF); 568 569 /* 570 * Schedule another timeout one second from now. 571 */ 572 callout_reset(&sc->tick_ch, hz, ate_tick, sc); 573} 574 575static void 576ate_set_mac(struct ate_softc *sc, u_char *eaddr) 577{ 578 WR4(sc, ETH_SA1L, (eaddr[3] << 24) | (eaddr[2] << 16) | 579 (eaddr[1] << 8) | eaddr[0]); 580 WR4(sc, ETH_SA1H, (eaddr[5] << 8) | (eaddr[4])); 581 582} 583 584static void 585ate_get_mac(struct ate_softc *sc, u_char *eaddr) 586{ 587 uint32_t low, high; 588 589 /* 590 * The boot loader setup the MAC with an address, if one is set in 591 * the loader. The TSC loader will also set the MAC address in a 592 * similar way. Grab the MAC address from the SA1[HL] registers. 593 */ 594 low = RD4(sc, ETH_SA1L); 595 high = RD4(sc, ETH_SA1H); 596 eaddr[0] = (high >> 8) & 0xff; 597 eaddr[1] = high & 0xff; 598 eaddr[2] = (low >> 24) & 0xff; 599 eaddr[3] = (low >> 16) & 0xff; 600 eaddr[4] = (low >> 8) & 0xff; 601 eaddr[5] = low & 0xff; 602} 603 604static void 605ate_intr(void *xsc) 606{ 607 struct ate_softc *sc = xsc; 608 struct ifnet *ifp = sc->ifp; 609 int status; 610 int i; 611 void *bp; 612 struct mbuf *mb; 613 uint32_t rx_stat; 614 615 status = RD4(sc, ETH_ISR); 616 if (status == 0) 617 return; 618 if (status & ETH_ISR_RCOM) { 619 bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, 620 BUS_DMASYNC_POSTREAD); 621 while (sc->rx_descs[sc->rx_buf_ptr].addr & ETH_CPU_OWNER) { 622 i = sc->rx_buf_ptr; 623 sc->rx_buf_ptr = (i + 1) % ATE_MAX_RX_BUFFERS; 624 bp = sc->rx_buf[i]; 625 rx_stat = sc->rx_descs[i].status; 626 if ((rx_stat & ETH_LEN_MASK) == 0) { 627 printf("ignoring bogus 0 len packet\n"); 628 bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, 629 BUS_DMASYNC_PREWRITE); 630 sc->rx_descs[i].addr &= ~ETH_CPU_OWNER; 631 bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, 632 BUS_DMASYNC_POSTWRITE); 633 continue; 634 } 635 /* Flush memory for mbuf so we don't get stale bytes */ 636 bus_dmamap_sync(sc->rxtag, sc->rx_map[i], 637 BUS_DMASYNC_POSTREAD); 638 WR4(sc, ETH_RSR, RD4(sc, ETH_RSR)); 639 640 /* 641 * The length returned by the device includes the 642 * ethernet CRC calculation for the packet, but 643 * ifnet drivers are supposed to discard it. 644 */ 645 mb = m_devget(sc->rx_buf[i], 646 (rx_stat & ETH_LEN_MASK) - ETHER_CRC_LEN, 647 ETHER_ALIGN, ifp, NULL); 648 bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, 649 BUS_DMASYNC_PREWRITE); 650 sc->rx_descs[i].addr &= ~ETH_CPU_OWNER; 651 bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, 652 BUS_DMASYNC_POSTWRITE); 653 bus_dmamap_sync(sc->rxtag, sc->rx_map[i], 654 BUS_DMASYNC_PREREAD); 655 if (mb != NULL) { 656 ifp->if_ipackets++; 657 (*ifp->if_input)(ifp, mb); 658 } 659 660 } 661 } 662 if (status & ETH_ISR_TCOM) { 663 ATE_LOCK(sc); 664 /* XXX TSR register should be cleared */ 665 if (sc->sent_mbuf[0]) { 666 bus_dmamap_sync(sc->rxtag, sc->tx_map[0], 667 BUS_DMASYNC_POSTWRITE); 668 m_freem(sc->sent_mbuf[0]); 669 ifp->if_opackets++; 670 sc->sent_mbuf[0] = NULL; 671 } 672 if (sc->sent_mbuf[1]) { 673 if (RD4(sc, ETH_TSR) & ETH_TSR_IDLE) { 674 bus_dmamap_sync(sc->rxtag, sc->tx_map[1], 675 BUS_DMASYNC_POSTWRITE); 676 m_freem(sc->sent_mbuf[1]); 677 ifp->if_opackets++; 678 sc->txcur = 0; 679 sc->sent_mbuf[0] = sc->sent_mbuf[1] = NULL; 680 } else { 681 sc->sent_mbuf[0] = sc->sent_mbuf[1]; 682 sc->sent_mbuf[1] = NULL; 683 sc->txcur = 1; 684 } 685 } else { 686 sc->sent_mbuf[0] = NULL; 687 sc->txcur = 0; 688 } 689 /* 690 * We're no longer busy, so clear the busy flag and call the 691 * start routine to xmit more packets. 692 */ 693 sc->ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 694 atestart_locked(sc->ifp); 695 ATE_UNLOCK(sc); 696 } 697 if (status & ETH_ISR_RBNA) { 698 printf("RBNA workaround\n"); 699 /* Workaround Errata #11 */ 700 WR4(sc, ETH_CTL, RD4(sc, ETH_CTL) &~ ETH_CTL_RE); 701 WR4(sc, ETH_CTL, RD4(sc, ETH_CTL) | ETH_CTL_RE); 702 } 703} 704 705/* 706 * Reset and initialize the chip 707 */ 708static void 709ateinit_locked(void *xsc) 710{ 711 struct ate_softc *sc = xsc; 712 struct ifnet *ifp = sc->ifp; 713 struct mii_data *mii; 714 715 ATE_ASSERT_LOCKED(sc); 716 717 /* 718 * XXX TODO(3) 719 * we need to turn on the EMAC clock in the pmc. With the 720 * default boot loader, this is already turned on. However, we 721 * need to think about how best to turn it on/off as the interface 722 * is brought up/down, as well as dealing with the mii bus... 723 * 724 * We also need to multiplex the pins correctly. 725 */ 726 727 /* 728 * There are two different ways that the mii bus is connected 729 * to this chip. Select the right one based on a compile-time 730 * option. 731 */ 732 if (sc->use_rmii) 733 WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) | ETH_CFG_RMII); 734 else 735 WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) & ~ETH_CFG_RMII); 736 737 /* 738 * Turn on the multicast hash, and write 0's to it. 739 */ 740 WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) | ETH_CFG_MTI); 741 WR4(sc, ETH_HSH, 0); 742 WR4(sc, ETH_HSL, 0); 743 744 WR4(sc, ETH_CTL, RD4(sc, ETH_CTL) | ETH_CTL_TE | ETH_CTL_RE); 745 WR4(sc, ETH_IER, ETH_ISR_RCOM | ETH_ISR_TCOM | ETH_ISR_RBNA); 746 747 /* 748 * Boot loader fills in MAC address. If that's not the case, then 749 * we should set SA1L and SA1H here to the appropriate value. Note: 750 * the byte order is big endian, not little endian, so we have some 751 * swapping to do. Again, if we need it (which I don't think we do). 752 */ 753 ate_setmcast(sc); 754 755 /* 756 * Set 'running' flag, and clear output active flag 757 * and attempt to start the output 758 */ 759 ifp->if_drv_flags |= IFF_DRV_RUNNING; 760 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 761 762 mii = device_get_softc(sc->miibus); 763 mii_pollstat(mii); 764 ate_stat_update(sc, mii->mii_media_active); 765 atestart_locked(ifp); 766 767 callout_reset(&sc->tick_ch, hz, ate_tick, sc); 768} 769 770/* 771 * dequeu packets and transmit 772 */ 773static void 774atestart_locked(struct ifnet *ifp) 775{ 776 struct ate_softc *sc = ifp->if_softc; 777 struct mbuf *m, *mdefrag; 778 bus_dma_segment_t segs[1]; 779 int nseg, e; 780 781 ATE_ASSERT_LOCKED(sc); 782 if (ifp->if_drv_flags & IFF_DRV_OACTIVE) 783 return; 784 785 while (sc->txcur < ATE_MAX_TX_BUFFERS) { 786 /* 787 * check to see if there's room to put another packet into the 788 * xmit queue. The EMAC chip has a ping-pong buffer for xmit 789 * packets. We use OACTIVE to indicate "we can stuff more into 790 * our buffers (clear) or not (set)." 791 */ 792 if (!(RD4(sc, ETH_TSR) & ETH_TSR_BNQ)) { 793 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 794 return; 795 } 796 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 797 if (m == 0) { 798 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 799 return; 800 } 801 e = bus_dmamap_load_mbuf_sg(sc->mtag, sc->tx_map[sc->txcur], m, 802 segs, &nseg, 0); 803 if (e == EFBIG) { 804 mdefrag = m_defrag(m, M_DONTWAIT); 805 if (mdefrag == NULL) { 806 IFQ_DRV_PREPEND(&ifp->if_snd, m); 807 return; 808 } 809 m = mdefrag; 810 e = bus_dmamap_load_mbuf_sg(sc->mtag, 811 sc->tx_map[sc->txcur], m, segs, &nseg, 0); 812 } 813 if (e != 0) { 814 m_freem(m); 815 continue; 816 } 817 bus_dmamap_sync(sc->mtag, sc->tx_map[sc->txcur], 818 BUS_DMASYNC_PREWRITE); 819 820 /* 821 * tell the hardware to xmit the packet. 822 */ 823 WR4(sc, ETH_TAR, segs[0].ds_addr); 824 WR4(sc, ETH_TCR, segs[0].ds_len); 825 826 /* 827 * Tap off here if there is a bpf listener. 828 */ 829 BPF_MTAP(ifp, m); 830 831 sc->sent_mbuf[sc->txcur] = m; 832 sc->txcur++; 833 } 834} 835 836static void 837ateinit(void *xsc) 838{ 839 struct ate_softc *sc = xsc; 840 ATE_LOCK(sc); 841 ateinit_locked(sc); 842 ATE_UNLOCK(sc); 843} 844 845static void 846atestart(struct ifnet *ifp) 847{ 848 struct ate_softc *sc = ifp->if_softc; 849 ATE_LOCK(sc); 850 atestart_locked(ifp); 851 ATE_UNLOCK(sc); 852} 853 854/* 855 * Turn off interrupts, and stop the nic. Can be called with sc->ifp NULL 856 * so be careful. 857 */ 858static void 859atestop(struct ate_softc *sc) 860{ 861 struct ifnet *ifp = sc->ifp; 862 863 if (ifp) { 864 ifp->if_timer = 0; 865 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 866 } 867 868 callout_stop(&sc->tick_ch); 869 870 /* 871 * Enable some parts of the MAC that are needed always (like the 872 * MII bus. This turns off the RE and TE bits, which will remain 873 * off until ateinit() is called to turn them on. With RE and TE 874 * turned off, there's no DMA to worry about after this write. 875 */ 876 WR4(sc, ETH_CTL, ETH_CTL_MPE); 877 878 /* 879 * Turn off all the configured options and revert to defaults. 880 */ 881 WR4(sc, ETH_CFG, ETH_CFG_CLK_32); 882 883 /* 884 * Turn off all the interrupts, and ack any pending ones by reading 885 * the ISR. 886 */ 887 WR4(sc, ETH_IDR, 0xffffffff); 888 RD4(sc, ETH_ISR); 889 890 /* 891 * Clear out the Transmit and Receiver Status registers of any 892 * errors they may be reporting 893 */ 894 WR4(sc, ETH_TSR, 0xffffffff); 895 WR4(sc, ETH_RSR, 0xffffffff); 896 897 /* 898 * XXX TODO(8) 899 * need to worry about the busdma resources? Yes, I think we need 900 * to sync and unload them. We may also need to release the mbufs 901 * that are assocaited with RX and TX operations. 902 */ 903 904 /* 905 * XXX we should power down the EMAC if it isn't in use, after 906 * putting it into loopback mode. This saves about 400uA according 907 * to the datasheet. 908 */ 909} 910 911static int 912ateioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 913{ 914 struct ate_softc *sc = ifp->if_softc; 915 struct mii_data *mii; 916 struct ifreq *ifr = (struct ifreq *)data; 917 int error = 0; 918 919 switch (cmd) { 920 case SIOCSIFFLAGS: 921 ATE_LOCK(sc); 922 if ((ifp->if_flags & IFF_UP) == 0 && 923 ifp->if_drv_flags & IFF_DRV_RUNNING) { 924 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 925 atestop(sc); 926 } else { 927 /* reinitialize card on any parameter change */ 928 ateinit_locked(sc); 929 } 930 ATE_UNLOCK(sc); 931 break; 932 933 case SIOCADDMULTI: 934 case SIOCDELMULTI: 935 /* update multicast filter list. */ 936 ATE_LOCK(sc); 937 ate_setmcast(sc); 938 ATE_UNLOCK(sc); 939 error = 0; 940 break; 941 942 case SIOCSIFMEDIA: 943 case SIOCGIFMEDIA: 944 mii = device_get_softc(sc->miibus); 945 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 946 break; 947 default: 948 error = ether_ioctl(ifp, cmd, data); 949 break; 950 } 951 return (error); 952} 953 954static void 955ate_child_detached(device_t dev, device_t child) 956{ 957 struct ate_softc *sc; 958 959 sc = device_get_softc(dev); 960 if (child == sc->miibus) 961 sc->miibus = NULL; 962} 963 964/* 965 * MII bus support routines. 966 */ 967static int 968ate_miibus_readreg(device_t dev, int phy, int reg) 969{ 970 struct ate_softc *sc; 971 int val; 972 973 /* 974 * XXX if we implement agressive power savings, then we need 975 * XXX to make sure that the clock to the emac is on here 976 */ 977 978 if (phy != 0) 979 return (0xffff); 980 sc = device_get_softc(dev); 981 DELAY(1); /* Hangs w/o this delay really 30.5us atm */ 982 WR4(sc, ETH_MAN, ETH_MAN_REG_RD(phy, reg)); 983 while ((RD4(sc, ETH_SR) & ETH_SR_IDLE) == 0) 984 continue; 985 val = RD4(sc, ETH_MAN) & ETH_MAN_VALUE_MASK; 986 987 return (val); 988} 989 990static void 991ate_miibus_writereg(device_t dev, int phy, int reg, int data) 992{ 993 struct ate_softc *sc; 994 995 /* 996 * XXX if we implement agressive power savings, then we need 997 * XXX to make sure that the clock to the emac is on here 998 */ 999 1000 sc = device_get_softc(dev); 1001 WR4(sc, ETH_MAN, ETH_MAN_REG_WR(phy, reg, data)); 1002 while ((RD4(sc, ETH_SR) & ETH_SR_IDLE) == 0) 1003 continue; 1004 return; 1005} 1006 1007static device_method_t ate_methods[] = { 1008 /* Device interface */ 1009 DEVMETHOD(device_probe, ate_probe), 1010 DEVMETHOD(device_attach, ate_attach), 1011 DEVMETHOD(device_detach, ate_detach), 1012 1013 /* Bus interface */ 1014 DEVMETHOD(bus_child_detached, ate_child_detached), 1015 1016 /* MII interface */ 1017 DEVMETHOD(miibus_readreg, ate_miibus_readreg), 1018 DEVMETHOD(miibus_writereg, ate_miibus_writereg), 1019 1020 { 0, 0 } 1021}; 1022 1023static driver_t ate_driver = { 1024 "ate", 1025 ate_methods, 1026 sizeof(struct ate_softc), 1027}; 1028 1029DRIVER_MODULE(ate, atmelarm, ate_driver, ate_devclass, 0, 0); 1030DRIVER_MODULE(miibus, ate, miibus_driver, miibus_devclass, 0, 0); 1031MODULE_DEPEND(ate, miibus, 1, 1, 1); 1032MODULE_DEPEND(ate, ether, 1, 1, 1); 1033