if_ate.c revision 161617
1/*- 2 * Copyright (c) 2006 M. Warner Losh. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 14 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 15 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 16 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 19 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 20 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 23 */ 24 25/* TODO: (in no order) 26 * 27 * 8) Need to sync busdma goo in atestop 28 * 9) atestop should maybe free the mbufs? 29 * 30 * 1) detach 31 * 2) Free dma setup 32 * 3) Turn on the clock in pmc and turn on pins? Turn off? 33 */ 34 35#include <sys/cdefs.h> 36__FBSDID("$FreeBSD: head/sys/arm/at91/if_ate.c 161617 2006-08-25 13:38:42Z cognet $"); 37 38#include <sys/param.h> 39#include <sys/systm.h> 40#include <sys/bus.h> 41#include <sys/kernel.h> 42#include <sys/mbuf.h> 43#include <sys/malloc.h> 44#include <sys/module.h> 45#include <sys/rman.h> 46#include <sys/socket.h> 47#include <sys/sockio.h> 48#include <machine/bus.h> 49 50#include <net/ethernet.h> 51#include <net/if.h> 52#include <net/if_arp.h> 53#include <net/if_dl.h> 54#include <net/if_media.h> 55#include <net/if_mib.h> 56#include <net/if_types.h> 57 58#ifdef INET 59#include <netinet/in.h> 60#include <netinet/in_systm.h> 61#include <netinet/in_var.h> 62#include <netinet/ip.h> 63#endif 64 65#include <net/bpf.h> 66#include <net/bpfdesc.h> 67 68#include <dev/mii/mii.h> 69#include <dev/mii/miivar.h> 70#include <arm/at91/if_atereg.h> 71 72#include "miibus_if.h" 73 74#define ATE_MAX_TX_BUFFERS 64 /* We have ping-pong tx buffers */ 75#define ATE_MAX_RX_BUFFERS 64 76 77struct ate_softc 78{ 79 struct ifnet *ifp; /* ifnet pointer */ 80 struct mtx sc_mtx; /* basically a perimeter lock */ 81 device_t dev; /* Myself */ 82 device_t miibus; /* My child miibus */ 83 void *intrhand; /* Interrupt handle */ 84 struct resource *irq_res; /* IRQ resource */ 85 struct resource *mem_res; /* Memory resource */ 86 struct callout tick_ch; /* Tick callout */ 87 bus_dma_tag_t mtag; /* bus dma tag for mbufs */ 88 bus_dmamap_t tx_map[ATE_MAX_TX_BUFFERS]; 89 struct mbuf *sent_mbuf[ATE_MAX_TX_BUFFERS]; /* Sent mbufs */ 90 bus_dma_tag_t rxtag; 91 bus_dmamap_t rx_map[ATE_MAX_RX_BUFFERS]; 92 void *rx_buf[ATE_MAX_RX_BUFFERS]; /* RX buffer space */ 93 int rx_buf_ptr; 94 bus_dma_tag_t rx_desc_tag; 95 bus_dmamap_t rx_desc_map; 96 int txcur; /* current tx map pointer */ 97 bus_addr_t rx_desc_phys; 98 eth_rx_desc_t *rx_descs; 99 int use_rmii; 100 struct ifmib_iso_8802_3 mibdata; /* stuff for network mgmt */ 101}; 102 103static inline uint32_t 104RD4(struct ate_softc *sc, bus_size_t off) 105{ 106 return bus_read_4(sc->mem_res, off); 107} 108 109static inline void 110WR4(struct ate_softc *sc, bus_size_t off, uint32_t val) 111{ 112 bus_write_4(sc->mem_res, off, val); 113} 114 115#define ATE_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 116#define ATE_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 117#define ATE_LOCK_INIT(_sc) \ 118 mtx_init(&_sc->sc_mtx, device_get_nameunit(_sc->dev), \ 119 MTX_NETWORK_LOCK, MTX_DEF) 120#define ATE_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx); 121#define ATE_ASSERT_LOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_OWNED); 122#define ATE_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_NOTOWNED); 123 124static devclass_t ate_devclass; 125 126/* ifnet entry points */ 127 128static void ateinit_locked(void *); 129static void atestart_locked(struct ifnet *); 130 131static void ateinit(void *); 132static void atestart(struct ifnet *); 133static void atestop(struct ate_softc *); 134static void atewatchdog(struct ifnet *); 135static int ateioctl(struct ifnet * ifp, u_long, caddr_t); 136 137/* bus entry points */ 138 139static int ate_probe(device_t dev); 140static int ate_attach(device_t dev); 141static int ate_detach(device_t dev); 142static void ate_intr(void *); 143 144/* helper routines */ 145static int ate_activate(device_t dev); 146static void ate_deactivate(device_t dev); 147static int ate_ifmedia_upd(struct ifnet *ifp); 148static void ate_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr); 149static void ate_get_mac(struct ate_softc *sc, u_char *eaddr); 150static void ate_set_mac(struct ate_softc *sc, u_char *eaddr); 151 152/* 153 * The AT91 family of products has the ethernet called EMAC. However, 154 * it isn't self identifying. It is anticipated that the parent bus 155 * code will take care to only add ate devices where they really are. As 156 * such, we do nothing here to identify the device and just set its name. 157 */ 158static int 159ate_probe(device_t dev) 160{ 161 device_set_desc(dev, "EMAC"); 162 return (0); 163} 164 165static int 166ate_attach(device_t dev) 167{ 168 struct ate_softc *sc = device_get_softc(dev); 169 struct ifnet *ifp = NULL; 170 int err; 171 u_char eaddr[6]; 172 173 sc->dev = dev; 174 err = ate_activate(dev); 175 if (err) 176 goto out; 177 178 sc->use_rmii = (RD4(sc, ETH_CFG) & ETH_CFG_RMII) == ETH_CFG_RMII; 179 180 /* calling atestop before ifp is set is OK */ 181 atestop(sc); 182 ATE_LOCK_INIT(sc); 183 callout_init_mtx(&sc->tick_ch, &sc->sc_mtx, 0); 184 185 ate_get_mac(sc, eaddr); 186 ate_set_mac(sc, eaddr); 187 188 189 sc->ifp = ifp = if_alloc(IFT_ETHER); 190 if (mii_phy_probe(dev, &sc->miibus, ate_ifmedia_upd, ate_ifmedia_sts)) { 191 device_printf(dev, "Cannot find my PHY.\n"); 192 err = ENXIO; 193 goto out; 194 } 195 196 ifp->if_softc = sc; 197 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 198 ifp->if_mtu = ETHERMTU; 199 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 200 ifp->if_start = atestart; 201 ifp->if_ioctl = ateioctl; 202 ifp->if_watchdog = atewatchdog; 203 ifp->if_init = ateinit; 204 ifp->if_baudrate = 10000000; 205 IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN); 206 ifp->if_snd.ifq_maxlen = IFQ_MAXLEN; 207 IFQ_SET_READY(&ifp->if_snd); 208 ifp->if_timer = 0; 209 ifp->if_linkmib = &sc->mibdata; 210 ifp->if_linkmiblen = sizeof(sc->mibdata); 211 sc->mibdata.dot3Compliance = DOT3COMPLIANCE_COLLS; 212 213 ether_ifattach(ifp, eaddr); 214 215 /* 216 * Activate the interrupt 217 */ 218 err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_NET | INTR_MPSAFE, 219 ate_intr, sc, &sc->intrhand); 220 if (err) { 221 ether_ifdetach(ifp); 222 ATE_LOCK_DESTROY(sc); 223 } 224out:; 225 if (err) 226 ate_deactivate(dev); 227 if (err && ifp) 228 if_free(ifp); 229 return (err); 230} 231 232static int 233ate_detach(device_t dev) 234{ 235 return EBUSY; /* XXX TODO(1) */ 236} 237 238static void 239ate_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 240{ 241 struct ate_softc *sc; 242 243 if (error != 0) 244 return; 245 sc = (struct ate_softc *)arg; 246 sc->rx_desc_phys = segs[0].ds_addr; 247} 248 249static void 250ate_load_rx_buf(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 251{ 252 struct ate_softc *sc; 253 int i; 254 255 if (error != 0) 256 return; 257 sc = (struct ate_softc *)arg; 258 i = sc->rx_buf_ptr; 259 260 /* 261 * For the last buffer, set the wrap bit so the controller 262 * restarts from the first descriptor. 263 */ 264 if (i == ATE_MAX_RX_BUFFERS - 1) 265 sc->rx_descs[i].addr = segs[0].ds_addr | ETH_WRAP_BIT; 266 else 267 sc->rx_descs[i].addr = segs[0].ds_addr; 268 sc->rx_descs[i].status = 0; 269 /* Flush the memory in the mbuf */ 270 bus_dmamap_sync(sc->rxtag, sc->rx_map[i], BUS_DMASYNC_PREREAD); 271} 272 273/* 274 * Compute the multicast filter for this device using the standard 275 * algorithm. I wonder why this isn't in ether somewhere as a lot 276 * of different MAC chips use this method (or the reverse the bits) 277 * method. 278 */ 279static void 280ate_setmcast(struct ate_softc *sc) 281{ 282 uint32_t index; 283 uint32_t mcaf[2]; 284 u_char *af = (u_char *) mcaf; 285 struct ifmultiaddr *ifma; 286 287 mcaf[0] = 0; 288 mcaf[1] = 0; 289 290 IF_ADDR_LOCK(sc->ifp); 291 TAILQ_FOREACH(ifma, &sc->ifp->if_multiaddrs, ifma_link) { 292 if (ifma->ifma_addr->sa_family != AF_LINK) 293 continue; 294 index = ether_crc32_be(LLADDR((struct sockaddr_dl *) 295 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 296 af[index >> 3] |= 1 << (index & 7); 297 } 298 IF_ADDR_UNLOCK(sc->ifp); 299 300 /* 301 * Write the hash to the hash register. This card can also 302 * accept unicast packets as well as multicast packets using this 303 * register for easier bridging operations, but we don't take 304 * advantage of that. Locks here are to avoid LOR with the 305 * IF_ADDR_LOCK, but might not be strictly necessary. 306 */ 307 WR4(sc, ETH_HSL, mcaf[0]); 308 WR4(sc, ETH_HSH, mcaf[1]); 309} 310 311static int 312ate_activate(device_t dev) 313{ 314 struct ate_softc *sc; 315 int rid, err, i; 316 317 sc = device_get_softc(dev); 318 rid = 0; 319 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 320 RF_ACTIVE); 321 if (sc->mem_res == NULL) 322 goto errout; 323 rid = 0; 324 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 325 RF_ACTIVE); 326 if (sc->mem_res == NULL) 327 goto errout; 328 329 /* 330 * Allocate DMA tags and maps 331 */ 332 err = bus_dma_tag_create(NULL, 1, 0, BUS_SPACE_MAXADDR_32BIT, 333 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 1, MCLBYTES, 0, 334 busdma_lock_mutex, &sc->sc_mtx, &sc->mtag); 335 if (err != 0) 336 goto errout; 337 for (i = 0; i < ATE_MAX_TX_BUFFERS; i++) { 338 err = bus_dmamap_create(sc->mtag, 0, &sc->tx_map[i]); 339 if (err != 0) 340 goto errout; 341 } 342 /* 343 * Allocate our Rx buffers. This chip has a rx structure that's filled 344 * in 345 */ 346 347 /* 348 * Allocate DMA tags and maps for RX. 349 */ 350 err = bus_dma_tag_create(NULL, 1, 0, BUS_SPACE_MAXADDR_32BIT, 351 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 1, MCLBYTES, 0, 352 busdma_lock_mutex, &sc->sc_mtx, &sc->rxtag); 353 if (err != 0) 354 goto errout; 355 356 /* Dma TAG and MAP for the rx descriptors. */ 357 err = bus_dma_tag_create(NULL, sizeof(eth_rx_desc_t), 0, 358 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 359 ATE_MAX_RX_BUFFERS * sizeof(eth_rx_desc_t), 1, 360 ATE_MAX_RX_BUFFERS * sizeof(eth_rx_desc_t), 0, busdma_lock_mutex, 361 &sc->sc_mtx, &sc->rx_desc_tag); 362 if (err != 0) 363 goto errout; 364 if (bus_dmamem_alloc(sc->rx_desc_tag, (void **)&sc->rx_descs, 365 BUS_DMA_NOWAIT | BUS_DMA_COHERENT, &sc->rx_desc_map) != 0) 366 goto errout; 367 if (bus_dmamap_load(sc->rx_desc_tag, sc->rx_desc_map, 368 sc->rx_descs, ATE_MAX_RX_BUFFERS * sizeof(eth_rx_desc_t), 369 ate_getaddr, sc, 0) != 0) 370 goto errout; 371 /* XXX TODO(5) Put this in ateinit_locked? */ 372 for (i = 0; i < ATE_MAX_RX_BUFFERS; i++) { 373 sc->rx_buf_ptr = i; 374 if (bus_dmamem_alloc(sc->rxtag, (void **)&sc->rx_buf[i], 375 BUS_DMA_NOWAIT, &sc->rx_map[i]) != 0) 376 goto errout; 377 if (bus_dmamap_load(sc->rxtag, sc->rx_map[i], sc->rx_buf[i], 378 MCLBYTES, ate_load_rx_buf, sc, 0) != 0) 379 goto errout; 380 } 381 sc->rx_buf_ptr = 0; 382 /* Flush the memory for the EMAC rx descriptor */ 383 bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, BUS_DMASYNC_PREWRITE); 384 /* Write the descriptor queue address. */ 385 WR4(sc, ETH_RBQP, sc->rx_desc_phys); 386 return (0); 387errout: 388 ate_deactivate(dev); 389 return (ENOMEM); 390} 391 392static void 393ate_deactivate(device_t dev) 394{ 395 struct ate_softc *sc; 396 397 sc = device_get_softc(dev); 398 /* XXX TODO(2) teardown busdma junk, below from fxp -- customize */ 399#if 0 400 if (sc->fxp_mtag) { 401 for (i = 0; i < FXP_NRFABUFS; i++) { 402 rxp = &sc->fxp_desc.rx_list[i]; 403 if (rxp->rx_mbuf != NULL) { 404 bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map, 405 BUS_DMASYNC_POSTREAD); 406 bus_dmamap_unload(sc->fxp_mtag, rxp->rx_map); 407 m_freem(rxp->rx_mbuf); 408 } 409 bus_dmamap_destroy(sc->fxp_mtag, rxp->rx_map); 410 } 411 bus_dmamap_destroy(sc->fxp_mtag, sc->spare_map); 412 for (i = 0; i < FXP_NTXCB; i++) { 413 txp = &sc->fxp_desc.tx_list[i]; 414 if (txp->tx_mbuf != NULL) { 415 bus_dmamap_sync(sc->fxp_mtag, txp->tx_map, 416 BUS_DMASYNC_POSTWRITE); 417 bus_dmamap_unload(sc->fxp_mtag, txp->tx_map); 418 m_freem(txp->tx_mbuf); 419 } 420 bus_dmamap_destroy(sc->fxp_mtag, txp->tx_map); 421 } 422 bus_dma_tag_destroy(sc->fxp_mtag); 423 } 424 if (sc->fxp_stag) 425 bus_dma_tag_destroy(sc->fxp_stag); 426 if (sc->cbl_tag) 427 bus_dma_tag_destroy(sc->cbl_tag); 428 if (sc->mcs_tag) 429 bus_dma_tag_destroy(sc->mcs_tag); 430#endif 431 if (sc->intrhand) 432 bus_teardown_intr(dev, sc->irq_res, sc->intrhand); 433 sc->intrhand = 0; 434 bus_generic_detach(sc->dev); 435 if (sc->miibus) 436 device_delete_child(sc->dev, sc->miibus); 437 if (sc->mem_res) 438 bus_release_resource(dev, SYS_RES_IOPORT, 439 rman_get_rid(sc->mem_res), sc->mem_res); 440 sc->mem_res = 0; 441 if (sc->irq_res) 442 bus_release_resource(dev, SYS_RES_IRQ, 443 rman_get_rid(sc->irq_res), sc->irq_res); 444 sc->irq_res = 0; 445 return; 446} 447 448/* 449 * Change media according to request. 450 */ 451static int 452ate_ifmedia_upd(struct ifnet *ifp) 453{ 454 struct ate_softc *sc = ifp->if_softc; 455 struct mii_data *mii; 456 457 mii = device_get_softc(sc->miibus); 458 ATE_LOCK(sc); 459 mii_mediachg(mii); 460 ATE_UNLOCK(sc); 461 return (0); 462} 463 464/* 465 * Notify the world which media we're using. 466 */ 467static void 468ate_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 469{ 470 struct ate_softc *sc = ifp->if_softc; 471 struct mii_data *mii; 472 473 mii = device_get_softc(sc->miibus); 474 ATE_LOCK(sc); 475 mii_pollstat(mii); 476 ifmr->ifm_active = mii->mii_media_active; 477 ifmr->ifm_status = mii->mii_media_status; 478 ATE_UNLOCK(sc); 479} 480 481static void 482ate_tick(void *xsc) 483{ 484 struct ate_softc *sc = xsc; 485 struct mii_data *mii; 486 int active; 487 488 /* 489 * The KB920x boot loader tests ETH_SR & ETH_SR_LINK and will ask 490 * the MII if there's a link if this bit is clear. Not sure if we 491 * should do the same thing here or not. 492 */ 493 ATE_ASSERT_LOCKED(sc); 494 if (sc->miibus != NULL) { 495 mii = device_get_softc(sc->miibus); 496 active = mii->mii_media_active; 497 mii_tick(mii); 498 if (mii->mii_media_status & IFM_ACTIVE && 499 active != mii->mii_media_active) { 500 /* 501 * The speed and full/half-duplex state needs 502 * to be reflected in the ETH_CFG register, it 503 * seems. 504 */ 505 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T) 506 WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) & 507 ~ETH_CFG_SPD); 508 else 509 WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) | 510 ETH_CFG_SPD); 511 if (mii->mii_media_active & IFM_FDX) 512 WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) | 513 ETH_CFG_FD); 514 else 515 WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) & 516 ~ETH_CFG_FD); 517 } 518 } 519 520 /* 521 * Update the stats as best we can. When we're done, clear 522 * the status counters and start over. We're supposed to read these 523 * registers often enough that they won't overflow. Hopefully 524 * once a second is often enough. Some don't map well to 525 * the dot3Stats mib, so for those we just count them as general 526 * errors. Stats for iframes, ibutes, oframes and obytes are 527 * collected elsewhere. These registers zero on a read to prevent 528 * races. 529 */ 530 sc->mibdata.dot3StatsAlignmentErrors += RD4(sc, ETH_ALE); 531 sc->mibdata.dot3StatsFCSErrors += RD4(sc, ETH_SEQE); 532 sc->mibdata.dot3StatsSingleCollisionFrames += RD4(sc, ETH_SCOL); 533 sc->mibdata.dot3StatsMultipleCollisionFrames += RD4(sc, ETH_MCOL); 534 sc->mibdata.dot3StatsSQETestErrors += RD4(sc, ETH_SQEE); 535 sc->mibdata.dot3StatsDeferredTransmissions += RD4(sc, ETH_DTE); 536 sc->mibdata.dot3StatsLateCollisions += RD4(sc, ETH_LCOL); 537 sc->mibdata.dot3StatsExcessiveCollisions += RD4(sc, ETH_ECOL); 538 sc->mibdata.dot3StatsCarrierSenseErrors += RD4(sc, ETH_CSE); 539 sc->mibdata.dot3StatsFrameTooLongs += RD4(sc, ETH_ELR); 540 sc->mibdata.dot3StatsInternalMacReceiveErrors += RD4(sc, ETH_DRFC); 541 /* 542 * not sure where to lump these, so count them against the errors 543 * for the interface. 544 */ 545 sc->ifp->if_oerrors += RD4(sc, ETH_CSE) + RD4(sc, ETH_TUE); 546 sc->ifp->if_ierrors += RD4(sc, ETH_CDE) + RD4(sc, ETH_RJB) + 547 RD4(sc, ETH_USF); 548 549 /* 550 * Schedule another timeout one second from now. 551 */ 552 callout_reset(&sc->tick_ch, hz, ate_tick, sc); 553} 554 555static void 556ate_set_mac(struct ate_softc *sc, u_char *eaddr) 557{ 558 WR4(sc, ETH_SA1L, (eaddr[3] << 24) | (eaddr[2] << 16) | 559 (eaddr[1] << 8) | eaddr[0]); 560 WR4(sc, ETH_SA1H, (eaddr[5] << 8) | (eaddr[4])); 561 562} 563 564static void 565ate_get_mac(struct ate_softc *sc, u_char *eaddr) 566{ 567 uint32_t low, high; 568 569 /* 570 * The KB920x loaders will setup the MAC with an address, if one 571 * is set in the loader. The TSC loader will also set the MAC address 572 * in a similar way. Grab the MAC address from the SA1[HL] registers. 573 */ 574 low = RD4(sc, ETH_SA1L); 575 high = RD4(sc, ETH_SA1H); 576 eaddr[0] = (high >> 8) & 0xff; 577 eaddr[1] = high & 0xff; 578 eaddr[2] = (low >> 24) & 0xff; 579 eaddr[3] = (low >> 16) & 0xff; 580 eaddr[4] = (low >> 8) & 0xff; 581 eaddr[5] = low & 0xff; 582} 583 584static void 585ate_intr(void *xsc) 586{ 587 struct ate_softc *sc = xsc; 588 int status; 589 int i; 590 void *bp; 591 struct mbuf *mb; 592 uint32_t rx_stat; 593 594 status = RD4(sc, ETH_ISR); 595 if (status == 0) 596 return; 597 if (status & ETH_ISR_RCOM) { 598 bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, 599 BUS_DMASYNC_POSTREAD); 600 while (sc->rx_descs[sc->rx_buf_ptr].addr & ETH_CPU_OWNER) { 601 i = sc->rx_buf_ptr; 602 sc->rx_buf_ptr = (i + 1) % ATE_MAX_RX_BUFFERS; 603 bp = sc->rx_buf[i]; 604 rx_stat = sc->rx_descs[i].status; 605 if ((rx_stat & ETH_LEN_MASK) == 0) { 606 printf("ignoring bogus 0 len packet\n"); 607 sc->rx_descs[i].addr &= ~ETH_CPU_OWNER; 608 bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, 609 BUS_DMASYNC_PREWRITE); 610 continue; 611 } 612 /* Flush memory for mbuf so we don't get stale bytes */ 613 bus_dmamap_sync(sc->rxtag, sc->rx_map[i], 614 BUS_DMASYNC_POSTREAD); 615 WR4(sc, ETH_RSR, RD4(sc, ETH_RSR)); // XXX WHY? XXX imp 616 /* 617 * The length returned by the device includes the 618 * ethernet CRC calculation for the packet, but 619 * ifnet drivers are supposed to discard it. 620 */ 621 mb = m_devget(sc->rx_buf[i], 622 (rx_stat & ETH_LEN_MASK) - ETHER_CRC_LEN, 623 ETHER_ALIGN, sc->ifp, NULL); 624 sc->rx_descs[i].addr &= ~ETH_CPU_OWNER; 625 bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, 626 BUS_DMASYNC_PREWRITE); 627 bus_dmamap_sync(sc->rxtag, sc->rx_map[i], 628 BUS_DMASYNC_PREREAD); 629 if (mb != NULL) 630 (*sc->ifp->if_input)(sc->ifp, mb); 631 } 632 } 633 if (status & ETH_ISR_TCOM) { 634 ATE_LOCK(sc); 635 if (sc->sent_mbuf[0]) { 636 m_freem(sc->sent_mbuf[0]); 637 sc->sent_mbuf[0] = NULL; 638 } 639 if (sc->sent_mbuf[1]) { 640 if (RD4(sc, ETH_TSR) & ETH_TSR_IDLE) { 641 m_freem(sc->sent_mbuf[1]); 642 sc->txcur = 0; 643 sc->sent_mbuf[0] = sc->sent_mbuf[1] = NULL; 644 } else { 645 sc->sent_mbuf[0] = sc->sent_mbuf[1]; 646 sc->sent_mbuf[1] = NULL; 647 sc->txcur = 1; 648 } 649 } else { 650 sc->sent_mbuf[0] = NULL; 651 sc->txcur = 0; 652 } 653 /* 654 * We're no longer busy, so clear the busy flag and call the 655 * start routine to xmit more packets. 656 */ 657 sc->ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 658 atestart_locked(sc->ifp); 659 ATE_UNLOCK(sc); 660 } 661 if (status & ETH_ISR_RBNA) { 662 printf("RBNA workaround\n"); 663 /* Workaround Errata #11 */ 664 WR4(sc, ETH_CTL, RD4(sc, ETH_CTL) &~ ETH_CTL_RE); 665 WR4(sc, ETH_CTL, RD4(sc, ETH_CTL) | ETH_CTL_RE); 666 } 667} 668 669/* 670 * Reset and initialize the chip 671 */ 672static void 673ateinit_locked(void *xsc) 674{ 675 struct ate_softc *sc = xsc; 676 struct ifnet *ifp = sc->ifp; 677 678 ATE_ASSERT_LOCKED(sc); 679 680 /* 681 * XXX TODO(3) 682 * we need to turn on the EMAC clock in the pmc. With the 683 * default boot loader, this is already turned on. However, we 684 * need to think about how best to turn it on/off as the interface 685 * is brought up/down, as well as dealing with the mii bus... 686 * 687 * We also need to multiplex the pins correctly. 688 */ 689 690 /* 691 * There are two different ways that the mii bus is connected 692 * to this chip. Select the right one based on a compile-time 693 * option. 694 */ 695 if (sc->use_rmii) 696 WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) | ETH_CFG_RMII); 697 else 698 WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) & ~ETH_CFG_RMII); 699 700 /* 701 * Turn on the multicast hash, and write 0's to it. 702 */ 703 WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) | ETH_CFG_MTI); 704 WR4(sc, ETH_HSH, 0); 705 WR4(sc, ETH_HSL, 0); 706 707 WR4(sc, ETH_CTL, RD4(sc, ETH_CTL) | ETH_CTL_TE | ETH_CTL_RE); 708 WR4(sc, ETH_IER, ETH_ISR_RCOM | ETH_ISR_TCOM | ETH_ISR_RBNA); 709 710 /* 711 * Boot loader fills in MAC address. If that's not the case, then 712 * we should set SA1L and SA1H here to the appropriate value. Note: 713 * the byte order is big endian, not little endian, so we have some 714 * swapping to do. Again, if we need it (which I don't think we do). 715 */ 716 ate_setmcast(sc); 717 718 /* 719 * Set 'running' flag, and clear output active flag 720 * and attempt to start the output 721 */ 722 ifp->if_drv_flags |= IFF_DRV_RUNNING; 723 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 724 atestart_locked(ifp); 725 726 callout_reset(&sc->tick_ch, hz, ate_tick, sc); 727} 728 729/* 730 * dequeu packets and transmit 731 */ 732static void 733atestart_locked(struct ifnet *ifp) 734{ 735 struct ate_softc *sc = ifp->if_softc; 736 struct mbuf *m, *mdefrag; 737 bus_dma_segment_t segs[1]; 738 int nseg; 739 740 ATE_ASSERT_LOCKED(sc); 741 if (ifp->if_drv_flags & IFF_DRV_OACTIVE) 742 return; 743 744 while (sc->txcur < ATE_MAX_TX_BUFFERS) { 745 /* 746 * check to see if there's room to put another packet into the 747 * xmit queue. The EMAC chip has a ping-pong buffer for xmit 748 * packets. We use OACTIVE to indicate "we can stuff more into 749 * our buffers (clear) or not (set)." 750 */ 751 if (!(RD4(sc, ETH_TSR) & ETH_TSR_BNQ)) { 752 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 753 return; 754 } 755 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 756 if (m == 0) { 757 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 758 return; 759 } 760 mdefrag = m_defrag(m, M_DONTWAIT); 761 if (mdefrag == NULL) { 762 IFQ_DRV_PREPEND(&ifp->if_snd, m); 763 return; 764 } 765 m = mdefrag; 766 if (bus_dmamap_load_mbuf_sg(sc->mtag, sc->tx_map[sc->txcur], m, 767 segs, &nseg, 0) != 0) { 768 m_freem(m); 769 continue; 770 } 771 bus_dmamap_sync(sc->mtag, sc->tx_map[sc->txcur], 772 BUS_DMASYNC_PREWRITE); 773 774 /* 775 * tell the hardware to xmit the packet. 776 */ 777 WR4(sc, ETH_TAR, segs[0].ds_addr); 778 WR4(sc, ETH_TCR, segs[0].ds_len); 779 780 /* 781 * Tap off here if there is a bpf listener. 782 */ 783 BPF_MTAP(ifp, m); 784 785 sc->sent_mbuf[sc->txcur] = m; 786 sc->txcur++; 787 } 788} 789 790static void 791ateinit(void *xsc) 792{ 793 struct ate_softc *sc = xsc; 794 ATE_LOCK(sc); 795 ateinit_locked(sc); 796 ATE_UNLOCK(sc); 797} 798 799static void 800atestart(struct ifnet *ifp) 801{ 802 struct ate_softc *sc = ifp->if_softc; 803 ATE_LOCK(sc); 804 atestart_locked(ifp); 805 ATE_UNLOCK(sc); 806} 807 808/* 809 * Turn off interrupts, and stop the nic. Can be called with sc->ifp NULL 810 * so be careful. 811 */ 812static void 813atestop(struct ate_softc *sc) 814{ 815 struct ifnet *ifp = sc->ifp; 816 817 if (ifp) { 818 ifp->if_timer = 0; 819 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 820 } 821 822 callout_stop(&sc->tick_ch); 823 824 /* 825 * Enable some parts of the MAC that are needed always (like the 826 * MII bus. This turns off the RE and TE bits, which will remain 827 * off until ateinit() is called to turn them on. With RE and TE 828 * turned off, there's no DMA to worry about after this write. 829 */ 830 WR4(sc, ETH_CTL, ETH_CTL_MPE); 831 832 /* 833 * Turn off all the configured options and revert to defaults. 834 */ 835 WR4(sc, ETH_CFG, ETH_CFG_CLK_32); 836 837 /* 838 * Turn off all the interrupts, and ack any pending ones by reading 839 * the ISR. 840 */ 841 WR4(sc, ETH_IDR, 0xffffffff); 842 RD4(sc, ETH_ISR); 843 844 /* 845 * Clear out the Transmit and Receiver Status registers of any 846 * errors they may be reporting 847 */ 848 WR4(sc, ETH_TSR, 0xffffffff); 849 WR4(sc, ETH_RSR, 0xffffffff); 850 851 /* 852 * XXX TODO(8) 853 * need to worry about the busdma resources? Yes, I think we need 854 * to sync and unload them. We may also need to release the mbufs 855 * that are assocaited with RX and TX operations. 856 */ 857 858 /* 859 * XXX we should power down the EMAC if it isn't in use, after 860 * putting it into loopback mode. This saves about 400uA according 861 * to the datasheet. 862 */ 863} 864 865static void 866atewatchdog(struct ifnet *ifp) 867{ 868 struct ate_softc *sc = ifp->if_softc; 869 870 ATE_LOCK(sc); 871 device_printf(sc->dev, "Device timeout\n"); 872 ifp->if_oerrors++; 873 ateinit_locked(sc); 874 ATE_UNLOCK(sc); 875} 876 877static int 878ateioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 879{ 880 struct ate_softc *sc = ifp->if_softc; 881 struct mii_data *mii; 882 struct ifreq *ifr = (struct ifreq *)data; 883 int error = 0; 884 885 switch (cmd) { 886 case SIOCSIFFLAGS: 887 ATE_LOCK(sc); 888 if ((ifp->if_flags & IFF_UP) == 0 && 889 ifp->if_drv_flags & IFF_DRV_RUNNING) { 890 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 891 atestop(sc); 892 } else { 893 /* reinitialize card on any parameter change */ 894 ateinit_locked(sc); 895 } 896 ATE_UNLOCK(sc); 897 break; 898 899 case SIOCADDMULTI: 900 case SIOCDELMULTI: 901 /* update multicast filter list. */ 902 ATE_LOCK(sc); 903 ate_setmcast(sc); 904 ATE_UNLOCK(sc); 905 error = 0; 906 break; 907 908 case SIOCSIFMEDIA: 909 case SIOCGIFMEDIA: 910 mii = device_get_softc(sc->miibus); 911 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 912 break; 913 default: 914 error = ether_ioctl(ifp, cmd, data); 915 break; 916 } 917 return (error); 918} 919 920static void 921ate_child_detached(device_t dev, device_t child) 922{ 923 struct ate_softc *sc; 924 925 sc = device_get_softc(dev); 926 if (child == sc->miibus) 927 sc->miibus = NULL; 928} 929 930/* 931 * MII bus support routines. 932 */ 933static int 934ate_miibus_readreg(device_t dev, int phy, int reg) 935{ 936 struct ate_softc *sc; 937 int val; 938 939 /* 940 * XXX if we implement agressive power savings, then we need 941 * XXX to make sure that the clock to the emac is on here 942 */ 943 944 if (phy != 0) 945 return (0xffff); 946 sc = device_get_softc(dev); 947 DELAY(1); /* Hangs w/o this delay really 30.5us atm */ 948 WR4(sc, ETH_MAN, ETH_MAN_REG_RD(phy, reg)); 949 while ((RD4(sc, ETH_SR) & ETH_SR_IDLE) == 0) 950 continue; 951 val = RD4(sc, ETH_MAN) & ETH_MAN_VALUE_MASK; 952 953 return (val); 954} 955 956static void 957ate_miibus_writereg(device_t dev, int phy, int reg, int data) 958{ 959 struct ate_softc *sc; 960 961 /* 962 * XXX if we implement agressive power savings, then we need 963 * XXX to make sure that the clock to the emac is on here 964 */ 965 966 sc = device_get_softc(dev); 967 WR4(sc, ETH_MAN, ETH_MAN_REG_WR(phy, reg, data)); 968 while ((RD4(sc, ETH_SR) & ETH_SR_IDLE) == 0) 969 continue; 970 return; 971} 972 973static device_method_t ate_methods[] = { 974 /* Device interface */ 975 DEVMETHOD(device_probe, ate_probe), 976 DEVMETHOD(device_attach, ate_attach), 977 DEVMETHOD(device_detach, ate_detach), 978 979 /* Bus interface */ 980 DEVMETHOD(bus_child_detached, ate_child_detached), 981 982 /* MII interface */ 983 DEVMETHOD(miibus_readreg, ate_miibus_readreg), 984 DEVMETHOD(miibus_writereg, ate_miibus_writereg), 985 986 { 0, 0 } 987}; 988 989static driver_t ate_driver = { 990 "ate", 991 ate_methods, 992 sizeof(struct ate_softc), 993}; 994 995DRIVER_MODULE(ate, atmelarm, ate_driver, ate_devclass, 0, 0); 996DRIVER_MODULE(miibus, ate, miibus_driver, miibus_devclass, 0, 0); 997MODULE_DEPEND(ate, miibus, 1, 1, 1); 998MODULE_DEPEND(ate, ether, 1, 1, 1); 999