if_ate.c revision 157562
1/*- 2 * Copyright (c) 2006 M. Warner Losh. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 14 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 15 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 16 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 19 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 20 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 23 */ 24 25/* TODO: (in no order) 26 * 27 * 8) Need to sync busdma goo in atestop 28 * 9) atestop should maybe free the mbufs? 29 * 30 * 1) detach 31 * 2) Free dma setup 32 * 3) Turn on the clock in pmc and turn on pins? Turn off? 33 */ 34 35#include <sys/cdefs.h> 36__FBSDID("$FreeBSD: head/sys/arm/at91/if_ate.c 157562 2006-04-06 04:30:23Z imp $"); 37 38#include <sys/param.h> 39#include <sys/systm.h> 40#include <sys/bus.h> 41#include <sys/kernel.h> 42#include <sys/mbuf.h> 43#include <sys/malloc.h> 44#include <sys/module.h> 45#include <sys/rman.h> 46#include <sys/socket.h> 47#include <sys/sockio.h> 48#include <machine/bus.h> 49 50#include <net/ethernet.h> 51#include <net/if.h> 52#include <net/if_arp.h> 53#include <net/if_dl.h> 54#include <net/if_media.h> 55#include <net/if_mib.h> 56#include <net/if_types.h> 57 58#ifdef INET 59#include <netinet/in.h> 60#include <netinet/in_systm.h> 61#include <netinet/in_var.h> 62#include <netinet/ip.h> 63#endif 64 65#include <net/bpf.h> 66#include <net/bpfdesc.h> 67 68#include <dev/mii/mii.h> 69#include <dev/mii/miivar.h> 70#include <arm/at91/if_atereg.h> 71 72#include "miibus_if.h" 73 74#define ATE_MAX_TX_BUFFERS 2 /* We have ping-pong tx buffers */ 75#define ATE_MAX_RX_BUFFERS 64 76 77struct ate_softc 78{ 79 struct ifnet *ifp; /* ifnet pointer */ 80 struct mtx sc_mtx; /* basically a perimeter lock */ 81 device_t dev; /* Myself */ 82 device_t miibus; /* My child miibus */ 83 void *intrhand; /* Interrupt handle */ 84 struct resource *irq_res; /* IRQ resource */ 85 struct resource *mem_res; /* Memory resource */ 86 struct callout tick_ch; /* Tick callout */ 87 bus_dma_tag_t mtag; /* bus dma tag for mbufs */ 88 bus_dmamap_t tx_map[ATE_MAX_TX_BUFFERS]; 89 struct mbuf *sent_mbuf[ATE_MAX_TX_BUFFERS]; /* Sent mbufs */ 90 bus_dma_tag_t rxtag; 91 bus_dmamap_t rx_map[ATE_MAX_RX_BUFFERS]; 92 void *rx_buf[ATE_MAX_RX_BUFFERS]; /* RX buffer space */ 93 int rx_buf_ptr; 94 bus_dma_tag_t rx_desc_tag; 95 bus_dmamap_t rx_desc_map; 96 int txcur; /* current tx map pointer */ 97 bus_addr_t rx_desc_phys; 98 eth_rx_desc_t *rx_descs; 99 struct ifmib_iso_8802_3 mibdata; /* stuff for network mgmt */ 100}; 101 102static inline uint32_t 103RD4(struct ate_softc *sc, bus_size_t off) 104{ 105 return bus_read_4(sc->mem_res, off); 106} 107 108static inline void 109WR4(struct ate_softc *sc, bus_size_t off, uint32_t val) 110{ 111 bus_write_4(sc->mem_res, off, val); 112} 113 114#define ATE_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 115#define ATE_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 116#define ATE_LOCK_INIT(_sc) \ 117 mtx_init(&_sc->sc_mtx, device_get_nameunit(_sc->dev), \ 118 MTX_NETWORK_LOCK, MTX_DEF) 119#define ATE_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx); 120#define ATE_ASSERT_LOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_OWNED); 121#define ATE_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_NOTOWNED); 122 123static devclass_t ate_devclass; 124 125/* ifnet entry points */ 126 127static void ateinit_locked(void *); 128static void atestart_locked(struct ifnet *); 129 130static void ateinit(void *); 131static void atestart(struct ifnet *); 132static void atestop(struct ate_softc *); 133static void atewatchdog(struct ifnet *); 134static int ateioctl(struct ifnet * ifp, u_long, caddr_t); 135 136/* bus entry points */ 137 138static int ate_probe(device_t dev); 139static int ate_attach(device_t dev); 140static int ate_detach(device_t dev); 141static void ate_intr(void *); 142 143/* helper routines */ 144static int ate_activate(device_t dev); 145static void ate_deactivate(device_t dev); 146static int ate_ifmedia_upd(struct ifnet *ifp); 147static void ate_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr); 148static void ate_get_mac(struct ate_softc *sc, u_char *eaddr); 149static void ate_set_mac(struct ate_softc *sc, u_char *eaddr); 150 151/* 152 * The AT91 family of products has the ethernet called EMAC. However, 153 * it isn't self identifying. It is anticipated that the parent bus 154 * code will take care to only add ate devices where they really are. As 155 * such, we do nothing here to identify the device and just set its name. 156 */ 157static int 158ate_probe(device_t dev) 159{ 160 device_set_desc(dev, "EMAC"); 161 return (0); 162} 163 164static int 165ate_attach(device_t dev) 166{ 167 struct ate_softc *sc = device_get_softc(dev); 168 struct ifnet *ifp = NULL; 169 int err; 170 u_char eaddr[6]; 171 172 sc->dev = dev; 173 err = ate_activate(dev); 174 if (err) 175 goto out; 176 177 /* calling atestop before ifp is set is OK */ 178 atestop(sc); 179 ATE_LOCK_INIT(sc); 180 callout_init_mtx(&sc->tick_ch, &sc->sc_mtx, 0); 181 182 ate_get_mac(sc, eaddr); 183 ate_set_mac(sc, eaddr); 184 185 sc->ifp = ifp = if_alloc(IFT_ETHER); 186 if (mii_phy_probe(dev, &sc->miibus, ate_ifmedia_upd, ate_ifmedia_sts)) { 187 device_printf(dev, "Cannot find my PHY.\n"); 188 err = ENXIO; 189 goto out; 190 } 191 192 ifp->if_softc = sc; 193 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 194 ifp->if_mtu = ETHERMTU; 195 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 196 ifp->if_start = atestart; 197 ifp->if_ioctl = ateioctl; 198 ifp->if_watchdog = atewatchdog; 199 ifp->if_init = ateinit; 200 ifp->if_baudrate = 10000000; 201 IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN); 202 ifp->if_snd.ifq_maxlen = IFQ_MAXLEN; 203 IFQ_SET_READY(&ifp->if_snd); 204 ifp->if_timer = 0; 205 ifp->if_linkmib = &sc->mibdata; 206 ifp->if_linkmiblen = sizeof(sc->mibdata); 207 sc->mibdata.dot3Compliance = DOT3COMPLIANCE_COLLS; 208 209 ether_ifattach(ifp, eaddr); 210 211 /* 212 * Activate the interrupt 213 */ 214 err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_NET | INTR_MPSAFE, 215 ate_intr, sc, &sc->intrhand); 216 if (err) { 217 ether_ifdetach(ifp); 218 ATE_LOCK_DESTROY(sc); 219 } 220out:; 221 if (err) 222 ate_deactivate(dev); 223 if (err && ifp) 224 if_free(ifp); 225 return (err); 226} 227 228static int 229ate_detach(device_t dev) 230{ 231 return EBUSY; /* XXX TODO(1) */ 232} 233 234static void 235ate_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 236{ 237 struct ate_softc *sc; 238 239 if (error != 0) 240 return; 241 sc = (struct ate_softc *)arg; 242 sc->rx_desc_phys = segs[0].ds_addr; 243} 244 245static void 246ate_load_rx_buf(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 247{ 248 struct ate_softc *sc; 249 int i; 250 251 if (error != 0) 252 return; 253 sc = (struct ate_softc *)arg; 254 i = sc->rx_buf_ptr; 255 256 /* 257 * For the last buffer, set the wrap bit so the controller 258 * restarts from the first descriptor. 259 */ 260 if (i == ATE_MAX_RX_BUFFERS - 1) 261 sc->rx_descs[i].addr = segs[0].ds_addr | ETH_WRAP_BIT; 262 else 263 sc->rx_descs[i].addr = segs[0].ds_addr; 264 sc->rx_descs[i].status = 0; 265 /* Flush the memory in the mbuf */ 266 bus_dmamap_sync(sc->rxtag, sc->rx_map[i], BUS_DMASYNC_PREREAD); 267} 268 269/* 270 * Compute the multicast filter for this device using the standard 271 * algorithm. I wonder why this isn't in ether somewhere as a lot 272 * of different MAC chips use this method (or the reverse the bits) 273 * method. 274 */ 275static void 276ate_setmcast(struct ate_softc *sc) 277{ 278 uint32_t index; 279 uint32_t mcaf[2]; 280 u_char *af = (u_char *) mcaf; 281 struct ifmultiaddr *ifma; 282 283 mcaf[0] = 0; 284 mcaf[1] = 0; 285 286 IF_ADDR_LOCK(sc->ifp); 287 TAILQ_FOREACH(ifma, &sc->ifp->if_multiaddrs, ifma_link) { 288 if (ifma->ifma_addr->sa_family != AF_LINK) 289 continue; 290 index = ether_crc32_be(LLADDR((struct sockaddr_dl *) 291 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 292 af[index >> 3] |= 1 << (index & 7); 293 } 294 IF_ADDR_UNLOCK(sc->ifp); 295 296 /* 297 * Write the hash to the hash register. This card can also 298 * accept unicast packets as well as multicast packets using this 299 * register for easier bridging operations, but we don't take 300 * advantage of that. Locks here are to avoid LOR with the 301 * IF_ADDR_LOCK, but might not be strictly necessary. 302 */ 303 WR4(sc, ETH_HSL, mcaf[0]); 304 WR4(sc, ETH_HSH, mcaf[1]); 305} 306 307static int 308ate_activate(device_t dev) 309{ 310 struct ate_softc *sc; 311 int rid, err, i; 312 313 sc = device_get_softc(dev); 314 rid = 0; 315 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 316 RF_ACTIVE); 317 if (sc->mem_res == NULL) 318 goto errout; 319 rid = 0; 320 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 321 RF_ACTIVE); 322 if (sc->mem_res == NULL) 323 goto errout; 324 325 /* 326 * Allocate DMA tags and maps 327 */ 328 err = bus_dma_tag_create(NULL, 1, 0, BUS_SPACE_MAXADDR_32BIT, 329 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 1, MCLBYTES, 0, 330 busdma_lock_mutex, &sc->sc_mtx, &sc->mtag); 331 if (err != 0) 332 goto errout; 333 for (i = 0; i < ATE_MAX_TX_BUFFERS; i++) { 334 err = bus_dmamap_create(sc->mtag, 0, &sc->tx_map[i]); 335 if (err != 0) 336 goto errout; 337 } 338 /* 339 * Allocate our Rx buffers. This chip has a rx structure that's filled 340 * in 341 */ 342 343 /* 344 * Allocate DMA tags and maps for RX. 345 */ 346 err = bus_dma_tag_create(NULL, 1, 0, BUS_SPACE_MAXADDR_32BIT, 347 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 1, MCLBYTES, 0, 348 busdma_lock_mutex, &sc->sc_mtx, &sc->rxtag); 349 if (err != 0) 350 goto errout; 351 for (i = 0; i < ATE_MAX_RX_BUFFERS; i++) { 352 err = bus_dmamap_create(sc->rxtag, 0, &sc->rx_map[i]); 353 if (err != 0) 354 goto errout; 355 } 356 357 /* Dma TAG and MAP for the rx descriptors. */ 358 err = bus_dma_tag_create(NULL, sizeof(eth_rx_desc_t), 0, 359 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 360 ATE_MAX_RX_BUFFERS * sizeof(eth_rx_desc_t), 1, 361 ATE_MAX_RX_BUFFERS * sizeof(eth_rx_desc_t), 0, busdma_lock_mutex, 362 &sc->sc_mtx, &sc->rx_desc_tag); 363 if (err != 0) 364 goto errout; 365 if (bus_dmamem_alloc(sc->rx_desc_tag, (void **)&sc->rx_descs, 366 BUS_DMA_NOWAIT | BUS_DMA_COHERENT, &sc->rx_desc_map) != 0) 367 goto errout; 368 if (bus_dmamap_load(sc->rx_desc_tag, sc->rx_desc_map, 369 sc->rx_descs, ATE_MAX_RX_BUFFERS * sizeof(eth_rx_desc_t), 370 ate_getaddr, sc, 0) != 0) 371 goto errout; 372 /* XXX TODO(5) Put this in ateinit_locked? */ 373 for (i = 0; i < ATE_MAX_RX_BUFFERS; i++) { 374 sc->rx_buf_ptr = i; 375 if (bus_dmamem_alloc(sc->rxtag, (void **)&sc->rx_buf[i], 376 BUS_DMA_NOWAIT, &sc->rx_map[i]) != 0) 377 goto errout; 378 if (bus_dmamap_load(sc->rxtag, sc->rx_map[i], sc->rx_buf[i], 379 MCLBYTES, ate_load_rx_buf, sc, 0) != 0) 380 goto errout; 381 } 382 sc->rx_buf_ptr = 0; 383 /* Flush the memory for the EMAC rx descriptor */ 384 bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, BUS_DMASYNC_PREWRITE); 385 /* Write the descriptor queue address. */ 386 WR4(sc, ETH_RBQP, sc->rx_desc_phys); 387 return (0); 388errout: 389 ate_deactivate(dev); 390 return (ENOMEM); 391} 392 393static void 394ate_deactivate(device_t dev) 395{ 396 struct ate_softc *sc; 397 398 sc = device_get_softc(dev); 399 /* XXX TODO(2) teardown busdma junk, below from fxp -- customize */ 400#if 0 401 if (sc->fxp_mtag) { 402 for (i = 0; i < FXP_NRFABUFS; i++) { 403 rxp = &sc->fxp_desc.rx_list[i]; 404 if (rxp->rx_mbuf != NULL) { 405 bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map, 406 BUS_DMASYNC_POSTREAD); 407 bus_dmamap_unload(sc->fxp_mtag, rxp->rx_map); 408 m_freem(rxp->rx_mbuf); 409 } 410 bus_dmamap_destroy(sc->fxp_mtag, rxp->rx_map); 411 } 412 bus_dmamap_destroy(sc->fxp_mtag, sc->spare_map); 413 for (i = 0; i < FXP_NTXCB; i++) { 414 txp = &sc->fxp_desc.tx_list[i]; 415 if (txp->tx_mbuf != NULL) { 416 bus_dmamap_sync(sc->fxp_mtag, txp->tx_map, 417 BUS_DMASYNC_POSTWRITE); 418 bus_dmamap_unload(sc->fxp_mtag, txp->tx_map); 419 m_freem(txp->tx_mbuf); 420 } 421 bus_dmamap_destroy(sc->fxp_mtag, txp->tx_map); 422 } 423 bus_dma_tag_destroy(sc->fxp_mtag); 424 } 425 if (sc->fxp_stag) 426 bus_dma_tag_destroy(sc->fxp_stag); 427 if (sc->cbl_tag) 428 bus_dma_tag_destroy(sc->cbl_tag); 429 if (sc->mcs_tag) 430 bus_dma_tag_destroy(sc->mcs_tag); 431#endif 432 if (sc->intrhand) 433 bus_teardown_intr(dev, sc->irq_res, sc->intrhand); 434 sc->intrhand = 0; 435 bus_generic_detach(sc->dev); 436 if (sc->miibus) 437 device_delete_child(sc->dev, sc->miibus); 438 if (sc->mem_res) 439 bus_release_resource(dev, SYS_RES_IOPORT, 440 rman_get_rid(sc->mem_res), sc->mem_res); 441 sc->mem_res = 0; 442 if (sc->irq_res) 443 bus_release_resource(dev, SYS_RES_IRQ, 444 rman_get_rid(sc->irq_res), sc->irq_res); 445 sc->irq_res = 0; 446 return; 447} 448 449/* 450 * Change media according to request. 451 */ 452static int 453ate_ifmedia_upd(struct ifnet *ifp) 454{ 455 struct ate_softc *sc = ifp->if_softc; 456 struct mii_data *mii; 457 458 mii = device_get_softc(sc->miibus); 459 ATE_LOCK(sc); 460 mii_mediachg(mii); 461 ATE_UNLOCK(sc); 462 return (0); 463} 464 465/* 466 * Notify the world which media we're using. 467 */ 468static void 469ate_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 470{ 471 struct ate_softc *sc = ifp->if_softc; 472 struct mii_data *mii; 473 474 mii = device_get_softc(sc->miibus); 475 ATE_LOCK(sc); 476 mii_pollstat(mii); 477 ifmr->ifm_active = mii->mii_media_active; 478 ifmr->ifm_status = mii->mii_media_status; 479 ATE_UNLOCK(sc); 480} 481 482static void 483ate_tick(void *xsc) 484{ 485 struct ate_softc *sc = xsc; 486 struct mii_data *mii; 487 int active; 488 489 /* 490 * The KB920x boot loader tests ETH_SR & ETH_SR_LINK and will ask 491 * the MII if there's a link if this bit is clear. Not sure if we 492 * should do the same thing here or not. 493 */ 494 ATE_ASSERT_LOCKED(sc); 495 if (sc->miibus != NULL) { 496 mii = device_get_softc(sc->miibus); 497 active = mii->mii_media_active; 498 mii_tick(mii); 499 if (mii->mii_media_status & IFM_ACTIVE && 500 active != mii->mii_media_active) { 501 /* 502 * The speed and full/half-duplex state needs 503 * to be reflected in the ETH_CFG register, it 504 * seems. 505 */ 506 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T) 507 WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) & 508 ~ETH_CFG_SPD); 509 else 510 WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) | 511 ETH_CFG_SPD); 512 if (mii->mii_media_active & IFM_FDX) 513 WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) | 514 ETH_CFG_FD); 515 else 516 WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) & 517 ~ETH_CFG_FD); 518 } 519 } 520 521 /* 522 * Update the stats as best we can. When we're done, clear 523 * the status counters and start over. We're supposed to read these 524 * registers often enough that they won't overflow. Hopefully 525 * once a second is often enough. Some don't map well to 526 * the dot3Stats mib, so for those we just count them as general 527 * errors. Stats for iframes, ibutes, oframes and obytes are 528 * collected elsewhere. These registers zero on a read to prevent 529 * races. 530 */ 531 sc->mibdata.dot3StatsAlignmentErrors += RD4(sc, ETH_ALE); 532 sc->mibdata.dot3StatsFCSErrors += RD4(sc, ETH_SEQE); 533 sc->mibdata.dot3StatsSingleCollisionFrames += RD4(sc, ETH_SCOL); 534 sc->mibdata.dot3StatsMultipleCollisionFrames += RD4(sc, ETH_MCOL); 535 sc->mibdata.dot3StatsSQETestErrors += RD4(sc, ETH_SQEE); 536 sc->mibdata.dot3StatsDeferredTransmissions += RD4(sc, ETH_DTE); 537 sc->mibdata.dot3StatsLateCollisions += RD4(sc, ETH_LCOL); 538 sc->mibdata.dot3StatsExcessiveCollisions += RD4(sc, ETH_ECOL); 539 sc->mibdata.dot3StatsCarrierSenseErrors += RD4(sc, ETH_CSE); 540 sc->mibdata.dot3StatsFrameTooLongs += RD4(sc, ETH_ELR); 541 sc->mibdata.dot3StatsInternalMacReceiveErrors += RD4(sc, ETH_DRFC); 542 /* 543 * not sure where to lump these, so count them against the errors 544 * for the interface. 545 */ 546 sc->ifp->if_oerrors += RD4(sc, ETH_CSE) + RD4(sc, ETH_TUE); 547 sc->ifp->if_ierrors += RD4(sc, ETH_CDE) + RD4(sc, ETH_RJB) + 548 RD4(sc, ETH_USF); 549 550 /* 551 * Schedule another timeout one second from now. 552 */ 553 callout_reset(&sc->tick_ch, hz, ate_tick, sc); 554} 555 556static void 557ate_set_mac(struct ate_softc *sc, u_char *eaddr) 558{ 559 WR4(sc, ETH_SA1L, (eaddr[3] << 24) | (eaddr[2] << 16) | 560 (eaddr[1] << 8) | eaddr[0]); 561 WR4(sc, ETH_SA1H, (eaddr[5] << 8) | (eaddr[4])); 562 563} 564 565static void 566ate_get_mac(struct ate_softc *sc, u_char *eaddr) 567{ 568 uint32_t low, high; 569 570 /* 571 * The KB920x loaders will setup the MAC with an address, if one 572 * is set in the loader. The TSC loader will also set the MAC address 573 * in a similar way. Grab the MAC address from the SA1[HL] registers. 574 */ 575 low = RD4(sc, ETH_SA1L); 576 high = RD4(sc, ETH_SA1H); 577 eaddr[0] = (high >> 8) & 0xff; 578 eaddr[1] = high & 0xff; 579 eaddr[2] = (low >> 24) & 0xff; 580 eaddr[3] = (low >> 16) & 0xff; 581 eaddr[4] = (low >> 8) & 0xff; 582 eaddr[5] = low & 0xff; 583} 584 585static void 586ate_intr(void *xsc) 587{ 588 struct ate_softc *sc = xsc; 589 int status; 590 int i; 591 void *bp; 592 struct mbuf *mb; 593 uint32_t rx_stat; 594 595 status = RD4(sc, ETH_ISR); 596 if (status == 0) 597 return; 598 if (status & ETH_ISR_RCOM) { 599 bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, 600 BUS_DMASYNC_POSTREAD); 601 while (sc->rx_descs[sc->rx_buf_ptr].addr & ETH_CPU_OWNER) { 602 i = sc->rx_buf_ptr; 603 sc->rx_buf_ptr = (i + 1) % ATE_MAX_RX_BUFFERS; 604 bp = sc->rx_buf[i]; 605 rx_stat = sc->rx_descs[i].status; 606 if ((rx_stat & ETH_LEN_MASK) == 0) { 607 printf("ignoring bogus 0 len packet\n"); 608 sc->rx_descs[i].addr &= ~ETH_CPU_OWNER; 609 bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, 610 BUS_DMASYNC_PREWRITE); 611 continue; 612 } 613 /* Flush memory for mbuf so we don't get stale bytes */ 614 bus_dmamap_sync(sc->rxtag, sc->rx_map[i], 615 BUS_DMASYNC_POSTREAD); 616 WR4(sc, ETH_RSR, RD4(sc, ETH_RSR)); // XXX WHY? XXX imp 617 /* 618 * The length returned by the device includes the 619 * ethernet CRC calculation for the packet, but 620 * ifnet drivers are supposed to discard it. 621 */ 622 mb = m_devget(sc->rx_buf[i], 623 (rx_stat & ETH_LEN_MASK) - ETHER_CRC_LEN, 624 ETHER_ALIGN, sc->ifp, NULL); 625 sc->rx_descs[i].addr &= ~ETH_CPU_OWNER; 626 bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, 627 BUS_DMASYNC_PREWRITE); 628 bus_dmamap_sync(sc->rxtag, sc->rx_map[i], 629 BUS_DMASYNC_PREREAD); 630 if (mb != NULL) 631 (*sc->ifp->if_input)(sc->ifp, mb); 632 } 633 } 634 if (status & ETH_ISR_TCOM) { 635 ATE_LOCK(sc); 636 if (sc->sent_mbuf[0]) { 637 m_freem(sc->sent_mbuf[0]); 638 sc->sent_mbuf[0] = NULL; 639 } 640 if (sc->sent_mbuf[1]) { 641 if (RD4(sc, ETH_TSR) & ETH_TSR_IDLE) { 642 m_freem(sc->sent_mbuf[1]); 643 sc->txcur = 0; 644 sc->sent_mbuf[0] = sc->sent_mbuf[1] = NULL; 645 } else { 646 sc->sent_mbuf[0] = sc->sent_mbuf[1]; 647 sc->sent_mbuf[1] = NULL; 648 sc->txcur = 1; 649 } 650 } else { 651 sc->sent_mbuf[0] = NULL; 652 sc->txcur = 0; 653 } 654 /* 655 * We're no longer busy, so clear the busy flag and call the 656 * start routine to xmit more packets. 657 */ 658 sc->ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 659 atestart_locked(sc->ifp); 660 ATE_UNLOCK(sc); 661 } 662 if (status & ETH_ISR_RBNA) { 663 printf("RBNA workaround\n"); 664 /* Workaround Errata #11 */ 665 WR4(sc, ETH_CTL, RD4(sc, ETH_CTL) &~ ETH_CTL_RE); 666 WR4(sc, ETH_CTL, RD4(sc, ETH_CTL) | ETH_CTL_RE); 667 } 668} 669 670/* 671 * Reset and initialize the chip 672 */ 673static void 674ateinit_locked(void *xsc) 675{ 676 struct ate_softc *sc = xsc; 677 struct ifnet *ifp = sc->ifp; 678 679 ATE_ASSERT_LOCKED(sc); 680 681 /* 682 * XXX TODO(3) 683 * we need to turn on the EMAC clock in the pmc. With the 684 * default boot loader, this is already turned on. However, we 685 * need to think about how best to turn it on/off as the interface 686 * is brought up/down, as well as dealing with the mii bus... 687 * 688 * We also need to multiplex the pins correctly. 689 */ 690 691 /* 692 * There are two different ways that the mii bus is connected 693 * to this chip. Select the right one based on a compile-time 694 * option. 695 */ 696#ifdef ATE_USE_RMII 697 WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) | ETH_CFG_RMII); 698#else 699 WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) & ~ETH_CFG_RMII); 700#endif 701 /* 702 * Turn on the multicast hash, and write 0's to it. 703 */ 704 WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) | ETH_CFG_MTI); 705 WR4(sc, ETH_HSH, 0); 706 WR4(sc, ETH_HSL, 0); 707 708 WR4(sc, ETH_CTL, RD4(sc, ETH_CTL) | ETH_CTL_TE | ETH_CTL_RE); 709 WR4(sc, ETH_IER, ETH_ISR_RCOM | ETH_ISR_TCOM | ETH_ISR_RBNA); 710 711 /* 712 * Boot loader fills in MAC address. If that's not the case, then 713 * we should set SA1L and SA1H here to the appropriate value. Note: 714 * the byte order is big endian, not little endian, so we have some 715 * swapping to do. Again, if we need it (which I don't think we do). 716 */ 717 ate_setmcast(sc); 718 719 /* 720 * Set 'running' flag, and clear output active flag 721 * and attempt to start the output 722 */ 723 ifp->if_drv_flags |= IFF_DRV_RUNNING; 724 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 725 atestart_locked(ifp); 726 727 callout_reset(&sc->tick_ch, hz, ate_tick, sc); 728} 729 730/* 731 * dequeu packets and transmit 732 */ 733static void 734atestart_locked(struct ifnet *ifp) 735{ 736 struct ate_softc *sc = ifp->if_softc; 737 struct mbuf *m, *mdefrag; 738 bus_dma_segment_t segs[1]; 739 int nseg; 740 741 ATE_ASSERT_LOCKED(sc); 742 if (ifp->if_drv_flags & IFF_DRV_OACTIVE) 743 return; 744 745 while (sc->txcur < ATE_MAX_TX_BUFFERS) { 746 /* 747 * check to see if there's room to put another packet into the 748 * xmit queue. The EMAC chip has a ping-pong buffer for xmit 749 * packets. We use OACTIVE to indicate "we can stuff more into 750 * our buffers (clear) or not (set)." 751 */ 752 if (!(RD4(sc, ETH_TSR) & ETH_TSR_BNQ)) { 753 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 754 return; 755 } 756 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 757 if (m == 0) { 758 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 759 return; 760 } 761 mdefrag = m_defrag(m, M_DONTWAIT); 762 if (mdefrag == NULL) { 763 m_freem(m); 764 return; 765 } 766 m = mdefrag; 767 if (bus_dmamap_load_mbuf_sg(sc->mtag, sc->tx_map[sc->txcur], m, 768 segs, &nseg, 0) != 0) { 769 m_freem(m); 770 continue; 771 } 772 bus_dmamap_sync(sc->mtag, sc->tx_map[sc->txcur], 773 BUS_DMASYNC_PREWRITE); 774 775 /* 776 * tell the hardware to xmit the packet. 777 */ 778 WR4(sc, ETH_TAR, segs[0].ds_addr); 779 WR4(sc, ETH_TCR, segs[0].ds_len); 780 781 /* 782 * Tap off here if there is a bpf listener. 783 */ 784 BPF_MTAP(ifp, m); 785 786 sc->sent_mbuf[sc->txcur] = m; 787 sc->txcur++; 788 } 789} 790 791static void 792ateinit(void *xsc) 793{ 794 struct ate_softc *sc = xsc; 795 ATE_LOCK(sc); 796 ateinit_locked(sc); 797 ATE_UNLOCK(sc); 798} 799 800static void 801atestart(struct ifnet *ifp) 802{ 803 struct ate_softc *sc = ifp->if_softc; 804 ATE_LOCK(sc); 805 atestart_locked(ifp); 806 ATE_UNLOCK(sc); 807} 808 809/* 810 * Turn off interrupts, and stop the nic. Can be called with sc->ifp NULL 811 * so be careful. 812 */ 813static void 814atestop(struct ate_softc *sc) 815{ 816 struct ifnet *ifp = sc->ifp; 817 818 if (ifp) { 819 ifp->if_timer = 0; 820 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 821 } 822 823 callout_stop(&sc->tick_ch); 824 825 /* 826 * Enable some parts of the MAC that are needed always (like the 827 * MII bus. This turns off the RE and TE bits, which will remain 828 * off until ateinit() is called to turn them on. With RE and TE 829 * turned off, there's no DMA to worry about after this write. 830 */ 831 WR4(sc, ETH_CTL, ETH_CTL_MPE); 832 833 /* 834 * Turn off all the configured options and revert to defaults. 835 */ 836 WR4(sc, ETH_CFG, ETH_CFG_CLK_32); 837 838 /* 839 * Turn off all the interrupts, and ack any pending ones by reading 840 * the ISR. 841 */ 842 WR4(sc, ETH_IDR, 0xffffffff); 843 RD4(sc, ETH_ISR); 844 845 /* 846 * Clear out the Transmit and Receiver Status registers of any 847 * errors they may be reporting 848 */ 849 WR4(sc, ETH_TSR, 0xffffffff); 850 WR4(sc, ETH_RSR, 0xffffffff); 851 852 /* 853 * XXX TODO(8) 854 * need to worry about the busdma resources? Yes, I think we need 855 * to sync and unload them. We may also need to release the mbufs 856 * that are assocaited with RX and TX operations. 857 */ 858 859 /* 860 * XXX we should power down the EMAC if it isn't in use, after 861 * putting it into loopback mode. This saves about 400uA according 862 * to the datasheet. 863 */ 864} 865 866static void 867atewatchdog(struct ifnet *ifp) 868{ 869 struct ate_softc *sc = ifp->if_softc; 870 871 ATE_LOCK(sc); 872 device_printf(sc->dev, "Device timeout\n"); 873 ifp->if_oerrors++; 874 ateinit_locked(sc); 875 ATE_UNLOCK(sc); 876} 877 878static int 879ateioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 880{ 881 struct ate_softc *sc = ifp->if_softc; 882 struct mii_data *mii; 883 struct ifreq *ifr = (struct ifreq *)data; 884 int error = 0; 885 886 switch (cmd) { 887 case SIOCSIFFLAGS: 888 ATE_LOCK(sc); 889 if ((ifp->if_flags & IFF_UP) == 0 && 890 ifp->if_drv_flags & IFF_DRV_RUNNING) { 891 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 892 atestop(sc); 893 } else { 894 /* reinitialize card on any parameter change */ 895 ateinit_locked(sc); 896 } 897 ATE_UNLOCK(sc); 898 break; 899 900 case SIOCADDMULTI: 901 case SIOCDELMULTI: 902 /* update multicast filter list. */ 903 ATE_LOCK(sc); 904 ate_setmcast(sc); 905 ATE_UNLOCK(sc); 906 error = 0; 907 break; 908 909 case SIOCSIFMEDIA: 910 case SIOCGIFMEDIA: 911 mii = device_get_softc(sc->miibus); 912 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 913 break; 914 default: 915 error = ether_ioctl(ifp, cmd, data); 916 break; 917 } 918 return (error); 919} 920 921static void 922ate_child_detached(device_t dev, device_t child) 923{ 924 struct ate_softc *sc; 925 926 sc = device_get_softc(dev); 927 if (child == sc->miibus) 928 sc->miibus = NULL; 929} 930 931/* 932 * MII bus support routines. 933 */ 934static int 935ate_miibus_readreg(device_t dev, int phy, int reg) 936{ 937 struct ate_softc *sc; 938 int val; 939 940 /* 941 * XXX if we implement agressive power savings, then we need 942 * XXX to make sure that the clock to the emac is on here 943 */ 944 945 if (phy != 0) 946 return (0xffff); 947 sc = device_get_softc(dev); 948 DELAY(1); /* Hangs w/o this delay really 30.5us atm */ 949 WR4(sc, ETH_MAN, ETH_MAN_REG_RD(phy, reg)); 950 while ((RD4(sc, ETH_SR) & ETH_SR_IDLE) == 0) 951 continue; 952 val = RD4(sc, ETH_MAN) & ETH_MAN_VALUE_MASK; 953 954 return (val); 955} 956 957static void 958ate_miibus_writereg(device_t dev, int phy, int reg, int data) 959{ 960 struct ate_softc *sc; 961 962 /* 963 * XXX if we implement agressive power savings, then we need 964 * XXX to make sure that the clock to the emac is on here 965 */ 966 967 sc = device_get_softc(dev); 968 WR4(sc, ETH_MAN, ETH_MAN_REG_WR(phy, reg, data)); 969 while ((RD4(sc, ETH_SR) & ETH_SR_IDLE) == 0) 970 continue; 971 return; 972} 973 974static device_method_t ate_methods[] = { 975 /* Device interface */ 976 DEVMETHOD(device_probe, ate_probe), 977 DEVMETHOD(device_attach, ate_attach), 978 DEVMETHOD(device_detach, ate_detach), 979 980 /* Bus interface */ 981 DEVMETHOD(bus_child_detached, ate_child_detached), 982 983 /* MII interface */ 984 DEVMETHOD(miibus_readreg, ate_miibus_readreg), 985 DEVMETHOD(miibus_writereg, ate_miibus_writereg), 986 987 { 0, 0 } 988}; 989 990static driver_t ate_driver = { 991 "ate", 992 ate_methods, 993 sizeof(struct ate_softc), 994}; 995 996DRIVER_MODULE(ate, atmelarm, ate_driver, ate_devclass, 0, 0); 997DRIVER_MODULE(miibus, ate, miibus_driver, miibus_devclass, 0, 0); 998MODULE_DEPEND(ate, miibus, 1, 1, 1); 999MODULE_DEPEND(ate, ether, 1, 1, 1); 1000