if_ate.c revision 155445
1/*- 2 * Copyright (c) 2006 M. Warner Losh. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 14 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 15 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 16 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 19 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 20 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 23 */ 24 25/* TODO: (in no order) 26 * 27 * 5) Setup RX buffers in ateinit_locked 28 * 8) Need to sync busdma goo in atestop 29 * 9) atestop should maybe free the mbufs? 30 * 10) On Rx, how do we get a new mbuf? 31 * 32 * 1) detach 33 * 2) Free dma setup 34 * 3) Turn on the clock in pmc and turn on pins? Turn off? 35 */ 36 37#include <sys/cdefs.h> 38__FBSDID("$FreeBSD: head/sys/arm/at91/if_ate.c 155445 2006-02-07 21:31:13Z cognet $"); 39 40#include <sys/param.h> 41#include <sys/systm.h> 42#include <sys/bus.h> 43#include <sys/kernel.h> 44#include <sys/mbuf.h> 45#include <sys/malloc.h> 46#include <sys/module.h> 47#include <sys/rman.h> 48#include <sys/socket.h> 49#include <sys/sockio.h> 50#include <machine/bus.h> 51 52#include <net/ethernet.h> 53#include <net/if.h> 54#include <net/if_arp.h> 55#include <net/if_dl.h> 56#include <net/if_media.h> 57#include <net/if_mib.h> 58#include <net/if_types.h> 59 60#ifdef INET 61#include <netinet/in.h> 62#include <netinet/in_systm.h> 63#include <netinet/in_var.h> 64#include <netinet/ip.h> 65#endif 66 67#include <net/bpf.h> 68#include <net/bpfdesc.h> 69 70#include <dev/mii/mii.h> 71#include <dev/mii/miivar.h> 72#include <arm/at91/if_atereg.h> 73 74#include "miibus_if.h" 75 76#define ATE_MAX_TX_BUFFERS 2 /* We have ping-pong tx buffers */ 77#define ATE_MAX_RX_BUFFERS 8 78 79struct ate_softc 80{ 81 struct ifnet *ifp; /* ifnet pointer */ 82 struct mtx sc_mtx; /* basically a perimeter lock */ 83 device_t dev; /* Myself */ 84 device_t miibus; /* My child miibus */ 85 void *intrhand; /* Interrupt handle */ 86 struct resource *irq_res; /* IRQ resource */ 87 struct resource *mem_res; /* Memory resource */ 88 struct callout tick_ch; /* Tick callout */ 89 bus_dma_tag_t mtag; /* bus dma tag for mbufs */ 90 bus_dmamap_t tx_map[ATE_MAX_TX_BUFFERS]; 91 bus_dma_tag_t rxtag; 92 bus_dmamap_t rx_map[ATE_MAX_RX_BUFFERS]; 93 bus_dma_tag_t rx_desc_tag; 94 bus_dmamap_t rx_desc_map; 95 int txcur; /* current tx map pointer */ 96 struct mbuf *sent_mbuf[ATE_MAX_TX_BUFFERS]; /* Sent mbufs */ 97 struct mbuf *rx_mbuf[ATE_MAX_RX_BUFFERS]; /* RX mbufs */ 98 bus_addr_t rx_desc_phys; 99 eth_rx_desc_t *rx_descs; 100 struct ifmib_iso_8802_3 mibdata; /* stuff for network mgmt */ 101}; 102 103static inline uint32_t 104RD4(struct ate_softc *sc, bus_size_t off) 105{ 106 return bus_read_4(sc->mem_res, off); 107} 108 109static inline void 110WR4(struct ate_softc *sc, bus_size_t off, uint32_t val) 111{ 112 bus_write_4(sc->mem_res, off, val); 113} 114 115#define ATE_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 116#define ATE_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 117#define ATE_LOCK_INIT(_sc) \ 118 mtx_init(&_sc->sc_mtx, device_get_nameunit(_sc->dev), \ 119 MTX_NETWORK_LOCK, MTX_DEF) 120#define ATE_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx); 121#define ATE_ASSERT_LOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_OWNED); 122#define ATE_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_NOTOWNED); 123 124static devclass_t ate_devclass; 125 126/* ifnet entry points */ 127 128static void ateinit_locked(void *); 129static void atestart_locked(struct ifnet *); 130 131static void ateinit(void *); 132static void atestart(struct ifnet *); 133static void atestop(struct ate_softc *); 134static void atewatchdog(struct ifnet *); 135static int ateioctl(struct ifnet * ifp, u_long, caddr_t); 136 137/* bus entry points */ 138 139static int ate_probe(device_t dev); 140static int ate_attach(device_t dev); 141static int ate_detach(device_t dev); 142static void ate_intr(void *); 143 144/* helper routines */ 145static int ate_activate(device_t dev); 146static void ate_deactivate(device_t dev); 147static int ate_ifmedia_upd(struct ifnet *ifp); 148static void ate_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr); 149static void ate_get_mac(struct ate_softc *sc, u_char *eaddr); 150static void ate_set_mac(struct ate_softc *sc, u_char *eaddr); 151 152/* 153 * The AT91 family of products has the ethernet called EMAC. However, 154 * it isn't self identifying. It is anticipated that the parent bus 155 * code will take care to only add ate devices where they really are. As 156 * such, we do nothing here to identify the device and just set its name. 157 */ 158static int 159ate_probe(device_t dev) 160{ 161 device_set_desc(dev, "EMAC"); 162 return (0); 163} 164 165static int 166ate_attach(device_t dev) 167{ 168 struct ate_softc *sc = device_get_softc(dev); 169 struct ifnet *ifp = NULL; 170 int err; 171 u_char eaddr[6]; 172 173 sc->dev = dev; 174 err = ate_activate(dev); 175 if (err) 176 goto out; 177 178 /* calling atestop before ifp is set is OK */ 179 atestop(sc); 180 ATE_LOCK_INIT(sc); 181 callout_init_mtx(&sc->tick_ch, &sc->sc_mtx, 0); 182 183 ate_get_mac(sc, eaddr); 184 ate_set_mac(sc, eaddr); 185 186 sc->ifp = ifp = if_alloc(IFT_ETHER); 187 if (mii_phy_probe(dev, &sc->miibus, ate_ifmedia_upd, ate_ifmedia_sts)) { 188 device_printf(dev, "Cannot find my PHY.\n"); 189 err = ENXIO; 190 goto out; 191 } 192 193 ifp->if_softc = sc; 194 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 195 ifp->if_mtu = ETHERMTU; 196 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 197 ifp->if_start = atestart; 198 ifp->if_ioctl = ateioctl; 199 ifp->if_watchdog = atewatchdog; 200 ifp->if_init = ateinit; 201 ifp->if_baudrate = 10000000; 202 IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN); 203 ifp->if_snd.ifq_maxlen = IFQ_MAXLEN; 204 IFQ_SET_READY(&ifp->if_snd); 205 ifp->if_timer = 0; 206 ifp->if_linkmib = &sc->mibdata; 207 ifp->if_linkmiblen = sizeof(sc->mibdata); 208 sc->mibdata.dot3Compliance = DOT3COMPLIANCE_COLLS; 209 210 ether_ifattach(ifp, eaddr); 211 212 /* 213 * Activate the interrupt 214 */ 215 err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_NET | INTR_MPSAFE, 216 ate_intr, sc, &sc->intrhand); 217 if (err) { 218 ether_ifdetach(ifp); 219 ATE_LOCK_DESTROY(sc); 220 } 221out:; 222 if (err) 223 ate_deactivate(dev); 224 if (err && ifp) 225 if_free(ifp); 226 return (err); 227} 228 229static int 230ate_detach(device_t dev) 231{ 232 return EBUSY; /* XXX TODO(1) */ 233} 234 235static void 236ate_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 237{ 238 struct ate_softc *sc; 239 240 if (error != 0) 241 return; 242 sc = (struct ate_softc *)arg; 243 sc->rx_desc_phys = segs[0].ds_addr; 244} 245 246/* 247 * Compute the multicast filter for this device using the standard 248 * algorithm. I wonder why this isn't in ether somewhere as a lot 249 * of different MAC chips use this method (or the reverse the bits) 250 * method. 251 */ 252static void 253ate_setmcast(struct ate_softc *sc) 254{ 255 uint32_t index; 256 uint32_t mcaf[2]; 257 u_char *af = (u_char *) mcaf; 258 struct ifmultiaddr *ifma; 259 260 mcaf[0] = 0; 261 mcaf[1] = 0; 262 263 IF_ADDR_LOCK(sc->ifp); 264 TAILQ_FOREACH(ifma, &sc->ifp->if_multiaddrs, ifma_link) { 265 if (ifma->ifma_addr->sa_family != AF_LINK) 266 continue; 267 index = ether_crc32_be(LLADDR((struct sockaddr_dl *) 268 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 269 af[index >> 3] |= 1 << (index & 7); 270 } 271 IF_ADDR_UNLOCK(sc->ifp); 272 273 /* 274 * Write the hash to the hash register. This card can also 275 * accept unicast packets as well as multicast packets using this 276 * register for easier bridging operations, but we don't take 277 * advantage of that. Locks here are to avoid LOR with the 278 * IF_ADDR_LOCK, but might not be strictly necessary. 279 */ 280 ATE_LOCK(sc); 281 WR4(sc, ETH_HSL, mcaf[0]); 282 WR4(sc, ETH_HSH, mcaf[1]); 283 ATE_UNLOCK(sc); 284} 285 286static int 287ate_activate(device_t dev) 288{ 289 struct ate_softc *sc; 290 int rid, err, i; 291 292 sc = device_get_softc(dev); 293 rid = 0; 294 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 295 RF_ACTIVE); 296 if (sc->mem_res == NULL) 297 goto errout; 298 rid = 0; 299 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 300 RF_ACTIVE); 301 if (sc->mem_res == NULL) 302 goto errout; 303 304 /* 305 * Allocate DMA tags and maps 306 */ 307 err = bus_dma_tag_create(NULL, 1, 0, BUS_SPACE_MAXADDR_32BIT, 308 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 1, MCLBYTES, 0, 309 busdma_lock_mutex, &sc->sc_mtx, &sc->mtag); 310 if (err != 0) 311 goto errout; 312 for (i = 0; i < ATE_MAX_TX_BUFFERS; i++) { 313 err = bus_dmamap_create(sc->mtag, 0, &sc->tx_map[i]); 314 if (err != 0) 315 goto errout; 316 } 317 /* 318 * Allocate our Rx buffers. This chip has a rx structure that's filled 319 * in 320 */ 321 322 /* 323 * Allocate DMA tags and maps for RX. 324 */ 325 err = bus_dma_tag_create(NULL, 1, 0, BUS_SPACE_MAXADDR_32BIT, 326 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 1, MCLBYTES, 0, 327 busdma_lock_mutex, &sc->sc_mtx, &sc->rxtag); 328 if (err != 0) 329 goto errout; 330 for (i = 0; i < ATE_MAX_RX_BUFFERS; i++) { 331 err = bus_dmamap_create(sc->rxtag, 0, &sc->rx_map[i]); 332 if (err != 0) 333 goto errout; 334 } 335 336 /* Dma TAG and MAP for the rx descriptors. */ 337 err = bus_dma_tag_create(NULL, sizeof(eth_rx_desc_t), 0, 338 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 339 ATE_MAX_RX_BUFFERS * sizeof(eth_rx_desc_t), 1, 340 ATE_MAX_RX_BUFFERS * sizeof(eth_rx_desc_t), 0, busdma_lock_mutex, 341 &sc->sc_mtx, &sc->rx_desc_tag); 342 if (err != 0) 343 goto errout; 344 if (bus_dmamem_alloc(sc->rx_desc_tag, (void **)&sc->rx_descs, M_WAITOK, 345 &sc->rx_desc_map) != 0) 346 goto errout; 347 if (bus_dmamap_load(sc->rx_desc_tag, sc->rx_desc_map, 348 sc->rx_descs, ATE_MAX_RX_BUFFERS * sizeof(eth_rx_desc_t), 349 ate_getaddr, sc, 0) != 0) 350 goto errout; 351 /* XXX TODO(5) Put this in ateinit_locked? */ 352 for (i = 0; i < ATE_MAX_RX_BUFFERS; i++) { 353 bus_dma_segment_t seg; 354 int nsegs; 355 356 sc->rx_mbuf[i] = m_getcl(M_WAITOK, MT_DATA, M_PKTHDR); 357 sc->rx_mbuf[i]->m_len = sc->rx_mbuf[i]->m_pkthdr.len = 358 MCLBYTES; 359 if (bus_dmamap_load_mbuf_sg(sc->rxtag, sc->rx_map[i], 360 sc->rx_mbuf[i], &seg, &nsegs, 0) != 0) 361 goto errout; 362 /* 363 * For the last buffer, set the wrap bit so the controller 364 * restarts from the first descriptor. 365 */ 366 if (i == ATE_MAX_RX_BUFFERS - 1) 367 seg.ds_addr |= 1 << 1; 368 sc->rx_descs[i].addr = seg.ds_addr; 369 sc->rx_descs[i].status = 0; 370 bus_dmamap_sync(sc->rxtag, sc->rx_map[i], BUS_DMASYNC_PREWRITE); 371 } 372 bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, BUS_DMASYNC_PREWRITE); 373 /* Write the descriptor queue address. */ 374 WR4(sc, ETH_RBQP, sc->rx_desc_phys); 375 return (0); 376errout: 377 ate_deactivate(dev); 378 return (ENOMEM); 379} 380 381static void 382ate_deactivate(device_t dev) 383{ 384 struct ate_softc *sc; 385 386 sc = device_get_softc(dev); 387 /* XXX TODO(2) teardown busdma junk, below from fxp -- customize */ 388#if 0 389 if (sc->fxp_mtag) { 390 for (i = 0; i < FXP_NRFABUFS; i++) { 391 rxp = &sc->fxp_desc.rx_list[i]; 392 if (rxp->rx_mbuf != NULL) { 393 bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map, 394 BUS_DMASYNC_POSTREAD); 395 bus_dmamap_unload(sc->fxp_mtag, rxp->rx_map); 396 m_freem(rxp->rx_mbuf); 397 } 398 bus_dmamap_destroy(sc->fxp_mtag, rxp->rx_map); 399 } 400 bus_dmamap_destroy(sc->fxp_mtag, sc->spare_map); 401 for (i = 0; i < FXP_NTXCB; i++) { 402 txp = &sc->fxp_desc.tx_list[i]; 403 if (txp->tx_mbuf != NULL) { 404 bus_dmamap_sync(sc->fxp_mtag, txp->tx_map, 405 BUS_DMASYNC_POSTWRITE); 406 bus_dmamap_unload(sc->fxp_mtag, txp->tx_map); 407 m_freem(txp->tx_mbuf); 408 } 409 bus_dmamap_destroy(sc->fxp_mtag, txp->tx_map); 410 } 411 bus_dma_tag_destroy(sc->fxp_mtag); 412 } 413 if (sc->fxp_stag) 414 bus_dma_tag_destroy(sc->fxp_stag); 415 if (sc->cbl_tag) 416 bus_dma_tag_destroy(sc->cbl_tag); 417 if (sc->mcs_tag) 418 bus_dma_tag_destroy(sc->mcs_tag); 419#endif 420 if (sc->intrhand) 421 bus_teardown_intr(dev, sc->irq_res, sc->intrhand); 422 sc->intrhand = 0; 423 bus_generic_detach(sc->dev); 424 if (sc->miibus) 425 device_delete_child(sc->dev, sc->miibus); 426 if (sc->mem_res) 427 bus_release_resource(dev, SYS_RES_IOPORT, 428 rman_get_rid(sc->mem_res), sc->mem_res); 429 sc->mem_res = 0; 430 if (sc->irq_res) 431 bus_release_resource(dev, SYS_RES_IRQ, 432 rman_get_rid(sc->irq_res), sc->irq_res); 433 sc->irq_res = 0; 434 return; 435} 436 437/* 438 * Change media according to request. 439 */ 440static int 441ate_ifmedia_upd(struct ifnet *ifp) 442{ 443 struct ate_softc *sc = ifp->if_softc; 444 struct mii_data *mii; 445 446 mii = device_get_softc(sc->miibus); 447 ATE_LOCK(sc); 448 mii_mediachg(mii); 449 ATE_UNLOCK(sc); 450 return (0); 451} 452 453/* 454 * Notify the world which media we're using. 455 */ 456static void 457ate_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 458{ 459 struct ate_softc *sc = ifp->if_softc; 460 struct mii_data *mii; 461 462 mii = device_get_softc(sc->miibus); 463 ATE_LOCK(sc); 464 mii_pollstat(mii); 465 ifmr->ifm_active = mii->mii_media_active; 466 ifmr->ifm_status = mii->mii_media_status; 467 ATE_UNLOCK(sc); 468} 469 470static void 471ate_tick(void *xsc) 472{ 473 struct ate_softc *sc = xsc; 474 struct mii_data *mii; 475 int active; 476 477 /* 478 * The KB920x boot loader tests ETH_SR & ETH_SR_LINK and will ask 479 * the MII if there's a link if this bit is clear. Not sure if we 480 * should do the same thing here or not. 481 */ 482 ATE_ASSERT_LOCKED(sc); 483 if (sc->miibus != NULL) { 484 mii = device_get_softc(sc->miibus); 485 active = mii->mii_media_active; 486 mii_tick(mii); 487 if (mii->mii_media_status & IFM_ACTIVE && 488 active != mii->mii_media_active) { 489 /* 490 * The speed and full/half-duplex state needs 491 * to be reflected in the ETH_CFG register, it 492 * seems. 493 */ 494 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T) 495 WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) & 496 ~ETH_CFG_SPD); 497 else 498 WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) | 499 ETH_CFG_SPD); 500 if (mii->mii_media_active & IFM_FDX) 501 WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) | 502 ETH_CFG_FD); 503 else 504 WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) & 505 ~ETH_CFG_FD); 506 } 507 } 508 509 /* 510 * Update the stats as best we can. When we're done, clear 511 * the status counters and start over. We're supposed to read these 512 * registers often enough that they won't overflow. Hopefully 513 * once a second is often enough. Some don't map well to 514 * the dot3Stats mib, so for those we just count them as general 515 * errors. Stats for iframes, ibutes, oframes and obytes are 516 * collected elsewhere. These registers zero on a read to prevent 517 * races. 518 */ 519 sc->mibdata.dot3StatsAlignmentErrors += RD4(sc, ETH_ALE); 520 sc->mibdata.dot3StatsFCSErrors += RD4(sc, ETH_SEQE); 521 sc->mibdata.dot3StatsSingleCollisionFrames += RD4(sc, ETH_SCOL); 522 sc->mibdata.dot3StatsMultipleCollisionFrames += RD4(sc, ETH_MCOL); 523 sc->mibdata.dot3StatsSQETestErrors += RD4(sc, ETH_SQEE); 524 sc->mibdata.dot3StatsDeferredTransmissions += RD4(sc, ETH_DTE); 525 sc->mibdata.dot3StatsLateCollisions += RD4(sc, ETH_LCOL); 526 sc->mibdata.dot3StatsExcessiveCollisions += RD4(sc, ETH_ECOL); 527 sc->mibdata.dot3StatsCarrierSenseErrors += RD4(sc, ETH_CSE); 528 sc->mibdata.dot3StatsFrameTooLongs += RD4(sc, ETH_ELR); 529 sc->mibdata.dot3StatsInternalMacReceiveErrors += RD4(sc, ETH_DRFC); 530 /* 531 * not sure where to lump these, so count them against the errors 532 * for the interface. 533 */ 534 sc->ifp->if_oerrors += RD4(sc, ETH_CSE) + RD4(sc, ETH_TUE); 535 sc->ifp->if_ierrors += RD4(sc, ETH_CDE) + RD4(sc, ETH_RJB) + 536 RD4(sc, ETH_USF); 537 538 /* 539 * Schedule another timeout one second from now. 540 */ 541 callout_reset(&sc->tick_ch, hz, ate_tick, sc); 542} 543 544static void 545ate_set_mac(struct ate_softc *sc, u_char *eaddr) 546{ 547 WR4(sc, ETH_SA1L, (eaddr[3] << 24) | (eaddr[2] << 16) | 548 (eaddr[1] << 8) | eaddr[0]); 549 WR4(sc, ETH_SA1H, (eaddr[5] << 8) | (eaddr[4])); 550 551} 552 553static void 554ate_get_mac(struct ate_softc *sc, u_char *eaddr) 555{ 556 uint32_t low, high; 557 558 /* 559 * The KB920x loaders will setup the MAC with an address, if one 560 * is set in the loader. The TSC loader will also set the MAC address 561 * in a similar way. Grab the MAC address from the SA1[HL] registers. 562 */ 563 low = RD4(sc, ETH_SA1L); 564 high = RD4(sc, ETH_SA1H); 565 eaddr[0] = (high >> 8) & 0xff; 566 eaddr[1] = high & 0xff; 567 eaddr[2] = (low >> 24) & 0xff; 568 eaddr[3] = (low >> 16) & 0xff; 569 eaddr[4] = (low >> 8) & 0xff; 570 eaddr[5] = low & 0xff; 571} 572 573static void 574ate_intr(void *xsc) 575{ 576 struct ate_softc *sc = xsc; 577 int status; 578 int i; 579 580 status = RD4(sc, ETH_ISR); 581 if (status == 0) 582 return; 583 printf("IT IS %x %x\n", RD4(sc, ETH_RSR), RD4(sc, ETH_CTL)); 584 585 if (status & ETH_ISR_RCOM) { 586 bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, 587 BUS_DMASYNC_POSTREAD); 588 for (i = 0; i < ATE_MAX_RX_BUFFERS; i++) { 589 if (sc->rx_descs[i].addr & ETH_CPU_OWNER) { 590 struct mbuf *mb = sc->rx_mbuf[i]; 591 bus_dma_segment_t seg; 592 int rx_stat = sc->rx_descs[i].status; 593 int nsegs; 594 595 printf("GOT ONE\n"); 596 bus_dmamap_sync(sc->rxtag, 597 sc->rx_map[i], BUS_DMASYNC_POSTREAD); 598 bus_dmamap_unload(sc->rxtag, 599 sc->rx_map[i]); 600 WR4(sc, ETH_RSR, RD4(sc, ETH_RSR)); 601 /* 602 * Allocate a new buffer to replace this one. 603 * if we cannot, then we drop this packet 604 * and keep the old buffer we had. 605 */ 606 sc->rx_mbuf[i] = m_getcl(M_DONTWAIT, MT_DATA, 607 M_PKTHDR); 608 if (!sc->rx_mbuf[i]) { 609 sc->rx_mbuf[i] = mb; 610 sc->rx_descs[i].addr &= ~ETH_CPU_OWNER; 611 bus_dmamap_sync(sc->rx_desc_tag, 612 sc->rx_desc_map, 613 BUS_DMASYNC_PREWRITE); 614 continue; 615 } 616 if (bus_dmamap_load_mbuf_sg(sc->rxtag, 617 sc->rx_map[i], 618 sc->rx_mbuf[i], &seg, &nsegs, 0) != 0) { 619 sc->rx_mbuf[i] = mb; 620 sc->rx_descs[i].addr &= ~ETH_CPU_OWNER; 621 bus_dmamap_sync(sc->rx_desc_tag, 622 sc->rx_desc_map, 623 BUS_DMASYNC_PREWRITE); 624 continue; 625 } 626 mb->m_len = sc->rx_descs[i].status & 627 ETH_LEN_MASK; 628 mb->m_pkthdr.len = mb->m_len; 629 mb->m_pkthdr.rcvif = sc->ifp; 630 /* 631 * For the last buffer, set the wrap bit so 632 * the controller restarts from the first 633 * descriptor. 634 */ 635 if (i == ATE_MAX_RX_BUFFERS - 1) 636 seg.ds_addr |= 1 << 1; 637 sc->rx_descs[i].addr = seg.ds_addr; 638 sc->rx_descs[i].status = 0; 639 mb->m_len = rx_stat & ETH_LEN_MASK; 640 (*sc->ifp->if_input)(sc->ifp, mb); 641 break; 642 } 643 } 644 } 645 if (status & ETH_ISR_TCOM) { 646 if (sc->sent_mbuf[0]) 647 m_freem(sc->sent_mbuf[0]); 648 if (sc->sent_mbuf[1]) { 649 if (RD4(sc, ETH_TSR) & ETH_TSR_IDLE) { 650 m_freem(sc->sent_mbuf[1]); 651 sc->txcur = 0; 652 sc->sent_mbuf[0] = sc->sent_mbuf[1] = NULL; 653 } else { 654 sc->sent_mbuf[0] = sc->sent_mbuf[1]; 655 sc->sent_mbuf[1] = NULL; 656 sc->txcur = 1; 657 } 658 } else { 659 sc->sent_mbuf[0] = NULL; 660 sc->txcur = 0; 661 } 662 } 663 if (status & ETH_ISR_RBNA) { 664 /* Workaround Errata #11 */ 665 WR4(sc, ETH_CTL, RD4(sc, ETH_CTL) &~ ETH_CTL_RE); 666 WR4(sc, ETH_CTL, RD4(sc, ETH_CTL) | ETH_CTL_RE); 667 } 668} 669 670/* 671 * Reset and initialize the chip 672 */ 673static void 674ateinit_locked(void *xsc) 675{ 676 struct ate_softc *sc = xsc; 677 struct ifnet *ifp = sc->ifp; 678 679 ATE_ASSERT_LOCKED(sc); 680 681 /* 682 * XXX TODO(3) 683 * we need to turn on the EMAC clock in the pmc. With the 684 * default boot loader, this is already turned on. However, we 685 * need to think about how best to turn it on/off as the interface 686 * is brought up/down, as well as dealing with the mii bus... 687 * 688 * We also need to multiplex the pins correctly. 689 */ 690 691 /* 692 * There are two different ways that the mii bus is connected 693 * to this chip. Select the right one based on a compile-time 694 * option. 695 */ 696#ifdef ATE_USE_RMII 697 WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) | ETH_CFG_RMII); 698#else 699 WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) & ~ETH_CFG_RMII); 700#endif 701 /* 702 * Turn on the multicast hash, and write 0's to it. 703 */ 704 WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) | ETH_CFG_MTI); 705 WR4(sc, ETH_HSH, 0); 706 WR4(sc, ETH_HSL, 0); 707 708 WR4(sc, ETH_CTL, RD4(sc, ETH_CTL) | ETH_CTL_TE | ETH_CTL_RE); 709 WR4(sc, ETH_IER, /*ETH_ISR_RCOM | ETH_ISR_TCOM | ETH_ISR_RBNA*/ 710 0xffffffff); 711 712 /* 713 * Boot loader fills in MAC address. If that's not the case, then 714 * we should set SA1L and SA1H here to the appropriate value. Note: 715 * the byte order is big endian, not little endian, so we have some 716 * swapping to do. Again, if we need it (which I don't think we do). 717 */ 718 719 ate_setmcast(sc); 720 721 /* 722 * Set 'running' flag, and clear output active flag 723 * and attempt to start the output 724 */ 725 ifp->if_drv_flags |= IFF_DRV_RUNNING; 726 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 727 atestart_locked(ifp); 728 729 callout_reset(&sc->tick_ch, hz, ate_tick, sc); 730} 731 732/* 733 * dequeu packets and transmit 734 */ 735static void 736atestart_locked(struct ifnet *ifp) 737{ 738 struct ate_softc *sc = ifp->if_softc; 739 struct mbuf *m, *mdefrag; 740 bus_dma_segment_t segs[1]; 741 int nseg; 742 743 ATE_ASSERT_LOCKED(sc); 744 if (ifp->if_drv_flags & IFF_DRV_OACTIVE) 745 return; 746 747outloop: 748 /* 749 * check to see if there's room to put another packet into the 750 * xmit queue. The EMAC chip has a ping-pong buffer for xmit 751 * packets. We use OACTIVE to indicate "we can stuff more into 752 * our buffers (clear) or not (set)." 753 */ 754 if (!(RD4(sc, ETH_TSR) & ETH_TSR_BNQ)) { 755 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 756 return; 757 } 758 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 759 if (m == 0) { 760 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 761 return; 762 } 763 mdefrag = m_defrag(m, M_DONTWAIT); 764 if (mdefrag == NULL) { 765 m_freem(m); 766 return; 767 } 768 m = mdefrag; 769 770 if (bus_dmamap_load_mbuf_sg(sc->mtag, sc->tx_map[sc->txcur], m, segs, 771 &nseg, 0) != 0) { 772 m_free(m); 773 goto outloop; 774 } 775 bus_dmamap_sync(sc->mtag, sc->tx_map[sc->txcur], BUS_DMASYNC_PREWRITE); 776 sc->sent_mbuf[sc->txcur] = m; 777 sc->txcur++; 778 if (sc->txcur >= ATE_MAX_TX_BUFFERS) 779 sc->txcur = 0; 780 781 /* 782 * tell the hardware to xmit the packet. 783 */ 784 WR4(sc, ETH_TAR, segs[0].ds_addr); 785 WR4(sc, ETH_TCR, segs[0].ds_len); 786 787 /* 788 * Tap off here if there is a bpf listener. 789 */ 790 BPF_MTAP(ifp, m); 791 792 /* 793 * Once we've queued one packet, we'll do the rest via the ISR, 794 * save off a pointer. 795 */ 796 sc->sent_mbuf[1] = m; 797} 798 799static void 800ateinit(void *xsc) 801{ 802 struct ate_softc *sc = xsc; 803 ATE_LOCK(sc); 804 ateinit_locked(sc); 805 ATE_UNLOCK(sc); 806} 807 808static void 809atestart(struct ifnet *ifp) 810{ 811 struct ate_softc *sc = ifp->if_softc; 812 ATE_LOCK(sc); 813 atestart_locked(ifp); 814 ATE_UNLOCK(sc); 815} 816 817/* 818 * Turn off interrupts, and stop the nic. Can be called with sc->ifp NULL 819 * so be careful. 820 */ 821static void 822atestop(struct ate_softc *sc) 823{ 824 struct ifnet *ifp = sc->ifp; 825 826 if (ifp) { 827 ifp->if_timer = 0; 828 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 829 } 830 831 callout_stop(&sc->tick_ch); 832 833 /* 834 * Enable some parts of the MAC that are needed always (like the 835 * MII bus. This turns off the RE and TE bits, which will remain 836 * off until ateinit() is called to turn them on. With RE and TE 837 * turned off, there's no DMA to worry about after this write. 838 */ 839 WR4(sc, ETH_CTL, ETH_CTL_MPE); 840 841 /* 842 * Turn off all the configured options and revert to defaults. 843 */ 844 WR4(sc, ETH_CFG, ETH_CFG_CLK_32); 845 846 /* 847 * Turn off all the interrupts, and ack any pending ones by reading 848 * the ISR. 849 */ 850 WR4(sc, ETH_IDR, 0xffffffff); 851 RD4(sc, ETH_ISR); 852 853 /* 854 * Clear out the Transmit and Receiver Status registers of any 855 * errors they may be reporting 856 */ 857 WR4(sc, ETH_TSR, 0xffffffff); 858 WR4(sc, ETH_RSR, 0xffffffff); 859 860 /* 861 * XXX TODO(8) 862 * need to worry about the busdma resources? Yes, I think we need 863 * to sync and unload them. We may also need to release the mbufs 864 * that are assocaited with RX and TX operations. 865 */ 866 867 /* 868 * XXX we should power down the EMAC if it isn't in use, after 869 * putting it into loopback mode. This saves about 400uA according 870 * to the datasheet. 871 */ 872} 873 874static void 875atewatchdog(struct ifnet *ifp) 876{ 877 struct ate_softc *sc = ifp->if_softc; 878 879 ATE_LOCK(sc); 880 device_printf(sc->dev, "Device timeout\n"); 881 ifp->if_oerrors++; 882 ateinit_locked(sc); 883 ATE_UNLOCK(sc); 884} 885 886static int 887ateioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 888{ 889 struct ate_softc *sc = ifp->if_softc; 890 int error = 0; 891 892 switch (cmd) { 893 case SIOCSIFFLAGS: 894 ATE_LOCK(sc); 895 if ((ifp->if_flags & IFF_UP) == 0 && 896 ifp->if_drv_flags & IFF_DRV_RUNNING) { 897 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 898 atestop(sc); 899 } else { 900 /* reinitialize card on any parameter change */ 901 ateinit_locked(sc); 902 } 903 ATE_UNLOCK(sc); 904 break; 905 906 case SIOCADDMULTI: 907 case SIOCDELMULTI: 908 /* update multicast filter list. */ 909 ate_setmcast(sc); 910 error = 0; 911 break; 912 913 default: 914 error = ether_ioctl(ifp, cmd, data); 915 break; 916 } 917 return (error); 918} 919 920static void 921ate_child_detached(device_t dev, device_t child) 922{ 923 struct ate_softc *sc; 924 925 sc = device_get_softc(dev); 926 if (child == sc->miibus) 927 sc->miibus = NULL; 928} 929 930/* 931 * MII bus support routines. 932 */ 933static int 934ate_miibus_readreg(device_t dev, int phy, int reg) 935{ 936 struct ate_softc *sc; 937 int val; 938 939 /* 940 * XXX if we implement agressive power savings, then we need 941 * XXX to make sure that the clock to the emac is on here 942 */ 943 944 if (phy != 0) 945 return (0xffff); 946 sc = device_get_softc(dev); 947 DELAY(1); /* Hangs w/o this delay really 30.5us atm */ 948 WR4(sc, ETH_MAN, ETH_MAN_REG_RD(phy, reg)); 949 while ((RD4(sc, ETH_SR) & ETH_SR_IDLE) == 0) 950 continue; 951 val = RD4(sc, ETH_MAN) & ETH_MAN_VALUE_MASK; 952 953 return (val); 954} 955 956static void 957ate_miibus_writereg(device_t dev, int phy, int reg, int data) 958{ 959 struct ate_softc *sc; 960 961 /* 962 * XXX if we implement agressive power savings, then we need 963 * XXX to make sure that the clock to the emac is on here 964 */ 965 966 sc = device_get_softc(dev); 967 WR4(sc, ETH_MAN, ETH_MAN_REG_WR(phy, reg, data)); 968 while ((RD4(sc, ETH_SR) & ETH_SR_IDLE) == 0) 969 continue; 970 return; 971} 972 973static device_method_t ate_methods[] = { 974 /* Device interface */ 975 DEVMETHOD(device_probe, ate_probe), 976 DEVMETHOD(device_attach, ate_attach), 977 DEVMETHOD(device_detach, ate_detach), 978 979 /* Bus interface */ 980 DEVMETHOD(bus_child_detached, ate_child_detached), 981 982 /* MII interface */ 983 DEVMETHOD(miibus_readreg, ate_miibus_readreg), 984 DEVMETHOD(miibus_writereg, ate_miibus_writereg), 985 986 { 0, 0 } 987}; 988 989static driver_t ate_driver = { 990 "ate", 991 ate_methods, 992 sizeof(struct ate_softc), 993}; 994 995DRIVER_MODULE(ate, atmelarm, ate_driver, ate_devclass, 0, 0); 996DRIVER_MODULE(miibus, ate, miibus_driver, miibus_devclass, 0, 0); 997MODULE_DEPEND(ate, miibus, 1, 1, 1); 998MODULE_DEPEND(ate, ether, 1, 1, 1); 999