if_ate.c revision 155405
1/*- 2 * Copyright (c) 2006 M. Warner Losh. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 14 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 15 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 16 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 19 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 20 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 23 */ 24 25/* TODO: (in no order) 26 * 27 * 5) Setup RX buffers in ateinit_locked 28 * 8) Need to sync busdma goo in atestop 29 * 9) atestop should maybe free the mbufs? 30 * 10) On Rx, how do we get a new mbuf? 31 * 32 * 1) detach 33 * 2) Free dma setup 34 * 3) Turn on the clock in pmc and turn on pins? Turn off? 35 */ 36 37#include <sys/cdefs.h> 38__FBSDID("$FreeBSD: head/sys/arm/at91/if_ate.c 155405 2006-02-06 22:17:42Z cognet $"); 39 40#include <sys/param.h> 41#include <sys/systm.h> 42#include <sys/bus.h> 43#include <sys/kernel.h> 44#include <sys/mbuf.h> 45#include <sys/malloc.h> 46#include <sys/module.h> 47#include <sys/rman.h> 48#include <sys/socket.h> 49#include <sys/sockio.h> 50#include <machine/bus.h> 51 52#include <net/ethernet.h> 53#include <net/if.h> 54#include <net/if_arp.h> 55#include <net/if_dl.h> 56#include <net/if_media.h> 57#include <net/if_mib.h> 58#include <net/if_types.h> 59 60#ifdef INET 61#include <netinet/in.h> 62#include <netinet/in_systm.h> 63#include <netinet/in_var.h> 64#include <netinet/ip.h> 65#endif 66 67#include <net/bpf.h> 68#include <net/bpfdesc.h> 69 70#include <dev/mii/mii.h> 71#include <dev/mii/miivar.h> 72#include <arm/at91/if_atereg.h> 73 74#include "miibus_if.h" 75 76#define ATE_MAX_TX_BUFFERS 2 /* We have ping-pong tx buffers */ 77#define ATE_MAX_RX_BUFFERS 8 78 79struct ate_softc 80{ 81 struct ifnet *ifp; /* ifnet pointer */ 82 struct mtx sc_mtx; /* basically a perimeter lock */ 83 device_t dev; /* Myself */ 84 device_t miibus; /* My child miibus */ 85 void *intrhand; /* Interrupt handle */ 86 struct resource *irq_res; /* IRQ resource */ 87 struct resource *mem_res; /* Memory resource */ 88 struct callout tick_ch; /* Tick callout */ 89 bus_dma_tag_t mtag; /* bus dma tag for mbufs */ 90 bus_dmamap_t tx_map[ATE_MAX_TX_BUFFERS]; 91 bus_dma_tag_t rxtag; 92 bus_dmamap_t rx_map[ATE_MAX_RX_BUFFERS]; 93 bus_dma_tag_t rx_desc_tag; 94 bus_dmamap_t rx_desc_map; 95 int txcur; /* current tx map pointer */ 96 struct mbuf *sent_mbuf[ATE_MAX_TX_BUFFERS]; /* Sent mbufs */ 97 struct mbuf *rx_mbuf[ATE_MAX_RX_BUFFERS]; /* RX mbufs */ 98 bus_addr_t rx_desc_phys; 99 eth_rx_desc_t *rx_descs; 100 struct ifmib_iso_8802_3 mibdata; /* stuff for network mgmt */ 101}; 102 103static inline uint32_t 104RD4(struct ate_softc *sc, bus_size_t off) 105{ 106 return bus_read_4(sc->mem_res, off); 107} 108 109static inline void 110WR4(struct ate_softc *sc, bus_size_t off, uint32_t val) 111{ 112 bus_write_4(sc->mem_res, off, val); 113} 114 115#define ATE_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 116#define ATE_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 117#define ATE_LOCK_INIT(_sc) \ 118 mtx_init(&_sc->sc_mtx, device_get_nameunit(_sc->dev), \ 119 MTX_NETWORK_LOCK, MTX_DEF) 120#define ATE_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx); 121#define ATE_ASSERT_LOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_OWNED); 122#define ATE_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_NOTOWNED); 123 124static devclass_t ate_devclass; 125 126/* ifnet entry points */ 127 128static void ateinit_locked(void *); 129static void atestart_locked(struct ifnet *); 130 131static void ateinit(void *); 132static void atestart(struct ifnet *); 133static void atestop(struct ate_softc *); 134static void atewatchdog(struct ifnet *); 135static int ateioctl(struct ifnet * ifp, u_long, caddr_t); 136 137/* bus entry points */ 138 139static int ate_probe(device_t dev); 140static int ate_attach(device_t dev); 141static int ate_detach(device_t dev); 142static void ate_intr(void *); 143 144/* helper routines */ 145static int ate_activate(device_t dev); 146static void ate_deactivate(device_t dev); 147static int ate_ifmedia_upd(struct ifnet *ifp); 148static void ate_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr); 149static void ate_get_mac(struct ate_softc *sc, u_char *eaddr); 150 151/* 152 * The AT91 family of products has the ethernet called EMAC. However, 153 * it isn't self identifying. It is anticipated that the parent bus 154 * code will take care to only add ate devices where they really are. As 155 * such, we do nothing here to identify the device and just set its name. 156 */ 157static int 158ate_probe(device_t dev) 159{ 160 device_set_desc(dev, "EMAC"); 161 return (0); 162} 163 164static int 165ate_attach(device_t dev) 166{ 167 struct ate_softc *sc = device_get_softc(dev); 168 struct ifnet *ifp = NULL; 169 int err; 170 u_char eaddr[6]; 171 172 sc->dev = dev; 173 err = ate_activate(dev); 174 if (err) 175 goto out; 176 177 /* calling atestop before ifp is set is OK */ 178 atestop(sc); 179 ATE_LOCK_INIT(sc); 180 callout_init_mtx(&sc->tick_ch, &sc->sc_mtx, 0); 181 182 ate_get_mac(sc, eaddr); 183 184 sc->ifp = ifp = if_alloc(IFT_ETHER); 185 if (mii_phy_probe(dev, &sc->miibus, ate_ifmedia_upd, ate_ifmedia_sts)) { 186 device_printf(dev, "Cannot find my PHY.\n"); 187 err = ENXIO; 188 goto out; 189 } 190 191 ifp->if_softc = sc; 192 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 193 ifp->if_mtu = ETHERMTU; 194 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 195 ifp->if_start = atestart; 196 ifp->if_ioctl = ateioctl; 197 ifp->if_watchdog = atewatchdog; 198 ifp->if_init = ateinit; 199 ifp->if_baudrate = 10000000; 200 IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN); 201 ifp->if_snd.ifq_maxlen = IFQ_MAXLEN; 202 IFQ_SET_READY(&ifp->if_snd); 203 ifp->if_timer = 0; 204 ifp->if_linkmib = &sc->mibdata; 205 ifp->if_linkmiblen = sizeof(sc->mibdata); 206 sc->mibdata.dot3Compliance = DOT3COMPLIANCE_COLLS; 207 208 ether_ifattach(ifp, eaddr); 209 210 /* 211 * Activate the interrupt 212 */ 213 err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_NET | INTR_MPSAFE, 214 ate_intr, sc, &sc->intrhand); 215 if (err) { 216 ether_ifdetach(ifp); 217 ATE_LOCK_DESTROY(sc); 218 } 219out:; 220 if (err) 221 ate_deactivate(dev); 222 if (err && ifp) 223 if_free(ifp); 224 return (err); 225} 226 227static int 228ate_detach(device_t dev) 229{ 230 return EBUSY; /* XXX TODO(1) */ 231} 232 233static void 234ate_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 235{ 236 struct ate_softc *sc; 237 238 if (error != 0) 239 return; 240 sc = (struct ate_softc *)arg; 241 sc->rx_desc_phys = segs[0].ds_addr; 242} 243 244/* 245 * Compute the multicast filter for this device using the standard 246 * algorithm. I wonder why this isn't in ether somewhere as a lot 247 * of different MAC chips use this method (or the reverse the bits) 248 * method. 249 */ 250static void 251ate_setmcast(struct ate_softc *sc) 252{ 253 uint32_t index; 254 uint32_t mcaf[2]; 255 u_char *af = (u_char *) mcaf; 256 struct ifmultiaddr *ifma; 257 258 mcaf[0] = 0; 259 mcaf[1] = 0; 260 261 IF_ADDR_LOCK(sc->ifp); 262 TAILQ_FOREACH(ifma, &sc->ifp->if_multiaddrs, ifma_link) { 263 if (ifma->ifma_addr->sa_family != AF_LINK) 264 continue; 265 index = ether_crc32_be(LLADDR((struct sockaddr_dl *) 266 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 267 af[index >> 3] |= 1 << (index & 7); 268 } 269 IF_ADDR_UNLOCK(sc->ifp); 270 271 /* 272 * Write the hash to the hash register. This card can also 273 * accept unicast packets as well as multicast packets using this 274 * register for easier bridging operations, but we don't take 275 * advantage of that. Locks here are to avoid LOR with the 276 * IF_ADDR_LOCK, but might not be strictly necessary. 277 */ 278 ATE_LOCK(sc); 279 WR4(sc, ETH_HSL, mcaf[0]); 280 WR4(sc, ETH_HSH, mcaf[1]); 281 ATE_UNLOCK(sc); 282} 283 284static int 285ate_activate(device_t dev) 286{ 287 struct ate_softc *sc; 288 int rid, err, i; 289 290 sc = device_get_softc(dev); 291 rid = 0; 292 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 293 RF_ACTIVE); 294 if (sc->mem_res == NULL) 295 goto errout; 296 rid = 0; 297 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 298 RF_ACTIVE); 299 if (sc->mem_res == NULL) 300 goto errout; 301 302 /* 303 * Allocate DMA tags and maps 304 */ 305 err = bus_dma_tag_create(NULL, 1, 0, BUS_SPACE_MAXADDR_32BIT, 306 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 1, MCLBYTES, 0, 307 busdma_lock_mutex, &sc->sc_mtx, &sc->mtag); 308 if (err != 0) 309 goto errout; 310 for (i = 0; i < ATE_MAX_TX_BUFFERS; i++) { 311 err = bus_dmamap_create(sc->mtag, 0, &sc->tx_map[i]); 312 if (err != 0) 313 goto errout; 314 } 315 /* 316 * Allocate our Rx buffers. This chip has a rx structure that's filled 317 * in 318 */ 319 320 /* 321 * Allocate DMA tags and maps for RX. 322 */ 323 err = bus_dma_tag_create(NULL, 1, 0, BUS_SPACE_MAXADDR_32BIT, 324 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 1, MCLBYTES, 0, 325 busdma_lock_mutex, &sc->sc_mtx, &sc->rxtag); 326 if (err != 0) 327 goto errout; 328 for (i = 0; i < ATE_MAX_RX_BUFFERS; i++) { 329 err = bus_dmamap_create(sc->rxtag, 0, &sc->rx_map[i]); 330 if (err != 0) 331 goto errout; 332 } 333 334 /* Dma TAG and MAP for the rx descriptors. */ 335 err = bus_dma_tag_create(NULL, sizeof(eth_rx_desc_t), 0, 336 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 337 ATE_MAX_RX_BUFFERS * sizeof(eth_rx_desc_t), 1, 338 ATE_MAX_RX_BUFFERS * sizeof(eth_rx_desc_t), 0, busdma_lock_mutex, 339 &sc->sc_mtx, &sc->rx_desc_tag); 340 if (err != 0) 341 goto errout; 342 if (bus_dmamem_alloc(sc->rx_desc_tag, (void **)&sc->rx_descs, M_WAITOK, 343 &sc->rx_desc_map) != 0) 344 goto errout; 345 if (bus_dmamap_load(sc->rx_desc_tag, sc->rx_desc_map, 346 sc->rx_descs, ATE_MAX_RX_BUFFERS * sizeof(eth_rx_desc_t), 347 ate_getaddr, sc, 0) != 0) 348 goto errout; 349 /* XXX TODO(5) Put this in ateinit_locked? */ 350 for (i = 0; i < ATE_MAX_RX_BUFFERS; i++) { 351 bus_dma_segment_t seg; 352 int nsegs; 353 354 sc->rx_mbuf[i] = m_getcl(M_WAITOK, MT_DATA, M_PKTHDR); 355 sc->rx_mbuf[i]->m_len = sc->rx_mbuf[i]->m_pkthdr.len = 356 MCLBYTES; 357 if (bus_dmamap_load_mbuf_sg(sc->rxtag, sc->rx_map[i], 358 sc->rx_mbuf[i], &seg, &nsegs, 0) != 0) 359 goto errout; 360 /* 361 * For the last buffer, set the wrap bit so the controller 362 * restarts from the first descriptor. 363 */ 364 if (i == ATE_MAX_RX_BUFFERS - 1) 365 seg.ds_addr |= 1 << 1; 366 sc->rx_descs[i].addr = seg.ds_addr; 367 sc->rx_descs[i].status = 0; 368 bus_dmamap_sync(sc->rxtag, sc->rx_map[i], BUS_DMASYNC_PREWRITE); 369 } 370 bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, BUS_DMASYNC_PREWRITE); 371 /* Write the descriptor queue address. */ 372 WR4(sc, ETH_RBQP, sc->rx_desc_phys); 373 return (0); 374errout: 375 ate_deactivate(dev); 376 return (ENOMEM); 377} 378 379static void 380ate_deactivate(device_t dev) 381{ 382 struct ate_softc *sc; 383 384 sc = device_get_softc(dev); 385 /* XXX TODO(2) teardown busdma junk, below from fxp -- customize */ 386#if 0 387 if (sc->fxp_mtag) { 388 for (i = 0; i < FXP_NRFABUFS; i++) { 389 rxp = &sc->fxp_desc.rx_list[i]; 390 if (rxp->rx_mbuf != NULL) { 391 bus_dmamap_sync(sc->fxp_mtag, rxp->rx_map, 392 BUS_DMASYNC_POSTREAD); 393 bus_dmamap_unload(sc->fxp_mtag, rxp->rx_map); 394 m_freem(rxp->rx_mbuf); 395 } 396 bus_dmamap_destroy(sc->fxp_mtag, rxp->rx_map); 397 } 398 bus_dmamap_destroy(sc->fxp_mtag, sc->spare_map); 399 for (i = 0; i < FXP_NTXCB; i++) { 400 txp = &sc->fxp_desc.tx_list[i]; 401 if (txp->tx_mbuf != NULL) { 402 bus_dmamap_sync(sc->fxp_mtag, txp->tx_map, 403 BUS_DMASYNC_POSTWRITE); 404 bus_dmamap_unload(sc->fxp_mtag, txp->tx_map); 405 m_freem(txp->tx_mbuf); 406 } 407 bus_dmamap_destroy(sc->fxp_mtag, txp->tx_map); 408 } 409 bus_dma_tag_destroy(sc->fxp_mtag); 410 } 411 if (sc->fxp_stag) 412 bus_dma_tag_destroy(sc->fxp_stag); 413 if (sc->cbl_tag) 414 bus_dma_tag_destroy(sc->cbl_tag); 415 if (sc->mcs_tag) 416 bus_dma_tag_destroy(sc->mcs_tag); 417#endif 418 if (sc->intrhand) 419 bus_teardown_intr(dev, sc->irq_res, sc->intrhand); 420 sc->intrhand = 0; 421 bus_generic_detach(sc->dev); 422 if (sc->miibus) 423 device_delete_child(sc->dev, sc->miibus); 424 if (sc->mem_res) 425 bus_release_resource(dev, SYS_RES_IOPORT, 426 rman_get_rid(sc->mem_res), sc->mem_res); 427 sc->mem_res = 0; 428 if (sc->irq_res) 429 bus_release_resource(dev, SYS_RES_IRQ, 430 rman_get_rid(sc->irq_res), sc->irq_res); 431 sc->irq_res = 0; 432 return; 433} 434 435/* 436 * Change media according to request. 437 */ 438static int 439ate_ifmedia_upd(struct ifnet *ifp) 440{ 441 struct ate_softc *sc = ifp->if_softc; 442 struct mii_data *mii; 443 444 mii = device_get_softc(sc->miibus); 445 ATE_LOCK(sc); 446 mii_mediachg(mii); 447 ATE_UNLOCK(sc); 448 return (0); 449} 450 451/* 452 * Notify the world which media we're using. 453 */ 454static void 455ate_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 456{ 457 struct ate_softc *sc = ifp->if_softc; 458 struct mii_data *mii; 459 460 mii = device_get_softc(sc->miibus); 461 ATE_LOCK(sc); 462 mii_pollstat(mii); 463 ifmr->ifm_active = mii->mii_media_active; 464 ifmr->ifm_status = mii->mii_media_status; 465 ATE_UNLOCK(sc); 466} 467 468static void 469ate_tick(void *xsc) 470{ 471 struct ate_softc *sc = xsc; 472 struct mii_data *mii; 473 int active; 474 475 /* 476 * The KB920x boot loader tests ETH_SR & ETH_SR_LINK and will ask 477 * the MII if there's a link if this bit is clear. Not sure if we 478 * should do the same thing here or not. 479 */ 480 ATE_ASSERT_LOCKED(sc); 481 if (sc->miibus != NULL) { 482 mii = device_get_softc(sc->miibus); 483 active = mii->mii_media_active; 484 mii_tick(mii); 485 if (mii->mii_media_status & IFM_ACTIVE && 486 active != mii->mii_media_active) { 487 /* 488 * The speed and full/half-duplex state needs 489 * to be reflected in the ETH_CFG register, it 490 * seems. 491 */ 492 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T) 493 WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) & 494 ~ETH_CFG_SPD); 495 else 496 WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) | 497 ETH_CFG_SPD); 498 if (mii->mii_media_active & IFM_FDX) 499 WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) | 500 ETH_CFG_FD); 501 else 502 WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) & 503 ~ETH_CFG_FD); 504 } 505 } 506 507 /* 508 * Update the stats as best we can. When we're done, clear 509 * the status counters and start over. We're supposed to read these 510 * registers often enough that they won't overflow. Hopefully 511 * once a second is often enough. Some don't map well to 512 * the dot3Stats mib, so for those we just count them as general 513 * errors. Stats for iframes, ibutes, oframes and obytes are 514 * collected elsewhere. These registers zero on a read to prevent 515 * races. 516 */ 517 sc->mibdata.dot3StatsAlignmentErrors += RD4(sc, ETH_ALE); 518 sc->mibdata.dot3StatsFCSErrors += RD4(sc, ETH_SEQE); 519 sc->mibdata.dot3StatsSingleCollisionFrames += RD4(sc, ETH_SCOL); 520 sc->mibdata.dot3StatsMultipleCollisionFrames += RD4(sc, ETH_MCOL); 521 sc->mibdata.dot3StatsSQETestErrors += RD4(sc, ETH_SQEE); 522 sc->mibdata.dot3StatsDeferredTransmissions += RD4(sc, ETH_DTE); 523 sc->mibdata.dot3StatsLateCollisions += RD4(sc, ETH_LCOL); 524 sc->mibdata.dot3StatsExcessiveCollisions += RD4(sc, ETH_ECOL); 525 sc->mibdata.dot3StatsCarrierSenseErrors += RD4(sc, ETH_CSE); 526 sc->mibdata.dot3StatsFrameTooLongs += RD4(sc, ETH_ELR); 527 sc->mibdata.dot3StatsInternalMacReceiveErrors += RD4(sc, ETH_DRFC); 528 /* 529 * not sure where to lump these, so count them against the errors 530 * for the interface. 531 */ 532 sc->ifp->if_oerrors += RD4(sc, ETH_CSE) + RD4(sc, ETH_TUE); 533 sc->ifp->if_ierrors += RD4(sc, ETH_CDE) + RD4(sc, ETH_RJB) + 534 RD4(sc, ETH_USF); 535 536 /* 537 * Schedule another timeout one second from now. 538 */ 539 callout_reset(&sc->tick_ch, hz, ate_tick, sc); 540} 541 542static void 543ate_get_mac(struct ate_softc *sc, u_char *eaddr) 544{ 545 uint32_t low, high; 546 547 /* 548 * The KB920x loaders will setup the MAC with an address, if one 549 * is set in the loader. The TSC loader will also set the MAC address 550 * in a similar way. Grab the MAC address from the SA1[HL] registers. 551 */ 552 low = RD4(sc, ETH_SA1L); 553 high = RD4(sc, ETH_SA1H); 554 eaddr[0] = (high >> 8) & 0xff; 555 eaddr[1] = high & 0xff; 556 eaddr[2] = (low >> 24) & 0xff; 557 eaddr[3] = (low >> 16) & 0xff; 558 eaddr[4] = (low >> 8) & 0xff; 559 eaddr[5] = low & 0xff; 560} 561 562static void 563ate_intr(void *xsc) 564{ 565 struct ate_softc *sc = xsc; 566 int status; 567 int i; 568 569 status = RD4(sc, ETH_ISR); 570 if (status == 0) 571 return; 572 printf("IT IS %x\n", RD4(sc, ETH_RSR)); 573 if (status & ETH_ISR_RCOM) { 574 bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, 575 BUS_DMASYNC_POSTREAD); 576 for (i = 0; i < ATE_MAX_RX_BUFFERS; i++) { 577 if (sc->rx_descs[i].addr & ETH_CPU_OWNER) { 578 struct mbuf *mb = sc->rx_mbuf[i]; 579 bus_dma_segment_t seg; 580 int rx_stat = sc->rx_descs[i].status; 581 int nsegs; 582 583 printf("GOT ONE\n"); 584 bus_dmamap_sync(sc->rxtag, 585 sc->rx_map[i], BUS_DMASYNC_POSTREAD); 586 bus_dmamap_unload(sc->rxtag, 587 sc->rx_map[i]); 588 WR4(sc, ETH_RSR, RD4(sc, ETH_RSR)); 589 /* 590 * Allocate a new buffer to replace this one. 591 * if we cannot, then we drop this packet 592 * and keep the old buffer we had. 593 */ 594 sc->rx_mbuf[i] = m_getcl(M_DONTWAIT, MT_DATA, 595 M_PKTHDR); 596 if (!sc->rx_mbuf[i]) { 597 sc->rx_mbuf[i] = mb; 598 sc->rx_descs[i].addr &= ~ETH_CPU_OWNER; 599 bus_dmamap_sync(sc->rx_desc_tag, 600 sc->rx_desc_map, 601 BUS_DMASYNC_PREWRITE); 602 continue; 603 } 604 if (bus_dmamap_load_mbuf_sg(sc->rxtag, 605 sc->rx_map[i], 606 sc->rx_mbuf[i], &seg, &nsegs, 0) != 0) { 607 sc->rx_mbuf[i] = mb; 608 sc->rx_descs[i].addr &= ~ETH_CPU_OWNER; 609 bus_dmamap_sync(sc->rx_desc_tag, 610 sc->rx_desc_map, 611 BUS_DMASYNC_PREWRITE); 612 continue; 613 } 614 mb->m_len = sc->rx_descs[i].status & 615 ETH_LEN_MASK; 616 /* 617 * For the last buffer, set the wrap bit so 618 * the controller restarts from the first 619 * descriptor. 620 */ 621 if (i == ATE_MAX_RX_BUFFERS - 1) 622 seg.ds_addr |= 1 << 1; 623 sc->rx_descs[i].addr = seg.ds_addr; 624 sc->rx_descs[i].status = 0; 625 mb->m_len = rx_stat & ETH_LEN_MASK; 626 (*sc->ifp->if_input)(sc->ifp, mb); 627 break; 628 } 629 } 630 } 631 if (status & ETH_ISR_TCOM) { 632 if (sc->sent_mbuf[0]) 633 m_freem(sc->sent_mbuf[0]); 634 if (sc->sent_mbuf[1]) { 635 if (RD4(sc, ETH_TSR) & ETH_TSR_IDLE) { 636 m_freem(sc->sent_mbuf[1]); 637 sc->txcur = 0; 638 sc->sent_mbuf[0] = sc->sent_mbuf[1] = NULL; 639 } else { 640 sc->sent_mbuf[0] = sc->sent_mbuf[1]; 641 sc->sent_mbuf[1] = NULL; 642 sc->txcur = 1; 643 } 644 } else { 645 sc->sent_mbuf[0] = NULL; 646 sc->txcur = 0; 647 } 648 } 649 if (status & ETH_ISR_RBNA) { 650 /* Workaround Errata #11 */ 651 WR4(sc, ETH_CTL, RD4(sc, ETH_CTL) &~ ETH_CTL_RE); 652 WR4(sc, ETH_CTL, RD4(sc, ETH_CTL) | ETH_CTL_RE); 653 } 654} 655 656/* 657 * Reset and initialize the chip 658 */ 659static void 660ateinit_locked(void *xsc) 661{ 662 struct ate_softc *sc = xsc; 663 struct ifnet *ifp = sc->ifp; 664 665 ATE_ASSERT_LOCKED(sc); 666 667 /* 668 * XXX TODO(3) 669 * we need to turn on the EMAC clock in the pmc. With the 670 * default boot loader, this is already turned on. However, we 671 * need to think about how best to turn it on/off as the interface 672 * is brought up/down, as well as dealing with the mii bus... 673 * 674 * We also need to multiplex the pins correctly. 675 */ 676 677 /* 678 * There are two different ways that the mii bus is connected 679 * to this chip. Select the right one based on a compile-time 680 * option. 681 */ 682#ifdef ATE_USE_RMII 683 WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) | ETH_CFG_RMII); 684#else 685 WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) & ~ETH_CFG_RMII); 686#endif 687 /* 688 * Turn on the multicast hash, and write 0's to it. 689 */ 690 WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) | ETH_CFG_MTI); 691 WR4(sc, ETH_HSH, 0); 692 WR4(sc, ETH_HSL, 0); 693 694 WR4(sc, ETH_CTL, RD4(sc, ETH_CTL) | ETH_CTL_TE | ETH_CTL_RE); 695 WR4(sc, ETH_IER, /*ETH_ISR_RCOM | ETH_ISR_TCOM | ETH_ISR_RBNA*/ 696 0xffffffff); 697 698 /* 699 * Boot loader fills in MAC address. If that's not the case, then 700 * we should set SA1L and SA1H here to the appropriate value. Note: 701 * the byte order is big endian, not little endian, so we have some 702 * swapping to do. Again, if we need it (which I don't think we do). 703 */ 704 705 ate_setmcast(sc); 706 707 /* 708 * Set 'running' flag, and clear output active flag 709 * and attempt to start the output 710 */ 711 ifp->if_drv_flags |= IFF_DRV_RUNNING; 712 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 713 atestart_locked(ifp); 714 715 callout_reset(&sc->tick_ch, hz, ate_tick, sc); 716} 717 718/* 719 * dequeu packets and transmit 720 */ 721static void 722atestart_locked(struct ifnet *ifp) 723{ 724 struct ate_softc *sc = ifp->if_softc; 725 struct mbuf *m, *mdefrag; 726 bus_dma_segment_t segs[1]; 727 int nseg; 728 729 ATE_ASSERT_LOCKED(sc); 730 if (ifp->if_drv_flags & IFF_DRV_OACTIVE) 731 return; 732 733outloop: 734 /* 735 * check to see if there's room to put another packet into the 736 * xmit queue. The EMAC chip has a ping-pong buffer for xmit 737 * packets. We use OACTIVE to indicate "we can stuff more into 738 * our buffers (clear) or not (set)." 739 */ 740 if (!(RD4(sc, ETH_TSR) & ETH_TSR_BNQ)) { 741 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 742 return; 743 } 744 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 745 if (m == 0) { 746 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 747 return; 748 } 749 mdefrag = m_defrag(m, M_DONTWAIT); 750 if (mdefrag == NULL) { 751 m_freem(m); 752 return; 753 } 754 m = mdefrag; 755 756 if (bus_dmamap_load_mbuf_sg(sc->mtag, sc->tx_map[sc->txcur], m, segs, 757 &nseg, 0) != 0) { 758 m_free(m); 759 goto outloop; 760 } 761 bus_dmamap_sync(sc->mtag, sc->tx_map[sc->txcur], BUS_DMASYNC_PREWRITE); 762 sc->sent_mbuf[sc->txcur] = m; 763 sc->txcur++; 764 if (sc->txcur >= ATE_MAX_TX_BUFFERS) 765 sc->txcur = 0; 766 767 /* 768 * tell the hardware to xmit the packet. 769 */ 770 WR4(sc, ETH_TAR, segs[0].ds_addr); 771 WR4(sc, ETH_TCR, segs[0].ds_len); 772 773 /* 774 * Tap off here if there is a bpf listener. 775 */ 776 BPF_MTAP(ifp, m); 777 778 /* 779 * Once we've queued one packet, we'll do the rest via the ISR, 780 * save off a pointer. 781 */ 782 sc->sent_mbuf[1] = m; 783} 784 785static void 786ateinit(void *xsc) 787{ 788 struct ate_softc *sc = xsc; 789 ATE_LOCK(sc); 790 ateinit_locked(sc); 791 ATE_UNLOCK(sc); 792} 793 794static void 795atestart(struct ifnet *ifp) 796{ 797 struct ate_softc *sc = ifp->if_softc; 798 ATE_LOCK(sc); 799 atestart_locked(ifp); 800 ATE_UNLOCK(sc); 801} 802 803/* 804 * Turn off interrupts, and stop the nic. Can be called with sc->ifp NULL 805 * so be careful. 806 */ 807static void 808atestop(struct ate_softc *sc) 809{ 810 struct ifnet *ifp = sc->ifp; 811 812 if (ifp) { 813 ifp->if_timer = 0; 814 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 815 } 816 817 callout_stop(&sc->tick_ch); 818 819 /* 820 * Enable some parts of the MAC that are needed always (like the 821 * MII bus. This turns off the RE and TE bits, which will remain 822 * off until ateinit() is called to turn them on. With RE and TE 823 * turned off, there's no DMA to worry about after this write. 824 */ 825 WR4(sc, ETH_CTL, ETH_CTL_MPE); 826 827 /* 828 * Turn off all the configured options and revert to defaults. 829 */ 830 WR4(sc, ETH_CFG, ETH_CFG_CLK_32); 831 832 /* 833 * Turn off all the interrupts, and ack any pending ones by reading 834 * the ISR. 835 */ 836 WR4(sc, ETH_IDR, 0xffffffff); 837 RD4(sc, ETH_ISR); 838 839 /* 840 * Clear out the Transmit and Receiver Status registers of any 841 * errors they may be reporting 842 */ 843 WR4(sc, ETH_TSR, 0xffffffff); 844 WR4(sc, ETH_RSR, 0xffffffff); 845 846 /* 847 * XXX TODO(8) 848 * need to worry about the busdma resources? Yes, I think we need 849 * to sync and unload them. We may also need to release the mbufs 850 * that are assocaited with RX and TX operations. 851 */ 852 853 /* 854 * XXX we should power down the EMAC if it isn't in use, after 855 * putting it into loopback mode. This saves about 400uA according 856 * to the datasheet. 857 */ 858} 859 860static void 861atewatchdog(struct ifnet *ifp) 862{ 863 struct ate_softc *sc = ifp->if_softc; 864 865 ATE_LOCK(sc); 866 device_printf(sc->dev, "Device timeout\n"); 867 ifp->if_oerrors++; 868 ateinit_locked(sc); 869 ATE_UNLOCK(sc); 870} 871 872static int 873ateioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 874{ 875 struct ate_softc *sc = ifp->if_softc; 876 int error = 0; 877 878 switch (cmd) { 879 case SIOCSIFFLAGS: 880 ATE_LOCK(sc); 881 if ((ifp->if_flags & IFF_UP) == 0 && 882 ifp->if_drv_flags & IFF_DRV_RUNNING) { 883 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 884 atestop(sc); 885 } else { 886 /* reinitialize card on any parameter change */ 887 ateinit_locked(sc); 888 } 889 ATE_UNLOCK(sc); 890 break; 891 892 case SIOCADDMULTI: 893 case SIOCDELMULTI: 894 /* update multicast filter list. */ 895 ate_setmcast(sc); 896 error = 0; 897 break; 898 899 default: 900 error = ether_ioctl(ifp, cmd, data); 901 break; 902 } 903 return (error); 904} 905 906static void 907ate_child_detached(device_t dev, device_t child) 908{ 909 struct ate_softc *sc; 910 911 sc = device_get_softc(dev); 912 if (child == sc->miibus) 913 sc->miibus = NULL; 914} 915 916/* 917 * MII bus support routines. 918 */ 919static int 920ate_miibus_readreg(device_t dev, int phy, int reg) 921{ 922 struct ate_softc *sc; 923 int val; 924 925 /* 926 * XXX if we implement agressive power savings, then we need 927 * XXX to make sure that the clock to the emac is on here 928 */ 929 930 if (phy != 0) 931 return (0xffff); 932 sc = device_get_softc(dev); 933 DELAY(1); /* Hangs w/o this delay really 30.5us atm */ 934 WR4(sc, ETH_MAN, ETH_MAN_REG_RD(phy, reg)); 935 while ((RD4(sc, ETH_SR) & ETH_SR_IDLE) == 0) 936 continue; 937 val = RD4(sc, ETH_MAN) & ETH_MAN_VALUE_MASK; 938 939 return (val); 940} 941 942static void 943ate_miibus_writereg(device_t dev, int phy, int reg, int data) 944{ 945 struct ate_softc *sc; 946 947 /* 948 * XXX if we implement agressive power savings, then we need 949 * XXX to make sure that the clock to the emac is on here 950 */ 951 952 sc = device_get_softc(dev); 953 WR4(sc, ETH_MAN, ETH_MAN_REG_WR(phy, reg, data)); 954 while ((RD4(sc, ETH_SR) & ETH_SR_IDLE) == 0) 955 continue; 956 return; 957} 958 959static device_method_t ate_methods[] = { 960 /* Device interface */ 961 DEVMETHOD(device_probe, ate_probe), 962 DEVMETHOD(device_attach, ate_attach), 963 DEVMETHOD(device_detach, ate_detach), 964 965 /* Bus interface */ 966 DEVMETHOD(bus_child_detached, ate_child_detached), 967 968 /* MII interface */ 969 DEVMETHOD(miibus_readreg, ate_miibus_readreg), 970 DEVMETHOD(miibus_writereg, ate_miibus_writereg), 971 972 { 0, 0 } 973}; 974 975static driver_t ate_driver = { 976 "ate", 977 ate_methods, 978 sizeof(struct ate_softc), 979}; 980 981DRIVER_MODULE(ate, atmelarm, ate_driver, ate_devclass, 0, 0); 982DRIVER_MODULE(miibus, ate, miibus_driver, miibus_devclass, 0, 0); 983MODULE_DEPEND(ate, miibus, 1, 1, 1); 984MODULE_DEPEND(ate, ether, 1, 1, 1); 985