board_bwct.c revision 160363
1/*- 2 * Copyright (c) 1994-1998 Mark Brinicombe. 3 * Copyright (c) 1994 Brini. 4 * All rights reserved. 5 * 6 * This code is derived from software written for Brini by Mark Brinicombe 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Brini. 19 * 4. The name of the company nor the name of the author may be used to 20 * endorse or promote products derived from this software without specific 21 * prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED 24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 27 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 * RiscBSD kernel project 36 * 37 * machdep.c 38 * 39 * Machine dependant functions for kernel setup 40 * 41 * This file needs a lot of work. 42 * 43 * Created : 17/09/94 44 */ 45 46#include "opt_msgbuf.h" 47#include "opt_ddb.h" 48#include "opt_at91.h" 49 50#include <sys/cdefs.h> 51__FBSDID("$FreeBSD: head/sys/arm/at91/kb920x_machdep.c 160363 2006-07-14 22:22:57Z imp $"); 52 53#define _ARM32_BUS_DMA_PRIVATE 54#include <sys/param.h> 55#include <sys/systm.h> 56#include <sys/sysproto.h> 57#include <sys/signalvar.h> 58#include <sys/imgact.h> 59#include <sys/kernel.h> 60#include <sys/ktr.h> 61#include <sys/linker.h> 62#include <sys/lock.h> 63#include <sys/malloc.h> 64#include <sys/mutex.h> 65#include <sys/pcpu.h> 66#include <sys/proc.h> 67#include <sys/ptrace.h> 68#include <sys/cons.h> 69#include <sys/bio.h> 70#include <sys/bus.h> 71#include <sys/buf.h> 72#include <sys/exec.h> 73#include <sys/kdb.h> 74#include <sys/msgbuf.h> 75#include <machine/reg.h> 76#include <machine/cpu.h> 77 78#include <vm/vm.h> 79#include <vm/pmap.h> 80#include <vm/vm.h> 81#include <vm/vm_object.h> 82#include <vm/vm_page.h> 83#include <vm/vm_pager.h> 84#include <vm/vm_map.h> 85#include <vm/vnode_pager.h> 86#include <machine/pmap.h> 87#include <machine/vmparam.h> 88#include <machine/pcb.h> 89#include <machine/undefined.h> 90#include <machine/machdep.h> 91#include <machine/metadata.h> 92#include <machine/armreg.h> 93#include <machine/bus.h> 94#include <sys/reboot.h> 95 96#include <arm/at91/at91rm92reg.h> 97#include <arm/at91/at91_piovar.h> 98#include <arm/at91/at91_pio_rm9200.h> 99 100#define KERNEL_PT_SYS 0 /* Page table for mapping proc0 zero page */ 101#define KERNEL_PT_KERN 1 102#define KERNEL_PT_KERN_NUM 22 103#define KERNEL_PT_AFKERNEL KERNEL_PT_KERN + KERNEL_PT_KERN_NUM /* L2 table for mapping after kernel */ 104#define KERNEL_PT_AFKERNEL_NUM 5 105 106/* this should be evenly divisable by PAGE_SIZE / L2_TABLE_SIZE_REAL (or 4) */ 107#define NUM_KERNEL_PTS (KERNEL_PT_AFKERNEL + KERNEL_PT_AFKERNEL_NUM) 108 109/* Define various stack sizes in pages */ 110#define IRQ_STACK_SIZE 1 111#define ABT_STACK_SIZE 1 112#define UND_STACK_SIZE 1 113 114extern u_int data_abort_handler_address; 115extern u_int prefetch_abort_handler_address; 116extern u_int undefined_handler_address; 117 118struct pv_addr kernel_pt_table[NUM_KERNEL_PTS]; 119 120extern void *_end; 121 122extern int *end; 123 124struct pcpu __pcpu; 125struct pcpu *pcpup = &__pcpu; 126 127/* Physical and virtual addresses for some global pages */ 128 129vm_paddr_t phys_avail[10]; 130vm_paddr_t dump_avail[4]; 131vm_offset_t physical_pages; 132vm_offset_t clean_sva, clean_eva; 133 134struct pv_addr systempage; 135struct pv_addr msgbufpv; 136struct pv_addr irqstack; 137struct pv_addr undstack; 138struct pv_addr abtstack; 139struct pv_addr kernelstack; 140struct pv_addr minidataclean; 141 142static struct trapframe proc0_tf; 143 144/* Static device mappings. */ 145static const struct pmap_devmap kb920x_devmap[] = { 146 /* 147 * Map the on-board devices VA == PA so that we can access them 148 * with the MMU on or off. 149 */ 150 { 151 /* 152 * This at least maps the interrupt controller, the UART 153 * and the timer. Other devices should use newbus to 154 * map their memory anyway. 155 */ 156 0xfff00000, 157 0xfff00000, 158 0x100000, 159 VM_PROT_READ|VM_PROT_WRITE, 160 PTE_NOCACHE, 161 }, 162#if 0 163 { 164 /* 165 * Add the ohci controller, and anything else that might be 166 * on this chip select for a VA/PA mapping. 167 */ 168 AT91RM92_OHCI_BASE, 169 AT91RM92_OHCI_BASE, 170 AT91RM92_OHCI_SIZE, 171 VM_PROT_READ|VM_PROT_WRITE, 172 PTE_NOCACHE, 173 }, 174#endif 175 { 176 0, 177 0, 178 0, 179 0, 180 0, 181 } 182}; 183 184#define SDRAM_START 0xa0000000 185 186#ifdef DDB 187extern vm_offset_t ksym_start, ksym_end; 188#endif 189 190static long 191ramsize(void) 192{ 193 uint32_t *SDRAMC = (uint32_t *)(AT91RM92_BASE + AT91RM92_SDRAMC_BASE); 194 uint32_t cr, mr; 195 int banks, rows, cols, bw; 196 197 cr = SDRAMC[AT91RM92_SDRAMC_CR / 4]; 198 mr = SDRAMC[AT91RM92_SDRAMC_MR / 4]; 199 bw = (mr & AT91RM92_SDRAMC_MR_DBW_16) ? 1 : 2; 200 banks = (cr & AT91RM92_SDRAMC_CR_NB_4) ? 2 : 1; 201 rows = ((cr & AT91RM92_SDRAMC_CR_NR_MASK) >> 2) + 11; 202 cols = (cr & AT91RM92_SDRAMC_CR_NC_MASK) + 8; 203 return (1 << (cols + rows + banks + bw)); 204} 205 206static long 207board_init(void) 208{ 209 /* 210 * Since the USART supprots RS-485 multidrop mode, it allows the 211 * TX pins to float. However, for RS-232 operations, we don't want 212 * these pins to float. Instead, they should be pulled up to avoid 213 * mismatches. Linux does something similar when it configures the 214 * TX lines. This implies that we also allow the RX lines to float 215 * rather than be in the state they are left in by the boot loader. 216 * Since they are input pins, I think that this is the right thing 217 * to do. 218 */ 219 220 /* PIOA's A periph: Turn USART 0 and 2's TX/RX pins */ 221 at91_pio_use_periph_a(AT91RM92_PIOA_BASE, 222 AT91C_PA18_RXD0 | AT91C_PA22_RXD2, 0); 223 at91_pio_use_periph_a(AT91RM92_PIOA_BASE, 224 AT91C_PA17_TXD0 | AT91C_PA23_TXD2, 1); 225 /* PIOA's B periph: Turn USART 3's TX/RX pins */ 226 at91_pio_use_periph_b(AT91RM92_PIOA_BASE, AT91C_PA6_RXD3, 0); 227 at91_pio_use_periph_b(AT91RM92_PIOA_BASE, AT91C_PA5_TXD3, 1); 228#if AT91_TSC 229 /* We're using TC0's A1 and A2 input */ 230 at91_pio_use_periph_b(AT91RM92_PIOA_BASE, 231 AT91C_PA19_TIOA1 | AT91C_PA21_TIOA2, 0); 232#endif 233 /* PIOB's A periph: Turn USART 1's TX/RX pins */ 234 at91_pio_use_periph_a(AT91RM92_PIOB_BASE, AT91C_PB21_RXD1, 0); 235 at91_pio_use_periph_a(AT91RM92_PIOB_BASE, AT91C_PB20_TXD1, 1); 236 237 /* Pin assignment */ 238#if AT91_TSC 239 /* Assert PA24 low -- talk to rubidium */ 240 at91_pio_use_gpio(AT91RM92_PIOA_BASE, AT91C_PIO_PA24); 241 at91_pio_gpio_output(AT91RM92_PIOA_BASE, AT91C_PIO_PA24, 0); 242 at91_pio_gpio_clear(AT91RM92_PIOA_BASE, AT91C_PIO_PA24); 243#endif 244 245 return (ramsize()); 246} 247 248void * 249initarm(void *arg, void *arg2) 250{ 251 struct pv_addr kernel_l1pt; 252 int loop; 253 u_int l1pagetable; 254 vm_offset_t freemempos; 255 vm_offset_t afterkern; 256 int i = 0; 257 uint32_t fake_preload[35]; 258 uint32_t memsize; 259 vm_offset_t lastaddr; 260#ifdef DDB 261 vm_offset_t zstart = 0, zend = 0; 262#endif 263 264 i = 0; 265 266 set_cpufuncs(); 267 268 fake_preload[i++] = MODINFO_NAME; 269 fake_preload[i++] = strlen("elf kernel") + 1; 270 strcpy((char*)&fake_preload[i++], "elf kernel"); 271 i += 2; 272 fake_preload[i++] = MODINFO_TYPE; 273 fake_preload[i++] = strlen("elf kernel") + 1; 274 strcpy((char*)&fake_preload[i++], "elf kernel"); 275 i += 2; 276 fake_preload[i++] = MODINFO_ADDR; 277 fake_preload[i++] = sizeof(vm_offset_t); 278 fake_preload[i++] = KERNBASE; 279 fake_preload[i++] = MODINFO_SIZE; 280 fake_preload[i++] = sizeof(uint32_t); 281 fake_preload[i++] = (uint32_t)&end - KERNBASE; 282#ifdef DDB 283 if (*(uint32_t *)KERNVIRTADDR == MAGIC_TRAMP_NUMBER) { 284 fake_preload[i++] = MODINFO_METADATA|MODINFOMD_SSYM; 285 fake_preload[i++] = sizeof(vm_offset_t); 286 fake_preload[i++] = *(uint32_t *)(KERNVIRTADDR + 4); 287 fake_preload[i++] = MODINFO_METADATA|MODINFOMD_ESYM; 288 fake_preload[i++] = sizeof(vm_offset_t); 289 fake_preload[i++] = *(uint32_t *)(KERNVIRTADDR + 8); 290 lastaddr = *(uint32_t *)(KERNVIRTADDR + 8); 291 zend = lastaddr; 292 zstart = *(uint32_t *)(KERNVIRTADDR + 4); 293 ksym_start = zstart; 294 ksym_end = zend; 295 } else 296#endif 297 lastaddr = (vm_offset_t)&end; 298 299 fake_preload[i++] = 0; 300 fake_preload[i] = 0; 301 preload_metadata = (void *)fake_preload; 302 303 304 pcpu_init(pcpup, 0, sizeof(struct pcpu)); 305 PCPU_SET(curthread, &thread0); 306 307#define KERNEL_TEXT_BASE (KERNBASE) 308 freemempos = (lastaddr + PAGE_MASK) & ~PAGE_MASK; 309 /* Define a macro to simplify memory allocation */ 310#define valloc_pages(var, np) \ 311 alloc_pages((var).pv_va, (np)); \ 312 (var).pv_pa = (var).pv_va + (KERNPHYSADDR - KERNVIRTADDR); 313 314#define alloc_pages(var, np) \ 315 (var) = freemempos; \ 316 freemempos += (np * PAGE_SIZE); \ 317 memset((char *)(var), 0, ((np) * PAGE_SIZE)); 318 319 while (((freemempos - L1_TABLE_SIZE) & (L1_TABLE_SIZE - 1)) != 0) 320 freemempos += PAGE_SIZE; 321 valloc_pages(kernel_l1pt, L1_TABLE_SIZE / PAGE_SIZE); 322 for (loop = 0; loop < NUM_KERNEL_PTS; ++loop) { 323 if (!(loop % (PAGE_SIZE / L2_TABLE_SIZE_REAL))) { 324 valloc_pages(kernel_pt_table[loop], 325 L2_TABLE_SIZE / PAGE_SIZE); 326 } else { 327 kernel_pt_table[loop].pv_va = freemempos - 328 (loop % (PAGE_SIZE / L2_TABLE_SIZE_REAL)) * 329 L2_TABLE_SIZE_REAL; 330 kernel_pt_table[loop].pv_pa = 331 kernel_pt_table[loop].pv_va - KERNVIRTADDR + 332 KERNPHYSADDR; 333 } 334 i++; 335 } 336 /* 337 * Allocate a page for the system page mapped to V0x00000000 338 * This page will just contain the system vectors and can be 339 * shared by all processes. 340 */ 341 valloc_pages(systempage, 1); 342 343 /* Allocate stacks for all modes */ 344 valloc_pages(irqstack, IRQ_STACK_SIZE); 345 valloc_pages(abtstack, ABT_STACK_SIZE); 346 valloc_pages(undstack, UND_STACK_SIZE); 347 valloc_pages(kernelstack, KSTACK_PAGES); 348 alloc_pages(minidataclean.pv_pa, 1); 349 valloc_pages(msgbufpv, round_page(MSGBUF_SIZE) / PAGE_SIZE); 350 /* 351 * Now we start construction of the L1 page table 352 * We start by mapping the L2 page tables into the L1. 353 * This means that we can replace L1 mappings later on if necessary 354 */ 355 l1pagetable = kernel_l1pt.pv_va; 356 357 /* Map the L2 pages tables in the L1 page table */ 358 pmap_link_l2pt(l1pagetable, ARM_VECTORS_LOW, 359 &kernel_pt_table[KERNEL_PT_SYS]); 360 for (i = 0; i < KERNEL_PT_KERN_NUM; i++) 361 pmap_link_l2pt(l1pagetable, KERNBASE + i * 0x100000, 362 &kernel_pt_table[KERNEL_PT_KERN + i]); 363 pmap_map_chunk(l1pagetable, KERNBASE, KERNPHYSADDR, 364 (((uint32_t)(lastaddr) - KERNBASE) + PAGE_SIZE) & ~(PAGE_SIZE - 1), 365 VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE); 366 afterkern = round_page((lastaddr + L1_S_SIZE) & ~(L1_S_SIZE 367 - 1)); 368 for (i = 0; i < KERNEL_PT_AFKERNEL_NUM; i++) { 369 pmap_link_l2pt(l1pagetable, afterkern + i * 0x00100000, 370 &kernel_pt_table[KERNEL_PT_AFKERNEL + i]); 371 } 372 pmap_map_entry(l1pagetable, afterkern, minidataclean.pv_pa, 373 VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE); 374 375 376 /* Map the vector page. */ 377 pmap_map_entry(l1pagetable, ARM_VECTORS_LOW, systempage.pv_pa, 378 VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE); 379 /* Map the stack pages */ 380 pmap_map_chunk(l1pagetable, irqstack.pv_va, irqstack.pv_pa, 381 IRQ_STACK_SIZE * PAGE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE); 382 pmap_map_chunk(l1pagetable, abtstack.pv_va, abtstack.pv_pa, 383 ABT_STACK_SIZE * PAGE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE); 384 pmap_map_chunk(l1pagetable, undstack.pv_va, undstack.pv_pa, 385 UND_STACK_SIZE * PAGE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE); 386 pmap_map_chunk(l1pagetable, kernelstack.pv_va, kernelstack.pv_pa, 387 KSTACK_PAGES * PAGE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE); 388 389 pmap_map_chunk(l1pagetable, kernel_l1pt.pv_va, kernel_l1pt.pv_pa, 390 L1_TABLE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_PAGETABLE); 391 pmap_map_chunk(l1pagetable, msgbufpv.pv_va, msgbufpv.pv_pa, 392 MSGBUF_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE); 393 394 395 for (loop = 0; loop < NUM_KERNEL_PTS; ++loop) { 396 pmap_map_chunk(l1pagetable, kernel_pt_table[loop].pv_va, 397 kernel_pt_table[loop].pv_pa, L2_TABLE_SIZE, 398 VM_PROT_READ|VM_PROT_WRITE, PTE_PAGETABLE); 399 } 400 401 pmap_devmap_bootstrap(l1pagetable, kb920x_devmap); 402 cpu_domains((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | DOMAIN_CLIENT); 403 setttb(kernel_l1pt.pv_pa); 404 cpu_tlb_flushID(); 405 cpu_domains(DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)); 406 cninit(); 407 memsize = board_init(); 408 physmem = memsize / PAGE_SIZE; 409 410 /* 411 * Pages were allocated during the secondary bootstrap for the 412 * stacks for different CPU modes. 413 * We must now set the r13 registers in the different CPU modes to 414 * point to these stacks. 415 * Since the ARM stacks use STMFD etc. we must set r13 to the top end 416 * of the stack memory. 417 */ 418 419 cpu_control(CPU_CONTROL_MMU_ENABLE, CPU_CONTROL_MMU_ENABLE); 420 set_stackptr(PSR_IRQ32_MODE, 421 irqstack.pv_va + IRQ_STACK_SIZE * PAGE_SIZE); 422 set_stackptr(PSR_ABT32_MODE, 423 abtstack.pv_va + ABT_STACK_SIZE * PAGE_SIZE); 424 set_stackptr(PSR_UND32_MODE, 425 undstack.pv_va + UND_STACK_SIZE * PAGE_SIZE); 426 427 428 429 /* 430 * We must now clean the cache again.... 431 * Cleaning may be done by reading new data to displace any 432 * dirty data in the cache. This will have happened in setttb() 433 * but since we are boot strapping the addresses used for the read 434 * may have just been remapped and thus the cache could be out 435 * of sync. A re-clean after the switch will cure this. 436 * After booting there are no gross reloations of the kernel thus 437 * this problem will not occur after initarm(). 438 */ 439 cpu_idcache_wbinv_all(); 440 441 /* Set stack for exception handlers */ 442 443 data_abort_handler_address = (u_int)data_abort_handler; 444 prefetch_abort_handler_address = (u_int)prefetch_abort_handler; 445 undefined_handler_address = (u_int)undefinedinstruction_bounce; 446 undefined_init(); 447 448 proc_linkup(&proc0, &ksegrp0, &thread0); 449 thread0.td_kstack = kernelstack.pv_va; 450 thread0.td_pcb = (struct pcb *) 451 (thread0.td_kstack + KSTACK_PAGES * PAGE_SIZE) - 1; 452 thread0.td_pcb->pcb_flags = 0; 453 thread0.td_frame = &proc0_tf; 454 pcpup->pc_curpcb = thread0.td_pcb; 455 456 arm_vector_init(ARM_VECTORS_LOW, ARM_VEC_ALL); 457 458 pmap_curmaxkvaddr = afterkern + 0x100000 * (KERNEL_PT_KERN_NUM - 1); 459 pmap_bootstrap(freemempos, 460 KERNVIRTADDR + 3 * memsize, 461 &kernel_l1pt); 462 msgbufp = (void*)msgbufpv.pv_va; 463 msgbufinit(msgbufp, MSGBUF_SIZE); 464 mutex_init(); 465 466 i = 0; 467 dump_avail[0] = KERNPHYSADDR; 468 dump_avail[1] = KERNPHYSADDR + memsize; 469 dump_avail[2] = 0; 470 dump_avail[3] = 0; 471 472 phys_avail[0] = freemempos - KERNVIRTADDR + KERNPHYSADDR; 473 phys_avail[1] = KERNPHYSADDR + memsize; 474 phys_avail[2] = 0; 475 phys_avail[3] = 0; 476 /* Do basic tuning, hz etc */ 477 init_param1(); 478 init_param2(physmem); 479 avail_end = KERNPHYSADDR + memsize - 1; 480 kdb_init(); 481 return ((void *)(kernelstack.pv_va + USPACE_SVC_STACK_TOP - 482 sizeof(struct pcb))); 483} 484