at91sam9g45reg.h revision 272213
11556Srgrimes/*- 21556Srgrimes * Copyright (c) 2009 Sylvestre Gallon. All rights reserved. 31556Srgrimes * Copyright (c) 2010 Greg Ansley. All rights reserved. 41556Srgrimes * Copyright (c) 2012 Andrew Turner. All rights reserved. 51556Srgrimes * 61556Srgrimes * Redistribution and use in source and binary forms, with or without 71556Srgrimes * modification, are permitted provided that the following conditions 81556Srgrimes * are met: 91556Srgrimes * 1. Redistributions of source code must retain the above copyright 101556Srgrimes * notice, this list of conditions and the following disclaimer. 111556Srgrimes * 2. Redistributions in binary form must reproduce the above copyright 121556Srgrimes * notice, this list of conditions and the following disclaimer in the 131556Srgrimes * documentation and/or other materials provided with the distribution. 141556Srgrimes * 151556Srgrimes * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 161556Srgrimes * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 171556Srgrimes * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 181556Srgrimes * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 191556Srgrimes * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 201556Srgrimes * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 211556Srgrimes * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 221556Srgrimes * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 231556Srgrimes * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 241556Srgrimes * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 251556Srgrimes * SUCH DAMAGE. 261556Srgrimes */ 271556Srgrimes 281556Srgrimes/* $FreeBSD: head/sys/arm/at91/at91sam9g45reg.h 272213 2014-09-27 14:39:00Z kevlo $ */ 291556Srgrimes 301556Srgrimes#ifndef AT91SAM9G45REG_H_ 311556Srgrimes#define AT91SAM9G45REG_H_ 321556Srgrimes 331556Srgrimes/* Chip Specific limits */ 341556Srgrimes#define SAM9G45_PLL_A_MIN_IN_FREQ 2000000 /* 2 Mhz */ 353044Sdg#define SAM9G45_PLL_A_MAX_IN_FREQ 32000000 /* 32 Mhz */ 3631098Sbde#define SAM9G45_PLL_A_MIN_OUT_FREQ 400000000 /* 400 Mhz */ 371556Srgrimes#define SAM9G45_PLL_A_MAX_OUT_FREQ 800000000 /* 800 Mhz */ 381556Srgrimes#define SAM9G45_PLL_A_MUL_SHIFT 16 391556Srgrimes#define SAM9G45_PLL_A_MUL_MASK 0xFF 4020425Ssteve#define SAM9G45_PLL_A_DIV_SHIFT 0 411556Srgrimes#define SAM9G45_PLL_A_DIV_MASK 0xFF 421556Srgrimes 4317987Speter/* 4417987Speter * Memory map, from datasheet : 4517987Speter * 0x00000000 - 0x0ffffffff : Internal Memories 4617987Speter * 0x10000000 - 0x1ffffffff : Chip Select 0 471556Srgrimes * 0x20000000 - 0x2ffffffff : Chip Select 1 481556Srgrimes * 0x30000000 - 0x3ffffffff : Chip Select 2 491556Srgrimes * 0x40000000 - 0x4ffffffff : Chip Select 3 501556Srgrimes * 0x50000000 - 0x5ffffffff : Chip Select 4 511556Srgrimes * 0x60000000 - 0x6ffffffff : Chip Select 5 5217987Speter * 0x70000000 - 0x7ffffffff : DDR SDRC 0 531556Srgrimes * 0x80000000 - 0xeffffffff : Undefined (Abort) 541556Srgrimes * 0xf0000000 - 0xfffffffff : Peripherals 551556Srgrimes */ 561556Srgrimes 571556Srgrimes#define AT91_CHIPSELECT_0 0x10000000 581556Srgrimes#define AT91_CHIPSELECT_1 0x20000000 591556Srgrimes#define AT91_CHIPSELECT_2 0x30000000 601556Srgrimes#define AT91_CHIPSELECT_3 0x40000000 611556Srgrimes#define AT91_CHIPSELECT_4 0x50000000 621556Srgrimes#define AT91_CHIPSELECT_5 0x60000000 631556Srgrimes 641556Srgrimes 651556Srgrimes#define AT91SAM9G45_EMAC_BASE 0xffbc000 661556Srgrimes#define AT91SAM9G45_EMAC_SIZE 0x4000 671556Srgrimes 681556Srgrimes#define AT91SAM9G45_RSTC_BASE 0xffffd00 691556Srgrimes#define AT91SAM9G45_RSTC_SIZE 0x10 701556Srgrimes 711556Srgrimes/* USART*/ 721556Srgrimes 731556Srgrimes#define AT91SAM9G45_USART_SIZE 0x4000 741556Srgrimes#define AT91SAM9G45_USART0_BASE 0xff8c000 7517987Speter#define AT91SAM9G45_USART0_SIZE AT91SAM9G45_USART_SIZE 761556Srgrimes#define AT91SAM9G45_USART1_BASE 0xff90000 7720902Ssteve#define AT91SAM9G45_USART1_SIZE AT91SAM9G45_USART_SIZE 7820902Ssteve#define AT91SAM9G45_USART2_BASE 0xff94000 7920902Ssteve#define AT91SAM9G45_USART2_SIZE AT91SAM9G45_USART_SIZE 801556Srgrimes#define AT91SAM9G45_USART3_BASE 0xff98000 8117987Speter#define AT91SAM9G45_USART3_SIZE AT91SAM9G45_USART_SIZE 8217987Speter 8320902Ssteve/*TC*/ 841556Srgrimes#define AT91SAM9G45_TC0_BASE 0xff7c000 8520902Ssteve#define AT91SAM9G45_TC0_SIZE 0x4000 8620902Ssteve#define AT91SAM9G45_TC0C0_BASE 0xff7c000 8720902Ssteve#define AT91SAM9G45_TC0C1_BASE 0xff7c040 8820902Ssteve#define AT91SAM9G45_TC0C2_BASE 0xff7c080 8920902Ssteve 9020902Ssteve#define AT91SAM9G45_TC1_BASE 0xffd4000 9120902Ssteve#define AT91SAM9G45_TC1_SIZE 0x4000 9220902Ssteve#define AT91SAM9G45_TC1C0_BASE 0xffd4000 9320902Ssteve#define AT91SAM9G45_TC1C1_BASE 0xffd4040 9420902Ssteve#define AT91SAM9G45_TC1C2_BASE 0xffd4080 9520902Ssteve 9620902Ssteve/*SPI*/ 9720902Ssteve 9820902Ssteve#define AT91SAM9G45_SPI0_BASE 0xffa48000 9920902Ssteve#define AT91SAM9G45_SPI0_SIZE 0x4000 10020902Ssteve 10120902Ssteve#define AT91SAM9G45_SPI1_BASE 0xffa8000 10220902Ssteve#define AT91SAM9G45_SPI1_SIZE 0x4000 10320902Ssteve 10420902Ssteve/* System Registers */ 10520902Ssteve#define AT91SAM9G45_SYS_BASE 0xffff000 10620902Ssteve#define AT91SAM9G45_SYS_SIZE 0x1000 10720902Ssteve 10820902Ssteve#define AT91SAM9G45_MATRIX_BASE 0xfffea00 10920902Ssteve#define AT91SAM9G45_MATRIX_SIZE 0x200 11020902Ssteve 11120902Ssteve#define AT91SAM9G45_DBGU_BASE 0xfffee00 11220902Ssteve#define AT91SAM9G45_DBGU_SIZE 0x200 11320902Ssteve 11420902Ssteve/* 11520902Ssteve * PIO 11620902Ssteve */ 11720902Ssteve#define AT91SAM9G45_PIOA_BASE 0xffff200 11820902Ssteve#define AT91SAM9G45_PIOA_SIZE 0x200 11920902Ssteve#define AT91SAM9G45_PIOB_BASE 0xffff400 12020902Ssteve#define AT91SAM9G45_PIOB_SIZE 0x200 12120902Ssteve#define AT91SAM9G45_PIOC_BASE 0xffff600 12220902Ssteve#define AT91SAM9G45_PIOC_SIZE 0x200 12320902Ssteve#define AT91SAM9G45_PIOD_BASE 0xffff800 12420902Ssteve#define AT91SAM9G45_PIOD_SIZE 0x200 12520902Ssteve#define AT91SAM9G45_PIOE_BASE 0xffffa00 12620902Ssteve#define AT91SAM9G45_PIOE_SIZE 0x200 12720902Ssteve 12820902Ssteve#define AT91SAM9G45_PMC_BASE 0xffffc00 12920902Ssteve#define AT91SAM9G45_PMC_SIZE 0x100 13020902Ssteve 1311556Srgrimes/* IRQs : */ 1321556Srgrimes/* 13317987Speter * 0: AIC 13417987Speter * 1: System peripheral (System timer, RTC, DBGU) 13517987Speter * 2: PIO Controller A 13620425Ssteve * 3: PIO Controller B 13717987Speter * 4: PIO Controller C 1381556Srgrimes * 5: PIO Controller D/E 1391556Srgrimes * 6: TRNG 1401556Srgrimes * 7: USART 0 1411556Srgrimes * 8: USART 1 14220902Ssteve * 9: USART 2 1431556Srgrimes * 10: USART 3 14420902Ssteve * 11: Multimedia Card interface 0 14520902Ssteve * 12: Two-wire interface 0 1461556Srgrimes * 13: Two-wire interface 1 1471556Srgrimes * 14: SPI 0 1481556Srgrimes * 15: SPI 1 14920902Ssteve * 16: SSC 0 15020902Ssteve * 17: SSC 1 15120902Ssteve * 18: Timer Counter 0, 1, 2, 3, 4, 5 15220902Ssteve * 19: PWM 15320902Ssteve * 20: Touch Screen ADC 15420902Ssteve * 21: DMA 15520902Ssteve * 22: USB Host port 15620902Ssteve * 23: LCD 15720902Ssteve * 24: AC97 15820902Ssteve * 25: EMAC 15920902Ssteve * 26: Image Sensor Interface 16020902Ssteve * 27: USB Device High Speed 16120902Ssteve * 28: - 16220902Ssteve * 29: Multimedia Card interface 1 16320902Ssteve * 30: Reserved 16420902Ssteve * 31: AIC 16520902Ssteve */ 16620902Ssteve 16720902Ssteve#define AT91SAM9G45_IRQ_SYSTEM 1 1681556Srgrimes#define AT91SAM9G45_IRQ_PIOA 2 1691556Srgrimes#define AT91SAM9G45_IRQ_PIOB 3 1701556Srgrimes#define AT91SAM9G45_IRQ_PIOC 4 1711556Srgrimes#define AT91SAM9G45_IRQ_PIODE 5 1721556Srgrimes#define AT91SAM9G45_IRQ_TRNG 6 1731556Srgrimes#define AT91SAM9G45_IRQ_USART0 7 1741556Srgrimes#define AT91SAM9G45_IRQ_USART1 8 1751556Srgrimes#define AT91SAM9G45_IRQ_USART2 9 1761556Srgrimes#define AT91SAM9G45_IRQ_USART3 10 17720902Ssteve#define AT91SAM9G45_IRQ_HSMCI0 11 1781556Srgrimes#define AT91SAM9G45_IRQ_TWI0 12 1791556Srgrimes#define AT91SAM9G45_IRQ_TWI1 13 1801556Srgrimes#define AT91SAM9G45_IRQ_SPI0 14 1811556Srgrimes#define AT91SAM9G45_IRQ_SPI1 15 1821556Srgrimes#define AT91SAM9G45_IRQ_SSC0 16 1831556Srgrimes#define AT91SAM9G45_IRQ_SSC1 17 1841556Srgrimes#define AT91SAM9G45_IRQ_TC0_TC5 18 1851556Srgrimes#define AT91SAM9G45_IRQ_PWM 19 1861556Srgrimes#define AT91SAM9G45_IRQ_TSADCC 20 18720902Ssteve#define AT91SAM9G45_IRQ_DMA 21 18820902Ssteve#define AT91SAM9G45_IRQ_UHP 22 1891556Srgrimes#define AT91SAM9G45_IRQ_LCDC 23 1901556Srgrimes#define AT91SAM9G45_IRQ_AC97C 24 19120902Ssteve#define AT91SAM9G45_IRQ_EMAC 25 1921556Srgrimes#define AT91SAM9G45_IRQ_ISI 26 1931556Srgrimes#define AT91SAM9G45_IRQ_UDPHS 27 1941556Srgrimes/* Reserved 28 */ 1951556Srgrimes#define AT91SAM9G45_IRQ_HSMCI1 29 1961556Srgrimes/* Reserved 30 */ 1971556Srgrimes#define AT91SAM9G45_IRQ_AICBASE 31 1981556Srgrimes 1991556Srgrimes/* Alias */ 2001556Srgrimes#define AT91SAM9G45_IRQ_DBGU AT91SAM9G45_IRQ_SYSTEM 2011556Srgrimes#define AT91SAM9G45_IRQ_PMC AT91SAM9G45_IRQ_SYSTEM 2021556Srgrimes#define AT91SAM9G45_IRQ_WDT AT91SAM9G45_IRQ_SYSTEM 2031556Srgrimes#define AT91SAM9G45_IRQ_PIT AT91SAM9G45_IRQ_SYSTEM 2041556Srgrimes#define AT91SAM9G45_IRQ_RSTC AT91SAM9G45_IRQ_SYSTEM 2051556Srgrimes#define AT91SAM9G45_IRQ_PIOD AT91SAM9G45_IRQ_PIODE 2061556Srgrimes#define AT91SAM9G45_IRQ_PIOE AT91SAM9G45_IRQ_PIODE 2071556Srgrimes#define AT91SAM9G45_IRQ_OHCI AT91SAM9G45_IRQ_UHP 20831098Sbde#define AT91SAM9G45_IRQ_TC0 AT91SAM9G45_IRQ_TC0_TC5 20920425Ssteve#define AT91SAM9G45_IRQ_TC1 AT91SAM9G45_IRQ_TC0_TC5 21017987Speter#define AT91SAM9G45_IRQ_TC2 AT91SAM9G45_IRQ_TC0_TC5 21117987Speter#define AT91SAM9G45_IRQ_TC3 AT91SAM9G45_IRQ_TC0_TC5 2121556Srgrimes#define AT91SAM9G45_IRQ_TC4 AT91SAM9G45_IRQ_TC0_TC5 21331098Sbde#define AT91SAM9G45_IRQ_TC5 AT91SAM9G45_IRQ_TC0_TC5 2141556Srgrimes#define AT91SAM9G45_IRQ_NAND (-1) 2151556Srgrimes 2161556Srgrimes#define AT91SAM9G45_AIC_BASE 0xffff000 2171556Srgrimes#define AT91SAM9G45_AIC_SIZE 0x200 2181556Srgrimes 2191556Srgrimes/* Timer */ 2201556Srgrimes 2211556Srgrimes#define AT91SAM9G45_WDT_BASE 0xffffd40 2221556Srgrimes#define AT91SAM9G45_WDT_SIZE 0x10 2231556Srgrimes 2241556Srgrimes#define AT91SAM9G45_PIT_BASE 0xffffd30 2251556Srgrimes#define AT91SAM9G45_PIT_SIZE 0x10 2261556Srgrimes 2271556Srgrimes#define AT91SAM9G45_SMC_BASE 0xfffe800 2281556Srgrimes#define AT91SAM9G45_SMC_SIZE 0x200 2291556Srgrimes 2301556Srgrimes#define AT91SAM9G45_HSMCI0_BASE 0xff80000 2311556Srgrimes#define AT91SAM9G45_HSMCI0_SIZE 0x4000 2321556Srgrimes 2331556Srgrimes#define AT91SAM9G45_HSMCI1_BASE 0xffd0000 2341556Srgrimes#define AT91SAM9G45_HSMCI1_SIZE 0x4000 2351556Srgrimes 2361556Srgrimes#define AT91SAM9G45_TWI0_BASE 0xff84000 2371556Srgrimes#define AT91SAM9G45_TWI0_SIZE 0x4000 2381556Srgrimes#define AT91SAM9G45_TWI1_BASE 0xff88000 2391556Srgrimes#define AT91SAM9G45_TWI1_SIZE 0x4000 2401556Srgrimes 2411556Srgrimes/* XXX Needs to be carfully coordinated with 2421556Srgrimes * other * soc's so phyical and vm address 2431556Srgrimes * mapping are unique. XXX 2441556Srgrimes */ 2451556Srgrimes#define AT91SAM9G45_OHCI_VA_BASE 0xdfb00000 2461556Srgrimes#define AT91SAM9G45_OHCI_BASE 0x00700000 2471556Srgrimes#define AT91SAM9G45_OHCI_SIZE 0x00100000 2481556Srgrimes 2491556Srgrimes#define AT91SAM9G45_NAND_VA_BASE 0xe0000000 2501556Srgrimes#define AT91SAM9G45_NAND_BASE 0x40000000 25117987Speter#define AT91SAM9G45_NAND_SIZE 0x10000000 25220902Ssteve 2538855Srgrimes 2548855Srgrimes/* DDRSDRC */ 2558855Srgrimes#define AT91SAM9G45_DDRSDRC1_BASE 0xfffea00 2561556Srgrimes#define AT91SAM9G45_DDRSDRC0_BASE 0xfffe600 25717987Speter#define AT91SAM9G45_DDRSDRC_MR 0x00 25817987Speter#define AT91SAM9G45_DDRSDRC_TR 0x04 25917987Speter#define AT91SAM9G45_DDRSDRC_CR 0x08 26017987Speter#define AT91SAM9G45_DDRSDRC_CR_NC_8 0x0 26117987Speter#define AT91SAM9G45_DDRSDRC_CR_NC_9 0x1 26217987Speter#define AT91SAM9G45_DDRSDRC_CR_NC_10 0x2 26331098Sbde#define AT91SAM9G45_DDRSDRC_CR_NC_11 0x3 26417987Speter#define AT91SAM9G45_DDRSDRC_CR_NC_MASK 0x00000003 2651556Srgrimes#define AT91SAM9G45_DDRSDRC_CR_NR_11 0x0 2668855Srgrimes#define AT91SAM9G45_DDRSDRC_CR_NR_12 0x4 2671556Srgrimes#define AT91SAM9G45_DDRSDRC_CR_NR_13 0x8 2681556Srgrimes#define AT91SAM9G45_DDRSDRC_CR_NR_14 0xc 2691556Srgrimes#define AT91SAM9G45_DDRSDRC_CR_NR_MASK 0x0000000c 2701556Srgrimes#define AT91SAM9G45_DDRSDRC_TPR0 0x0c 2711556Srgrimes#define AT91SAM9G45_DDRSDRC_TPR1 0x10 2721556Srgrimes#define AT91SAM9G45_DDRSDRC_TPR2 0x14 2731556Srgrimes/* Reserved 0x18 */ 2741556Srgrimes#define AT91SAM9G45_DDRSDRC_LPR 0x1c 2751556Srgrimes#define AT91SAM9G45_DDRSDRC_MDR 0x20 27631098Sbde#define AT91SAM9G45_DDRSDRC_MDR_SDR 0x0 2771556Srgrimes#define AT91SAM9G45_DDRSDRC_MDR_LPSDR 0x1 2781556Srgrimes#define AT91SAM9G45_DDRSDRC_MDR_LPDDR1 0x3 2791556Srgrimes#define AT91SAM9G45_DDRSDRC_MDR_DDR2 0x6 2801556Srgrimes#define AT91SAM9G45_DDRSDRC_MDR_MASK 0x00000007 2811556Srgrimes#define AT91SAM9G45_DDRSDRC_MDR_DBW_16 0x10 2821556Srgrimes#define AT91SAM9G45_DDRSDRC_DLL 0x24 28331098Sbde#define AT91SAM9G45_DDRSDRC_HSR 0x2c 28430969Sache#define AT91SAM9G45_DDRSDRC_DELAY1R 0x40 28531098Sbde#define AT91SAM9G45_DDRSDRC_DELAY2R 0x44 28631098Sbde#define AT91SAM9G45_DDRSDRC_DELAY3R 0x48 28730969Sache#define AT91SAM9G45_DDRSDRC_DELAY4R 0x4c 2881556Srgrimes/* Reserved 0x50 - 0xe0 */ 2891556Srgrimes#define AT91SAM9G45_DDRSDRC_WPMR 0xe4 29020902Ssteve#define AT91SAM9G45_DDRSDRC_WPSR 0xe8 2911556Srgrimes 2921556Srgrimes#endif /* AT91SAM9G45REG_H_*/ 2931556Srgrimes 29417987Speter