at91sam9g20reg.h revision 234923
1/*- 2 * Copyright (c) 2009 Sylvestre Gallon. All rights reserved. 3 * Copyright (c) 2010 Greg Ansley. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27/* $FreeBSD: head/sys/arm/at91/at91sam9g20reg.h 234923 2012-05-02 09:19:42Z imp $ */ 28 29#ifndef AT91SAM9G20REG_H_ 30#define AT91SAM9G20REG_H_ 31 32#ifndef AT91SAM9G20_MASTER_CLOCK 33#define AT91SAM9G20_MASTER_CLOCK ((18432000 * 43)/6) 34#endif 35 36/* Chip Specific limits */ 37#define SAM9G20_PLL_A_MIN_IN_FREQ 2000000 /* 2 Mhz */ 38#define SAM9G20_PLL_A_MAX_IN_FREQ 32000000 /* 32 Mhz */ 39#define SAM9G20_PLL_A_MIN_OUT_FREQ 400000000 /* 400 Mhz */ 40#define SAM9G20_PLL_A_MAX_OUT_FREQ 800000000 /* 800 Mhz */ 41#define SAM9G20_PLL_A_MUL_SHIFT 16 42#define SAM9G20_PLL_A_MUL_MASK 0xFF 43#define SAM9G20_PLL_A_DIV_SHIFT 0 44#define SAM9G20_PLL_A_DIV_MASK 0xFF 45 46#define SAM9G20_PLL_B_MIN_IN_FREQ 2000000 /* 2 Mhz */ 47#define SAM9G20_PLL_B_MAX_IN_FREQ 32000000 /* 32 Mhz */ 48#define SAM9G20_PLL_B_MIN_OUT_FREQ 30000000 /* 30 Mhz */ 49#define SAM9G20_PLL_B_MAX_OUT_FREQ 100000000 /* 100 Mhz */ 50#define SAM9G20_PLL_B_MUL_SHIFT 16 51#define SAM9G20_PLL_B_MUL_MASK 0x3F 52#define SAM9G20_PLL_B_DIV_SHIFT 0 53#define SAM9G20_PLL_B_DIV_MASK 0xFF 54 55/* 56 * Memory map, from datasheet : 57 * 0x00000000 - 0x0ffffffff : Internal Memories 58 * 0x10000000 - 0x1ffffffff : Chip Select 0 59 * 0x20000000 - 0x2ffffffff : Chip Select 1 60 * 0x30000000 - 0x3ffffffff : Chip Select 2 61 * 0x40000000 - 0x4ffffffff : Chip Select 3 62 * 0x50000000 - 0x5ffffffff : Chip Select 4 63 * 0x60000000 - 0x6ffffffff : Chip Select 5 64 * 0x70000000 - 0x7ffffffff : Chip Select 6 65 * 0x80000000 - 0x8ffffffff : Chip Select 7 66 * 0x90000000 - 0xeffffffff : Undefined (Abort) 67 * 0xf0000000 - 0xfffffffff : Peripherals 68 */ 69 70#define AT91_CHIPSELECT_0 0x10000000 71#define AT91_CHIPSELECT_1 0x20000000 72#define AT91_CHIPSELECT_2 0x30000000 73#define AT91_CHIPSELECT_3 0x40000000 74#define AT91_CHIPSELECT_4 0x50000000 75#define AT91_CHIPSELECT_5 0x60000000 76#define AT91_CHIPSELECT_6 0x70000000 77#define AT91_CHIPSELECT_7 0x80000000 78 79 80#define AT91SAM9G20_BASE 0xd0000000 81 82 83#define AT91SAM9G20_EMAC_BASE 0xffc4000 84#define AT91SAM9G20_EMAC_SIZE 0x4000 85 86#define AT91SAM9G20_RSTC_BASE 0xffffd00 87#define AT91SAM9G20_RSTC_SIZE 0x10 88 89#define RSTC_CR 0 90#define RSTC_PROCRST (1 << 0) 91#define RSTC_PERRST (1 << 2) 92#define RSTC_KEY (0xa5 << 24) 93 94/* USART*/ 95 96#define AT91SAM9G20_USART_SIZE 0x4000 97#define AT91SAM9G20_USART0_BASE 0xffb0000 98#define AT91SAM9G20_USART0_PDC 0xffb0100 99#define AT91SAM9G20_USART0_SIZE AT91SAM9G20_USART_SIZE 100#define AT91SAM9G20_USART1_BASE 0xffb4000 101#define AT91SAM9G20_USART1_PDC 0xffb4100 102#define AT91SAM9G20_USART1_SIZE AT91SAM9G20_USART_SIZE 103#define AT91SAM9G20_USART2_BASE 0xffb8000 104#define AT91SAM9G20_USART2_PDC 0xffb8100 105#define AT91SAM9G20_USART2_SIZE AT91SAM9G20_USART_SIZE 106#define AT91SAM9G20_USART3_BASE 0xffd0000 107#define AT91SAM9G20_USART3_PDC 0xffd0100 108#define AT91SAM9G20_USART3_SIZE AT91SAM9G20_USART_SIZE 109#define AT91SAM9G20_USART4_BASE 0xffd4000 110#define AT91SAM9G20_USART4_PDC 0xffd4100 111#define AT91SAM9G20_USART4_SIZE AT91SAM9G20_USART_SIZE 112#define AT91SAM9G20_USART5_BASE 0xffd8000 113#define AT91SAM9G20_USART5_PDC 0xffd8100 114#define AT91SAM9G20_USART5_SIZE AT91SAM9G20_USART_SIZE 115 116/*TC*/ 117#define AT91SAM9G20_TC0_BASE 0xffa0000 118#define AT91SAM9G20_TC0_SIZE 0x4000 119#define AT91SAM9G20_TC0C0_BASE 0xffa0000 120#define AT91SAM9G20_TC0C1_BASE 0xffa0040 121#define AT91SAM9G20_TC0C2_BASE 0xffa0080 122 123#define AT91SAM9G20_TC1_BASE 0xffdc000 124#define AT91SAM9G20_TC1_SIZE 0x4000 125 126/*SPI*/ 127 128#define AT91SAM9G20_SPI0_BASE 0xffc8000 129 130#define AT91SAM9G20_SPI0_SIZE 0x4000 131#define AT91SAM9G20_IRQ_SPI0 12 132 133#define AT91SAM9G20_SPI1_BASE 0xffcc000 134#define AT91SAM9G20_SPI1_SIZE 0x4000 135#define AT91SAM9G20_IRQ_SPI1 13 136 137/* System Registers */ 138#define AT91SAM9G20_SYS_BASE 0xffff000 139#define AT91SAM9G20_SYS_SIZE 0x1000 140 141#define AT91SAM9G20_MATRIX_BASE 0xfffee00 142#define AT91SAM9G20_MATRIX_SIZE 0x1000 143#define AT91SAM9G20_EBICSA 0x011C 144 145#define AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA (1 << 3) 146 147#define AT91SAM9G20_DBGU_BASE 0xffff200 148#define AT91SAM9G20_DBGU_SIZE 0x200 149 150/* 151 * PIO 152 */ 153#define AT91SAM9G20_PIOA_BASE 0xffff400 154#define AT91SAM9G20_PIOA_SIZE 0x200 155#define AT91SAM9G20_PIOB_BASE 0xffff600 156#define AT91SAM9G20_PIOB_SIZE 0x200 157#define AT91SAM9G20_PIOC_BASE 0xffff800 158#define AT91SAM9G20_PIOC_SIZE 0x200 159 160#define AT91RM92_PMC_BASE 0xffffc00 161#define AT91RM92_PMC_SIZE 0x100 162/* IRQs : */ 163/* 164 * 0: AIC 165 * 1: System peripheral (System timer, RTC, DBGU) 166 * 2: PIO Controller A 167 * 3: PIO Controller B 168 * 4: PIO Controller C 169 * 5: ADC 170 * 6: USART 0 171 * 7: USART 1 172 * 8: USART 2 173 * 9: MMC Interface 174 * 10: USB device port 175 * 11: Two-wirte interface 176 * 12: SPI 0 177 * 13: SPI 1 178 * 14: SSC 179 * 15: - (reserved) 180 * 16: - (reserved) 181 * 17: Timer Counter 0 182 * 18: Timer Counter 1 183 * 19: Timer Counter 2 184 * 20: USB Host port 185 * 21: EMAC 186 * 22: ISI 187 * 23: USART 3 188 * 24: USART 4 189 * 25: USART 2 190 * 26: Timer Counter 3 191 * 27: Timer Counter 4 192 * 28: Timer Counter 5 193 * 29: AIC IRQ0 194 * 30: AIC IRQ1 195 * 31: AIC IRQ2 196 */ 197 198#define AT91SAM9G20_IRQ_SYSTEM 1 199#define AT91SAM9G20_IRQ_PIOA 2 200#define AT91SAM9G20_IRQ_PIOB 3 201#define AT91SAM9G20_IRQ_PIOC 4 202#define AT91SAM9G20_IRQ_USART0 6 203#define AT91SAM9G20_IRQ_USART1 7 204#define AT91SAM9G20_IRQ_USART2 8 205#define AT91SAM9G20_IRQ_MCI 9 206#define AT91SAM9G20_IRQ_UDP 10 207#define AT91SAM9G20_IRQ_TWI 11 208#define AT91SAM9G20_IRQ_SPI0 12 209#define AT91SAM9G20_IRQ_SPI1 13 210#define AT91SAM9G20_IRQ_SSC0 14 211#define AT91SAM9G20_IRQ_SSC1 15 212#define AT91SAM9G20_IRQ_SSC2 16 213#define AT91SAM9G20_IRQ_TC0 17 214#define AT91SAM9G20_IRQ_TC1 18 215#define AT91SAM9G20_IRQ_TC2 19 216#define AT91SAM9G20_IRQ_UHP 20 217#define AT91SAM9G20_IRQ_EMAC 21 218#define AT91SAM9G20_IRQ_USART3 23 219#define AT91SAM9G20_IRQ_USART4 24 220#define AT91SAM9G20_IRQ_USART5 25 221#define AT91SAM9G20_IRQ_AICBASE 29 222 223/* Alias */ 224#define AT91SAM9G20_IRQ_DBGU AT91SAM9G20_IRQ_SYSTEM 225#define AT91SAM9G20_IRQ_PMC AT91SAM9G20_IRQ_SYSTEM 226#define AT91SAM9G20_IRQ_WDT AT91SAM9G20_IRQ_SYSTEM 227#define AT91SAM9G20_IRQ_PIT AT91SAM9G20_IRQ_SYSTEM 228#define AT91SAM9G20_IRQ_RSTC AT91SAM9G20_IRQ_SYSTEM 229#define AT91SAM9G20_IRQ_OHCI AT91SAM9G20_IRQ_UHP 230#define AT91SAM9G20_IRQ_NAND (-1) 231 232#define AT91SAM9G20_AIC_BASE 0xffff000 233#define AT91SAM9G20_AIC_SIZE 0x200 234 235/* Timer */ 236 237#define AT91SAM9G20_WDT_BASE 0xffffd40 238#define AT91SAM9G20_WDT_SIZE 0x10 239 240#define AT91SAM9G20_PIT_BASE 0xffffd30 241#define AT91SAM9G20_PIT_SIZE 0x10 242 243#define AT91SAM9G20_SMC_BASE 0xfffec00 244#define AT91SAM9G20_SMC_SIZE 0x200 245 246#define AT91SAM9G20_PMC_BASE 0xffffc00 247#define AT91SAM9G20_PMC_SIZE 0x100 248 249#define AT91SAM9G20_UDP_BASE 0xffa4000 250#define AT91SAM9G20_UDP_SIZE 0x4000 251 252#define AT91SAM9G20_MCI_BASE 0xffa8000 253#define AT91SAM9G20_MCI_SIZE 0x4000 254 255#define AT91SAM9G20_TWI_BASE 0xffaC000 256#define AT91SAM9G20_TWI_SIZE 0x4000 257 258/* XXX Needs to be carfully coordinated with 259 * other * soc's so phyical and vm address 260 * mapping are unique. XXX 261 */ 262#define AT91SAM9G20_OHCI_BASE 0xdfc00000 263#define AT91SAM9G20_OHCI_PA_BASE 0x00500000 264#define AT91SAM9G20_OHCI_SIZE 0x00100000 265 266#define AT91SAM9G20_NAND_BASE 0xe0000000 267#define AT91SAM9G20_NAND_PA_BASE 0x40000000 268#define AT91SAM9G20_NAND_SIZE 0x10000000 269 270 271/* SDRAMC */ 272#define AT91SAM9G20_SDRAMC_BASE 0xfffea00 273#define AT91SAM9G20_SDRAMC_MR 0x00 274#define AT91SAM9G20_SDRAMC_MR_MODE_NORMAL 0 275#define AT91SAM9G20_SDRAMC_MR_MODE_NOP 1 276#define AT91SAM9G20_SDRAMC_MR_MODE_PRECHARGE 2 277#define AT91SAM9G20_SDRAMC_MR_MODE_LOAD_MODE_REGISTER 3 278#define AT91SAM9G20_SDRAMC_MR_MODE_REFRESH 4 279#define AT91SAM9G20_SDRAMC_TR 0x04 280#define AT91SAM9G20_SDRAMC_CR 0x08 281#define AT91SAM9G20_SDRAMC_CR_NC_8 0x0 282#define AT91SAM9G20_SDRAMC_CR_NC_9 0x1 283#define AT91SAM9G20_SDRAMC_CR_NC_10 0x2 284#define AT91SAM9G20_SDRAMC_CR_NC_11 0x3 285#define AT91SAM9G20_SDRAMC_CR_NC_MASK 0x00000003 286#define AT91SAM9G20_SDRAMC_CR_NR_11 0x0 287#define AT91SAM9G20_SDRAMC_CR_NR_12 0x4 288#define AT91SAM9G20_SDRAMC_CR_NR_13 0x8 289#define AT91SAM9G20_SDRAMC_CR_NR_RES 0xc 290#define AT91SAM9G20_SDRAMC_CR_NR_MASK 0x0000000c 291#define AT91SAM9G20_SDRAMC_CR_NB_2 0x00 292#define AT91SAM9G20_SDRAMC_CR_NB_4 0x10 293#define AT91SAM9G20_SDRAMC_CR_DBW_16 0x80 294#define AT91SAM9G20_SDRAMC_CR_NB_MASK 0x00000010 295#define AT91SAM9G20_SDRAMC_CR_NCAS_MASK 0x00000060 296#define AT91SAM9G20_SDRAMC_CR_TWR_MASK 0x00000780 297#define AT91SAM9G20_SDRAMC_CR_TRC_MASK 0x00007800 298#define AT91SAM9G20_SDRAMC_CR_TRP_MASK 0x00078000 299#define AT91SAM9G20_SDRAMC_CR_TRCD_MASK 0x00780000 300#define AT91SAM9G20_SDRAMC_CR_TRAS_MASK 0x07800000 301#define AT91SAM9G20_SDRAMC_CR_TXSR_MASK 0x78000000 302#define AT91SAM9G20_SDRAMC_HSR 0x0c 303#define AT91SAM9G20_SDRAMC_LPR 0x10 304#define AT91SAM9G20_SDRAMC_IER 0x14 305#define AT91SAM9G20_SDRAMC_IDR 0x18 306#define AT91SAM9G20_SDRAMC_IMR 0x1c 307#define AT91SAM9G20_SDRAMC_ISR 0x20 308#define AT91SAM9G20_SDRAMC_MDR 0x24 309 310#endif /* AT91SAM9G20REG_H_*/ 311 312