at91sam9g20reg.h revision 210040
1/*- 2 * Copyright (c) 2009 Sylvestre Gallon. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 */ 25 26/* $FreeBSD: head/sys/arm/at91/at91sam9g20reg.h 210040 2010-07-14 00:48:53Z cognet $ */ 27 28#ifndef AT91SAM9G20REG_H_ 29#define AT91SAM9G20REG_H_ 30 31/* 32 * Memory map, from datasheet : 33 * 0x00000000 - 0x0ffffffff : Internal Memories 34 * 0x10000000 - 0x1ffffffff : Chip Select 0 35 * 0x20000000 - 0x2ffffffff : Chip Select 1 36 * 0x30000000 - 0x3ffffffff : Chip Select 2 37 * 0x40000000 - 0x4ffffffff : Chip Select 3 38 * 0x50000000 - 0x5ffffffff : Chip Select 4 39 * 0x60000000 - 0x6ffffffff : Chip Select 5 40 * 0x70000000 - 0x7ffffffff : Chip Select 6 41 * 0x80000000 - 0x8ffffffff : Chip Select 7 42 * 0x90000000 - 0xeffffffff : Undefined (Abort) 43 * 0xf0000000 - 0xfffffffff : Peripherals 44 */ 45 46#define AT91_CHIPSELECT_0 0x10000000 47#define AT91_CHIPSELECT_1 0x20000000 48#define AT91_CHIPSELECT_2 0x30000000 49#define AT91_CHIPSELECT_3 0x40000000 50#define AT91_CHIPSELECT_4 0x50000000 51#define AT91_CHIPSELECT_5 0x60000000 52#define AT91_CHIPSELECT_6 0x70000000 53#define AT91_CHIPSELECT_7 0x80000000 54 55 56#define AT91SAM9G20_BASE 0xd0000000 57 58 59#define AT91SAM9G20_IRQ_EMAC 21 60#define AT91SAM9G20_EMAC_BASE 0xffc4000 61#define AT91SAM9G20_EMAC_SIZE 0x4000 62 63#define AT91SAM9G20_RSTC_BASE 0xffffd00 64 65#define RSTC_CR 0 66#define RSTC_PROCRST (1 << 0) 67#define RSTC_PERRST (1 << 2) 68#define RSTC_KEY (0xa5 << 24) 69 70/* USART*/ 71 72#define AT91SAM9G20_USART0_BASE 0xffb0000 73#define AT91SAM9G20_USART0_PDC 0xffb0100 74#define AT91SAM9G20_USART1_BASE 0xffb4000 75#define AT91SAM9G20_USART1_PDC 0xffb4100 76#define AT91SAM9G20_USART2_BASE 0xffb8000 77#define AT91SAM9G20_USART2_PDC 0xffb8100 78#define AT91SAM9G20_USART_SIZE 0x4000 79 80/*TC*/ 81#define AT91SAM9G20_TC0_BASE 0xffa0000 82#define AT91SAM9G20_TC0_SIZE 0x4000 83#define AT91SAM9G20_TC0C0_BASE 0xffa0000 84#define AT91SAM9G20_TC0C1_BASE 0xffa0040 85#define AT91SAM9G20_TC0C2_BASE 0xffa0080 86 87#define AT91SAM9G20_TC1_BASE 0xffdc000 88#define AT91SAM9G20_TC1_SIZE 0x4000 89 90/*SPI*/ 91 92#define AT91SAM9G20_SPI0_BASE 0xffc8000 93 94#define AT91SAM9G20_SPI0_SIZE 0x4000 95#define AT91SAM9G20_IRQ_SPI0 12 96 97#define AT91SAM9G20_SPI1_BASE 0xffcc000 98#define AT91SAM9G20_SPI1_SIZE 0x4000 99#define AT91SAM9G20_IRQ_SPI1 13 100 101/* System Registers */ 102#define AT91SAM9G20_SYS_BASE 0xfffe000 103#define AT91SAM9G20_SYS_SIZE 0x2000 104 105#define AT91SAM9G20_MATRIX (0xe00) 106 107#define AT91SAM9G20_EBICSA (AT91SAM9G20_MATRIX + 0x011C) 108 109#define AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA (1 << 3) 110 111#define DBGU 0x200 112#define DBGU_SIZE 0x200 113#define DBGU_C1R (0x200 + 64) /* Chip ID1 Register */ 114#define DBGU_C2R (0x200 + 68) /* Chip ID2 Register */ 115#define DBGU_FNTR (0x200 + 72) /* Force NTRST Register */ 116 117/* 118 * PIO 119 */ 120#define AT91SAM9G20_PIOA_BASE 0xffff400 121#define AT91SAM9G20_PIO_SIZE 0x200 122#define AT91SAM9G20_PIOB_BASE 0xffff600 123#define AT91SAM9G20_PIOC_BASE 0xffff800 124 125#define AT91RM92_PMC_BASE 0xffffc00 126#define AT91RM92_PMC_SIZE 0x100 127/* IRQs : */ 128/* 129 * 0: AIC 130 * 1: System peripheral (System timer, RTC, DBGU) 131 * 2: PIO Controller A 132 * 3: PIO Controller B 133 * 4: PIO Controller C 134 * 5: - 135 * 6: USART 0 136 * 7: USART 1 137 * 8: USART 2 138 * 9: MMC Interface 139 * 10: USB device port 140 * 11: Two-wirte interface 141 * 12: SPI 142 * 13: SPI 143 * 14: SSC 144 * 15: SSC 145 * 16: SSC 146 * 17: Timer Counter 0 147 * 18: Timer Counter 1 148 * 19: Timer Counter 2 149 * 20: USB Host port 150 * 21: EMAC 151 * 22-28: - 152 * 29: AIC 153 * 30: AIC 154 * 31: AIC 155 */ 156 157#define AT91SAM9G20_IRQ_SYSTEM 1 158#define AT91SAM9G20_IRQ_PIOA 2 159#define AT91SAM9G20_IRQ_PIOB 3 160#define AT91SAM9G20_IRQ_PIOC 4 161#define AT91SAM9G20_IRQ_USART0 6 162#define AT91SAM9G20_IRQ_USART1 7 163#define AT91SAM9G20_IRQ_USART2 8 164#define AT91SAM9G20_IRQ_MCI 9 165#define AT91SAM9G20_IRQ_UDP 10 166#define AT91SAM9G20_IRQ_TWI 11 167#define AT91SAM9G20_IRQ_SPI0 12 168#define AT91SAM9G20_IRQ_SPI1 13 169#define AT91SAM9G20_IRQ_SSC0 14 170#define AT91SAM9G20_IRQ_SSC1 15 171#define AT91SAM9G20_IRQ_SSC2 16 172#define AT91SAM9G20_IRQ_TC0 17 173#define AT91SAM9G20_IRQ_TC1 18 174#define AT91SAM9G20_IRQ_TC2 19 175#define AT91SAM9G20_IRQ_UHP 20 176#define AT91SAM9G20_IRQ_AICBASE 29 177 178/* Timer */ 179 180#define AT91SAM9G20_DBGU_BASE 0xffff200 181#define AT91SAM9G20_DBGU_SIZE 0x200 182 183#define AT91SAM9G20_WDT_BASE 0xffffd40 184#define AT91SAM9G20_WDT_SIZE 0x10 185 186#define AT91SAM9G20_PIT_BASE 0xffffd30 187#define AT91SAM9G20_PIT_SIZE 10 188 189#define AT91SAM9G20_SMC_BASE 0xfffec00 190#define AT91SAM9G20_SMC_SIZE 0x200 191 192#define AT91SAM9G20_PMC_BASE 0xffffc00 193#define AT91SAM9G20_PMC_SIZE 0x100 194 195#define AT91SAM9G20_UDP_BASE 0xffa4000 196#define AT91SAM9G20_UDP_SIZE 0x4000 197 198#define AT91SAM9G20_OHCI_BASE 0xdfe00000 199#define AT91SAM9G20_OHCI_PA_BASE 0x00500000 200#define AT91SAM9G20_OHCI_SIZE 0x00100000 201 202 203//#define AT91SAM9G20_NAND_BASE 0xdf100000 204 205//#define AT91SAM9G20_NAND_BASE 0x40000000 206 207#define AT91SAM9G20_NAND_BASE 0xe0000000 208 209#define AT91SAM9G20_NAND_PA_BASE 0x40000000 210#define AT91SAM9G20_NAND_SIZE 0x10000000 211//#define AT91SAM9G20_NAND_SIZE 0x00900000 212 213//#define AT91SAM9G20_OHCI_SIZE 0x0004000 214 215/* SDRAMC */ 216#define AT91SAM9G20_SDRAMC_BASE 0xfffea00 217#define AT91SAM9G20_SDRAMC_MR 0x00 218#define AT91SAM9G20_SDRAMC_MR_MODE_NORMAL 0 219#define AT91SAM9G20_SDRAMC_MR_MODE_NOP 1 220#define AT91SAM9G20_SDRAMC_MR_MODE_PRECHARGE 2 221#define AT91SAM9G20_SDRAMC_MR_MODE_LOAD_MODE_REGISTER 3 222#define AT91SAM9G20_SDRAMC_MR_MODE_REFRESH 4 223#define AT91SAM9G20_SDRAMC_TR 0x04 224#define AT91SAM9G20_SDRAMC_CR 0x08 225#define AT91SAM9G20_SDRAMC_CR_NC_8 0x0 226#define AT91SAM9G20_SDRAMC_CR_NC_9 0x1 227#define AT91SAM9G20_SDRAMC_CR_NC_10 0x2 228#define AT91SAM9G20_SDRAMC_CR_NC_11 0x3 229#define AT91SAM9G20_SDRAMC_CR_NC_MASK 0x00000003 230#define AT91SAM9G20_SDRAMC_CR_NR_11 0x0 231#define AT91SAM9G20_SDRAMC_CR_NR_12 0x4 232#define AT91SAM9G20_SDRAMC_CR_NR_13 0x8 233#define AT91SAM9G20_SDRAMC_CR_NR_RES 0xc 234#define AT91SAM9G20_SDRAMC_CR_NR_MASK 0x0000000c 235#define AT91SAM9G20_SDRAMC_CR_NB_2 0x00 236#define AT91SAM9G20_SDRAMC_CR_NB_4 0x10 237#define AT91SAM9G20_SDRAMC_CR_NB_MASK 0x00000010 238#define AT91SAM9G20_SDRAMC_CR_NCAS_MASK 0x00000060 239#define AT91SAM9G20_SDRAMC_CR_TWR_MASK 0x00000780 240#define AT91SAM9G20_SDRAMC_CR_TRC_MASK 0x00007800 241#define AT91SAM9G20_SDRAMC_CR_TRP_MASK 0x00078000 242#define AT91SAM9G20_SDRAMC_CR_TRCD_MASK 0x00780000 243#define AT91SAM9G20_SDRAMC_CR_TRAS_MASK 0x07800000 244#define AT91SAM9G20_SDRAMC_CR_TXSR_MASK 0x78000000 245#define AT91SAM9G20_SDRAMC_HSR 0x0c 246#define AT91SAM9G20_SDRAMC_LPR 0x10 247#define AT91SAM9G20_SDRAMC_IER 0x14 248#define AT91SAM9G20_SDRAMC_IDR 0x18 249#define AT91SAM9G20_SDRAMC_IMR 0x1c 250#define AT91SAM9G20_SDRAMC_ISR 0x20 251#define AT91SAM9G20_SDRAMC_MDR 0x24 252 253#endif /* AT91SAM9G20REG_H_*/ 254 255