at91rm9200.c revision 238390
1/*- 2 * Copyright (c) 2005 Olivier Houchard. All rights reserved. 3 * Copyright (c) 2010 Greg Ansley. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> 28__FBSDID("$FreeBSD: head/sys/arm/at91/at91rm9200.c 238390 2012-07-12 04:23:11Z imp $"); 29 30#include <sys/param.h> 31#include <sys/systm.h> 32#include <sys/bus.h> 33#include <sys/kernel.h> 34#include <sys/malloc.h> 35#include <sys/module.h> 36 37#define _ARM32_BUS_DMA_PRIVATE 38#include <machine/bus.h> 39 40#include <arm/at91/at91var.h> 41#include <arm/at91/at91reg.h> 42#include <arm/at91/at91rm92reg.h> 43#include <arm/at91/at91_aicreg.h> 44#include <arm/at91/at91_pmcreg.h> 45#include <arm/at91/at91_streg.h> 46#include <arm/at91/at91_pmcvar.h> 47#include <arm/at91/at91soc.h> 48 49 50struct at91rm92_softc { 51 device_t dev; 52 bus_space_tag_t sc_st; 53 bus_space_handle_t sc_sh; 54 bus_space_handle_t sc_sys_sh; 55 bus_space_handle_t sc_aic_sh; 56}; 57/* 58 * Standard priority levels for the system. 0 is lowest and 7 is highest. 59 * These values are the ones Atmel uses for its Linux port, which differ 60 * a little form the ones that are in the standard distribution. Also, 61 * the ones marked with 'TWEEK' are different based on experience. 62 */ 63static const int at91_irq_prio[32] = 64{ 65 7, /* Advanced Interrupt Controller (FIQ) */ 66 7, /* System Peripherals */ 67 1, /* Parallel IO Controller A */ 68 1, /* Parallel IO Controller B */ 69 1, /* Parallel IO Controller C */ 70 1, /* Parallel IO Controller D */ 71 5, /* USART 0 */ 72 5, /* USART 1 */ 73 5, /* USART 2 */ 74 5, /* USART 3 */ 75 0, /* Multimedia Card Interface */ 76 2, /* USB Device Port */ 77 4, /* Two-Wire Interface */ /* TWEEK */ 78 5, /* Serial Peripheral Interface */ 79 4, /* Serial Synchronous Controller 0 */ 80 6, /* Serial Synchronous Controller 1 */ /* TWEEK */ 81 4, /* Serial Synchronous Controller 2 */ 82 0, /* Timer Counter 0 */ 83 6, /* Timer Counter 1 */ /* TWEEK */ 84 0, /* Timer Counter 2 */ 85 0, /* Timer Counter 3 */ 86 0, /* Timer Counter 4 */ 87 0, /* Timer Counter 5 */ 88 2, /* USB Host port */ 89 3, /* Ethernet MAC */ 90 0, /* Advanced Interrupt Controller (IRQ0) */ 91 0, /* Advanced Interrupt Controller (IRQ1) */ 92 0, /* Advanced Interrupt Controller (IRQ2) */ 93 0, /* Advanced Interrupt Controller (IRQ3) */ 94 0, /* Advanced Interrupt Controller (IRQ4) */ 95 0, /* Advanced Interrupt Controller (IRQ5) */ 96 0 /* Advanced Interrupt Controller (IRQ6) */ 97}; 98 99#define DEVICE(_name, _id, _unit) \ 100 { \ 101 _name, _unit, \ 102 AT91RM92_ ## _id ##_BASE, \ 103 AT91RM92_ ## _id ## _SIZE, \ 104 AT91RM92_IRQ_ ## _id \ 105 } 106 107static const struct cpu_devs at91_devs[] = 108{ 109 DEVICE("at91_pmc", PMC, 0), 110 DEVICE("at91_st", ST, 0), 111 DEVICE("at91_pio", PIOA, 0), 112 DEVICE("at91_pio", PIOB, 1), 113 DEVICE("at91_pio", PIOC, 2), 114 DEVICE("at91_pio", PIOD, 3), 115 DEVICE("at91_rtc", RTC, 0), 116 117 DEVICE("at91_mci", MCI, 0), 118 DEVICE("at91_twi", TWI, 0), 119 DEVICE("at91_udp", UDP, 0), 120 DEVICE("ate", EMAC, 0), 121 DEVICE("at91_ssc", SSC0, 0), 122 DEVICE("at91_ssc", SSC1, 1), 123 DEVICE("at91_ssc", SSC2, 2), 124 DEVICE("spi", SPI, 0), 125 126 DEVICE("uart", DBGU, 0), 127 DEVICE("uart", USART0, 1), 128 DEVICE("uart", USART1, 2), 129 DEVICE("uart", USART2, 3), 130 DEVICE("uart", USART3, 4), 131 DEVICE("at91_aic", AIC, 0), 132 DEVICE("at91_mc", MC, 0), 133 DEVICE("at91_tc", TC0, 0), 134 DEVICE("at91_tc", TC1, 1), 135 DEVICE("ohci", OHCI, 0), 136 DEVICE("af91_cfata", CF, 0), 137 { 0, 0, 0, 0, 0 } 138}; 139 140static uint32_t 141at91_pll_outb(int freq) 142{ 143 144 if (freq > 155000000) 145 return (0x0000); 146 else 147 return (0x8000); 148} 149 150static void 151at91_identify(driver_t *drv, device_t parent) 152{ 153 154 if (at91_cpu_is(AT91_T_RM9200)) 155 at91_add_child(parent, 0, "at91rm920", 0, 0, 0, -1, 0, 0); 156} 157 158static int 159at91_probe(device_t dev) 160{ 161 162 device_set_desc(dev, soc_info.name); 163 return (0); 164} 165 166static int 167at91_attach(device_t dev) 168{ 169 struct at91_pmc_clock *clk; 170 struct at91rm92_softc *sc = device_get_softc(dev); 171 struct at91_softc *at91sc = device_get_softc(device_get_parent(dev)); 172 173 sc->sc_st = at91sc->sc_st; 174 sc->sc_sh = at91sc->sc_sh; 175 sc->dev = dev; 176 177 if (bus_space_subregion(sc->sc_st, sc->sc_sh, AT91RM92_SYS_BASE, 178 AT91RM92_SYS_SIZE, &sc->sc_sys_sh) != 0) 179 panic("Enable to map system registers"); 180 181 /* Disable all interrupts for RTC (0xe24 == RTC_IDR) */ 182 bus_space_write_4(sc->sc_st, sc->sc_sys_sh, 0xe24, 0xffffffff); 183 184 /* Disable all interrupts for the SDRAM controller */ 185 bus_space_write_4(sc->sc_st, sc->sc_sys_sh, 0xfa8, 0xffffffff); 186 187 /* Update USB device port clock info */ 188 clk = at91_pmc_clock_ref("udpck"); 189 clk->pmc_mask = PMC_SCER_UDP; 190 at91_pmc_clock_deref(clk); 191 192 /* Update USB host port clock info */ 193 clk = at91_pmc_clock_ref("uhpck"); 194 clk->pmc_mask = PMC_SCER_UHP; 195 at91_pmc_clock_deref(clk); 196 197 /* Each SOC has different PLL contraints */ 198 clk = at91_pmc_clock_ref("plla"); 199 clk->pll_min_in = RM9200_PLL_A_MIN_IN_FREQ; /* 1 MHz */ 200 clk->pll_max_in = RM9200_PLL_A_MAX_IN_FREQ; /* 32 MHz */ 201 clk->pll_min_out = RM9200_PLL_A_MIN_OUT_FREQ; /* 80 MHz */ 202 clk->pll_max_out = RM9200_PLL_A_MAX_OUT_FREQ; /* 180 MHz */ 203 clk->pll_mul_shift = RM9200_PLL_A_MUL_SHIFT; 204 clk->pll_mul_mask = RM9200_PLL_A_MUL_MASK; 205 clk->pll_div_shift = RM9200_PLL_A_DIV_SHIFT; 206 clk->pll_div_mask = RM9200_PLL_A_DIV_MASK; 207 clk->set_outb = at91_pll_outb; 208 at91_pmc_clock_deref(clk); 209 210 clk = at91_pmc_clock_ref("pllb"); 211 clk->pll_min_in = RM9200_PLL_B_MIN_IN_FREQ; /* 100 KHz */ 212 clk->pll_max_in = RM9200_PLL_B_MAX_IN_FREQ; /* 32 MHz */ 213 clk->pll_min_out = RM9200_PLL_B_MIN_OUT_FREQ; /* 30 MHz */ 214 clk->pll_max_out = RM9200_PLL_B_MAX_OUT_FREQ; /* 240 MHz */ 215 clk->pll_mul_shift = RM9200_PLL_B_MUL_SHIFT; 216 clk->pll_mul_mask = RM9200_PLL_B_MUL_MASK; 217 clk->pll_div_shift = RM9200_PLL_B_DIV_SHIFT; 218 clk->pll_div_mask = RM9200_PLL_B_DIV_MASK; 219 clk->set_outb = at91_pll_outb; 220 at91_pmc_clock_deref(clk); 221 222 return (0); 223} 224 225static device_method_t at91_methods[] = { 226 DEVMETHOD(device_probe, at91_probe), 227 DEVMETHOD(device_attach, at91_attach), 228 DEVMETHOD(device_identify, at91_identify), 229 {0, 0}, 230}; 231 232static driver_t at91rm92_driver = { 233 "at91rm920", 234 at91_methods, 235 sizeof(struct at91rm92_softc), 236}; 237 238static devclass_t at91rm92_devclass; 239 240DRIVER_MODULE(at91rm920, atmelarm, at91rm92_driver, at91rm92_devclass, 0, 0); 241 242static struct at91_soc_data soc_data = { 243 .soc_delay = at91_st_delay, 244 .soc_reset = at91_st_cpu_reset, 245 .soc_irq_prio = at91_irq_prio, 246 .soc_children = at91_devs, 247}; 248 249AT91_SOC(AT91_T_RM9200, &soc_data); 250