at91rm9200.c revision 238376
1/*- 2 * Copyright (c) 2005 Olivier Houchard. All rights reserved. 3 * Copyright (c) 2010 Greg Ansley. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> 28__FBSDID("$FreeBSD: head/sys/arm/at91/at91rm9200.c 238376 2012-07-11 20:17:14Z imp $"); 29 30#include <sys/param.h> 31#include <sys/systm.h> 32#include <sys/bus.h> 33#include <sys/kernel.h> 34#include <sys/malloc.h> 35#include <sys/module.h> 36 37#define _ARM32_BUS_DMA_PRIVATE 38#include <machine/bus.h> 39 40#include <arm/at91/at91var.h> 41#include <arm/at91/at91reg.h> 42#include <arm/at91/at91rm92reg.h> 43#include <arm/at91/at91_aicreg.h> 44#include <arm/at91/at91_pmcreg.h> 45#include <arm/at91/at91_streg.h> 46#include <arm/at91/at91_pmcvar.h> 47#include <arm/at91/at91soc.h> 48 49 50struct at91rm92_softc { 51 device_t dev; 52 bus_space_tag_t sc_st; 53 bus_space_handle_t sc_sh; 54 bus_space_handle_t sc_sys_sh; 55 bus_space_handle_t sc_aic_sh; 56}; 57/* 58 * Standard priority levels for the system. 0 is lowest and 7 is highest. 59 * These values are the ones Atmel uses for its Linux port, which differ 60 * a little form the ones that are in the standard distribution. Also, 61 * the ones marked with 'TWEEK' are different based on experience. 62 */ 63static const int at91_irq_prio[32] = 64{ 65 7, /* Advanced Interrupt Controller (FIQ) */ 66 7, /* System Peripherals */ 67 1, /* Parallel IO Controller A */ 68 1, /* Parallel IO Controller B */ 69 1, /* Parallel IO Controller C */ 70 1, /* Parallel IO Controller D */ 71 5, /* USART 0 */ 72 5, /* USART 1 */ 73 5, /* USART 2 */ 74 5, /* USART 3 */ 75 0, /* Multimedia Card Interface */ 76 2, /* USB Device Port */ 77 4, /* Two-Wire Interface */ /* TWEEK */ 78 5, /* Serial Peripheral Interface */ 79 4, /* Serial Synchronous Controller 0 */ 80 6, /* Serial Synchronous Controller 1 */ /* TWEEK */ 81 4, /* Serial Synchronous Controller 2 */ 82 0, /* Timer Counter 0 */ 83 6, /* Timer Counter 1 */ /* TWEEK */ 84 0, /* Timer Counter 2 */ 85 0, /* Timer Counter 3 */ 86 0, /* Timer Counter 4 */ 87 0, /* Timer Counter 5 */ 88 2, /* USB Host port */ 89 3, /* Ethernet MAC */ 90 0, /* Advanced Interrupt Controller (IRQ0) */ 91 0, /* Advanced Interrupt Controller (IRQ1) */ 92 0, /* Advanced Interrupt Controller (IRQ2) */ 93 0, /* Advanced Interrupt Controller (IRQ3) */ 94 0, /* Advanced Interrupt Controller (IRQ4) */ 95 0, /* Advanced Interrupt Controller (IRQ5) */ 96 0 /* Advanced Interrupt Controller (IRQ6) */ 97}; 98 99#define DEVICE(_name, _id, _unit) \ 100 { \ 101 _name, _unit, \ 102 AT91RM92_ ## _id ##_BASE, \ 103 AT91RM92_ ## _id ## _SIZE, \ 104 AT91RM92_IRQ_ ## _id \ 105 } 106 107static const struct cpu_devs at91_devs[] = 108{ 109 DEVICE("at91_pmc", PMC, 0), 110 DEVICE("at91_st", ST, 0), 111 DEVICE("at91_pio", PIOA, 0), 112 DEVICE("at91_pio", PIOB, 1), 113 DEVICE("at91_pio", PIOC, 2), 114 DEVICE("at91_pio", PIOD, 3), 115 DEVICE("at91_rtc", RTC, 0), 116 117 DEVICE("at91_mci", MCI, 0), 118 DEVICE("at91_twi", TWI, 0), 119 DEVICE("at91_udp", UDP, 0), 120 DEVICE("ate", EMAC, 0), 121 DEVICE("at91_ssc", SSC0, 0), 122 DEVICE("at91_ssc", SSC1, 1), 123 DEVICE("at91_ssc", SSC2, 2), 124 DEVICE("spi", SPI, 0), 125 126 DEVICE("uart", DBGU, 0), 127 DEVICE("uart", USART0, 1), 128 DEVICE("uart", USART1, 2), 129 DEVICE("uart", USART2, 3), 130 DEVICE("uart", USART3, 4), 131 DEVICE("at91_aic", AIC, 0), 132 DEVICE("at91_mc", MC, 0), 133 DEVICE("at91_tc", TC0, 0), 134 DEVICE("at91_tc", TC1, 1), 135 DEVICE("ohci", OHCI, 0), 136 DEVICE("af91_cfata", CF, 0), 137 { 0, 0, 0, 0, 0 } 138}; 139 140static void 141at91_cpu_add_builtin_children(device_t dev) 142{ 143 int i; 144 const struct cpu_devs *walker; 145 146 for (i = 1, walker = at91_devs; walker->name; i++, walker++) { 147 at91_add_child(dev, i, walker->name, walker->unit, 148 walker->mem_base, walker->mem_len, walker->irq0, 149 walker->irq1, walker->irq2); 150 } 151} 152 153static uint32_t 154at91_pll_outb(int freq) 155{ 156 157 if (freq > 155000000) 158 return (0x0000); 159 else 160 return (0x8000); 161} 162 163static void 164at91_identify(driver_t *drv, device_t parent) 165{ 166 167 if (at91_cpu_is(AT91_T_RM9200)) { 168 at91_add_child(parent, 0, "at91rm920", 0, 0, 0, -1, 0, 0); 169 at91_cpu_add_builtin_children(parent); 170 } 171} 172 173static int 174at91_probe(device_t dev) 175{ 176 177 device_set_desc(dev, soc_info.name); 178 return (0); 179} 180 181static int 182at91_attach(device_t dev) 183{ 184 struct at91_pmc_clock *clk; 185 struct at91rm92_softc *sc = device_get_softc(dev); 186 int i; 187 188 struct at91_softc *at91sc = device_get_softc(device_get_parent(dev)); 189 190 sc->sc_st = at91sc->sc_st; 191 sc->sc_sh = at91sc->sc_sh; 192 sc->dev = dev; 193 194 if (bus_space_subregion(sc->sc_st, sc->sc_sh, AT91RM92_SYS_BASE, 195 AT91RM92_SYS_SIZE, &sc->sc_sys_sh) != 0) 196 panic("Enable to map system registers"); 197 198 if (bus_space_subregion(sc->sc_st, sc->sc_sh, AT91RM92_AIC_BASE, 199 AT91RM92_AIC_SIZE, &sc->sc_aic_sh) != 0) 200 panic("Enable to map system registers"); 201 202 /* XXX Hack to tell atmelarm about the AIC */ 203 at91sc->sc_aic_sh = sc->sc_aic_sh; 204 205 for (i = 0; i < 32; i++) { 206 bus_space_write_4(sc->sc_st, sc->sc_aic_sh, IC_SVR + 207 i * 4, i); 208 /* Priority. */ 209 bus_space_write_4(sc->sc_st, sc->sc_aic_sh, IC_SMR + i * 4, 210 at91_irq_prio[i]); 211 if (i < 8) 212 bus_space_write_4(sc->sc_st, sc->sc_aic_sh, IC_EOICR, 213 1); 214 } 215 216 bus_space_write_4(sc->sc_st, sc->sc_aic_sh, IC_SPU, 32); 217 /* No debug. */ 218 bus_space_write_4(sc->sc_st, sc->sc_aic_sh, IC_DCR, 0); 219 /* Disable and clear all interrupts. */ 220 bus_space_write_4(sc->sc_st, sc->sc_aic_sh, IC_IDCR, 0xffffffff); 221 bus_space_write_4(sc->sc_st, sc->sc_aic_sh, IC_ICCR, 0xffffffff); 222 223 /* Disable all interrupts for RTC (0xe24 == RTC_IDR) */ 224 bus_space_write_4(sc->sc_st, sc->sc_sys_sh, 0xe24, 0xffffffff); 225 226 /* Disable all interrupts for the SDRAM controller */ 227 bus_space_write_4(sc->sc_st, sc->sc_sys_sh, 0xfa8, 0xffffffff); 228 229 /* Update USB device port clock info */ 230 clk = at91_pmc_clock_ref("udpck"); 231 clk->pmc_mask = PMC_SCER_UDP; 232 at91_pmc_clock_deref(clk); 233 234 /* Update USB host port clock info */ 235 clk = at91_pmc_clock_ref("uhpck"); 236 clk->pmc_mask = PMC_SCER_UHP; 237 at91_pmc_clock_deref(clk); 238 239 /* Each SOC has different PLL contraints */ 240 clk = at91_pmc_clock_ref("plla"); 241 clk->pll_min_in = RM9200_PLL_A_MIN_IN_FREQ; /* 1 MHz */ 242 clk->pll_max_in = RM9200_PLL_A_MAX_IN_FREQ; /* 32 MHz */ 243 clk->pll_min_out = RM9200_PLL_A_MIN_OUT_FREQ; /* 80 MHz */ 244 clk->pll_max_out = RM9200_PLL_A_MAX_OUT_FREQ; /* 180 MHz */ 245 clk->pll_mul_shift = RM9200_PLL_A_MUL_SHIFT; 246 clk->pll_mul_mask = RM9200_PLL_A_MUL_MASK; 247 clk->pll_div_shift = RM9200_PLL_A_DIV_SHIFT; 248 clk->pll_div_mask = RM9200_PLL_A_DIV_MASK; 249 clk->set_outb = at91_pll_outb; 250 at91_pmc_clock_deref(clk); 251 252 clk = at91_pmc_clock_ref("pllb"); 253 clk->pll_min_in = RM9200_PLL_B_MIN_IN_FREQ; /* 100 KHz */ 254 clk->pll_max_in = RM9200_PLL_B_MAX_IN_FREQ; /* 32 MHz */ 255 clk->pll_min_out = RM9200_PLL_B_MIN_OUT_FREQ; /* 30 MHz */ 256 clk->pll_max_out = RM9200_PLL_B_MAX_OUT_FREQ; /* 240 MHz */ 257 clk->pll_mul_shift = RM9200_PLL_B_MUL_SHIFT; 258 clk->pll_mul_mask = RM9200_PLL_B_MUL_MASK; 259 clk->pll_div_shift = RM9200_PLL_B_DIV_SHIFT; 260 clk->pll_div_mask = RM9200_PLL_B_DIV_MASK; 261 clk->set_outb = at91_pll_outb; 262 at91_pmc_clock_deref(clk); 263 264 return (0); 265} 266 267static device_method_t at91_methods[] = { 268 DEVMETHOD(device_probe, at91_probe), 269 DEVMETHOD(device_attach, at91_attach), 270 DEVMETHOD(device_identify, at91_identify), 271 {0, 0}, 272}; 273 274static driver_t at91rm92_driver = { 275 "at91rm920", 276 at91_methods, 277 sizeof(struct at91rm92_softc), 278}; 279 280static devclass_t at91rm92_devclass; 281 282DRIVER_MODULE(at91rm920, atmelarm, at91rm92_driver, at91rm92_devclass, 0, 0); 283 284static struct at91_soc_data soc_data = { 285 .soc_delay = at91_st_delay, 286 .soc_reset = at91_st_cpu_reset 287}; 288 289AT91_SOC(AT91_T_RM9200, &soc_data); 290