1213496Scognet/*- 2213496Scognet * Copyright (c) 2005 Gallon Sylvestre. All rights reserved. 3213496Scognet * 4213496Scognet * Redistribution and use in source and binary forms, with or without 5213496Scognet * modification, are permitted provided that the following conditions 6213496Scognet * are met: 7213496Scognet * 1. Redistributions of source code must retain the above copyright 8213496Scognet * notice, this list of conditions and the following disclaimer. 9213496Scognet * 2. Redistributions in binary form must reproduce the above copyright 10213496Scognet * notice, this list of conditions and the following disclaimer in the 11213496Scognet * documentation and/or other materials provided with the distribution. 12213496Scognet * 13213496Scognet * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 14213496Scognet * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15213496Scognet * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16213496Scognet * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17213496Scognet * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18213496Scognet * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19213496Scognet * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20213496Scognet * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21213496Scognet * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22213496Scognet * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23213496Scognet * SUCH DAMAGE. 24213496Scognet */ 25213496Scognet 26236989Simp/* 27213496Scognet * $FreeBSD$ 28213496Scognet */ 29213496Scognet 30213496Scognet#ifndef ARM_AT91_AT91WDTREG_H 31213496Scognet#define ARM_AT91_AT91WDTREG_H 32213496Scognet 33213496Scognet#ifndef WDT_CLOCK 34213496Scognet#define WDT_CLOCK (32768) 35213496Scognet#endif 36213496Scognet#define WDT_DIV (128) /* Clock is slow clock / 128 */ 37213496Scognet 38213496Scognet#define WDT_CR 0x0 /* Control Register */ 39213496Scognet#define WDT_MR 0x4 /* Mode Register */ 40213496Scognet#define WDT_SR 0x8 /* Status Register */ 41213496Scognet 42213496Scognet/* WDT_CR */ 43213496Scognet#define WDT_KEY (0xa5<<24) 44213496Scognet#define WDT_WDRSTT 0x1 45213496Scognet 46213496Scognet/* WDT_MR */ 47213496Scognet#define WDT_WDV(x) (x & 0xfff) /* counter value*/ 48213496Scognet#define WDT_WDFIEN (1<<12) /* enable interrupt */ 49213496Scognet#define WDT_WDRSTEN (1<<13) /* enable reset */ 50213496Scognet#define WDT_WDRPROC (1<<14) /* processor reset */ 51213496Scognet#define WDT_WDDIS (1<<15) /* disable */ 52213496Scognet#define WDT_WDD(x) ((x & 0xfff) << 16) /* delta value */ 53213496Scognet#define WDT_WDDBGHLT (1<<28) /* halt in debug */ 54213496Scognet#define WDT_WDIDLEHLT (1<<29) /* halt in idle */ 55213496Scognet 56213496Scognet/* WDT_SR */ 57213496Scognet#define WDT_WDUNF 0x1 58213496Scognet#define WDT_WDERR 0x2 59213496Scognet 60213496Scognet#endif /* ARM_AT91_AT91WDTREG_H */ 61