at91_twi.c revision 225882
189051Sjake/*- 289051Sjake * Copyright (c) 2006 M. Warner Losh. All rights reserved. 389051Sjake * 489051Sjake * Redistribution and use in source and binary forms, with or without 589051Sjake * modification, are permitted provided that the following conditions 689051Sjake * are met: 789051Sjake * 1. Redistributions of source code must retain the above copyright 889051Sjake * notice, this list of conditions and the following disclaimer. 989051Sjake * 2. Redistributions in binary form must reproduce the above copyright 1089051Sjake * notice, this list of conditions and the following disclaimer in the 1189051Sjake * documentation and/or other materials provided with the distribution. 1289051Sjake * 1389051Sjake * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 1489051Sjake * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 1589051Sjake * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 1689051Sjake * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 1789051Sjake * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 1889051Sjake * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 1989051Sjake * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 2089051Sjake * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 2189051Sjake * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 2289051Sjake * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 2389051Sjake * SUCH DAMAGE. 2489051Sjake */ 2589051Sjake 2689051Sjake#include <sys/cdefs.h> 27114188Sjake__FBSDID("$FreeBSD: head/sys/arm/at91/at91_twi.c 225882 2011-09-30 04:55:23Z kevlo $"); 28114188Sjake 29114188Sjake#include <sys/param.h> 3089051Sjake#include <sys/systm.h> 3189051Sjake#include <sys/bus.h> 3289051Sjake#include <sys/conf.h> 3389051Sjake#include <sys/kernel.h> 3491617Sjake#include <sys/lock.h> 3589051Sjake#include <sys/mbuf.h> 3689051Sjake#include <sys/malloc.h> 3789051Sjake#include <sys/module.h> 3889051Sjake#include <sys/mutex.h> 3989051Sjake#include <sys/rman.h> 4089051Sjake#include <machine/bus.h> 4191617Sjake 42100899Sjake#include <arm/at91/at91_twireg.h> 4391617Sjake#include <arm/at91/at91var.h> 4491617Sjake 4591617Sjake#include <dev/iicbus/iiconf.h> 4691617Sjake#include <dev/iicbus/iicbus.h> 4791617Sjake#include "iicbus_if.h" 4891617Sjake 4991617Sjake#define TWI_SLOW_CLOCK 1500 5091617Sjake#define TWI_FAST_CLOCK 45000 5191617Sjake#define TWI_FASTEST_CLOCK 90000 52102040Sjake 53102040Sjakestruct at91_twi_softc 5491617Sjake{ 5591617Sjake device_t dev; /* Myself */ 5691617Sjake void *intrhand; /* Interrupt handle */ 5791617Sjake struct resource *irq_res; /* IRQ resource */ 5891617Sjake struct resource *mem_res; /* Memory resource */ 5991617Sjake struct mtx sc_mtx; /* basically a perimeter lock */ 6091617Sjake volatile uint32_t flags; 6191617Sjake uint32_t cwgr; 6291617Sjake int sc_started; 6391617Sjake int twi_addr; 6491617Sjake device_t iicbus; 6591617Sjake}; 6691617Sjake 6791617Sjakestatic inline uint32_t 6891617SjakeRD4(struct at91_twi_softc *sc, bus_size_t off) 69100899Sjake{ 7091617Sjake return bus_read_4(sc->mem_res, off); 7191617Sjake} 7291617Sjake 7391617Sjakestatic inline void 7491617SjakeWR4(struct at91_twi_softc *sc, bus_size_t off, uint32_t val) 7591617Sjake{ 7691617Sjake bus_write_4(sc->mem_res, off, val); 7791617Sjake} 7891617Sjake 7991617Sjake#define AT91_TWI_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 8091617Sjake#define AT91_TWI_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 8191617Sjake#define AT91_TWI_LOCK_INIT(_sc) \ 8291617Sjake mtx_init(&_sc->sc_mtx, device_get_nameunit(_sc->dev), \ 8389051Sjake "twi", MTX_DEF) 8491617Sjake#define AT91_TWI_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx); 8589051Sjake#define AT91_TWI_ASSERT_LOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_OWNED); 8691617Sjake#define AT91_TWI_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_NOTOWNED); 8791617Sjake#define TWI_DEF_CLK 100000 8891617Sjake 8991617Sjakestatic devclass_t at91_twi_devclass; 9091617Sjake 9189051Sjake/* bus entry points */ 9291617Sjake 9391617Sjakestatic int at91_twi_probe(device_t dev); 9491617Sjakestatic int at91_twi_attach(device_t dev); 9589051Sjakestatic int at91_twi_detach(device_t dev); 9691617Sjakestatic void at91_twi_intr(void *); 9789051Sjake 9891617Sjake/* helper routines */ 9991617Sjakestatic int at91_twi_activate(device_t dev); 10091617Sjakestatic void at91_twi_deactivate(device_t dev); 10191617Sjake 10291617Sjakestatic int 10391617Sjakeat91_twi_probe(device_t dev) 10491617Sjake{ 10589051Sjake device_set_desc(dev, "TWI"); 10691617Sjake return (0); 10789051Sjake} 10891617Sjake 10989051Sjakestatic int 11089051Sjakeat91_twi_attach(device_t dev) 11189051Sjake{ 11291617Sjake struct at91_twi_softc *sc = device_get_softc(dev); 11391617Sjake int err; 11489051Sjake 11589051Sjake sc->dev = dev; 11691617Sjake err = at91_twi_activate(dev); 11789051Sjake if (err) 11891617Sjake goto out; 11991617Sjake 12091617Sjake AT91_TWI_LOCK_INIT(sc); 12191617Sjake 12291617Sjake /* 12391617Sjake * Activate the interrupt 12491617Sjake */ 12591783Sjake err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE, 12691617Sjake NULL, at91_twi_intr, sc, &sc->intrhand); 12791783Sjake if (err) { 12889051Sjake AT91_TWI_LOCK_DESTROY(sc); 12989051Sjake goto out; 13089051Sjake } 13189051Sjake sc->cwgr = TWI_CWGR_CKDIV(8 * at91_master_clock / TWI_FASTEST_CLOCK) | 13289051Sjake TWI_CWGR_CHDIV(TWI_CWGR_DIV(TWI_DEF_CLK)) | 13391617Sjake TWI_CWGR_CLDIV(TWI_CWGR_DIV(TWI_DEF_CLK)); 13489051Sjake WR4(sc, TWI_CR, TWI_CR_SWRST); 13589051Sjake WR4(sc, TWI_CR, TWI_CR_MSEN | TWI_CR_SVDIS); 13689051Sjake WR4(sc, TWI_CWGR, sc->cwgr); 13791783Sjake 13891783Sjake if ((sc->iicbus = device_add_child(dev, "iicbus", -1)) == NULL) 13991783Sjake device_printf(dev, "could not allocate iicbus instance\n"); 14089051Sjake /* probe and attach the iicbus */ 14191783Sjake bus_generic_attach(dev); 14289051Sjakeout: 14391783Sjake if (err) 14491783Sjake at91_twi_deactivate(dev); 14589051Sjake return (err); 14691783Sjake} 14791783Sjake 14891783Sjakestatic int 14989051Sjakeat91_twi_detach(device_t dev) 150102040Sjake{ 151102040Sjake struct at91_twi_softc *sc; 15291783Sjake int rv; 15391783Sjake 15489051Sjake sc = device_get_softc(dev); 15589051Sjake at91_twi_deactivate(dev); 15691783Sjake if (sc->iicbus && (rv = device_delete_child(dev, sc->iicbus)) != 0) 15791783Sjake return (rv); 15891783Sjake 15991783Sjake AT91_TWI_LOCK_DESTROY(sc); 16091783Sjake 16189051Sjake return (0); 16289051Sjake} 16389051Sjake 16489051Sjakestatic int 16591783Sjakeat91_twi_activate(device_t dev) 16691617Sjake{ 16791617Sjake struct at91_twi_softc *sc; 16891617Sjake int rid; 16989051Sjake 17089051Sjake sc = device_get_softc(dev); 17189051Sjake rid = 0; 17289051Sjake sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 17389051Sjake RF_ACTIVE); 17489051Sjake if (sc->mem_res == NULL) 17589051Sjake goto errout; 17689051Sjake rid = 0; 17789051Sjake sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 17889051Sjake RF_ACTIVE); 17991783Sjake if (sc->irq_res == NULL) 18089051Sjake goto errout; 18191783Sjake return (0); 18289051Sjakeerrout: 18391783Sjake at91_twi_deactivate(dev); 18489051Sjake return (ENOMEM); 18589051Sjake} 18689051Sjake 18789051Sjakestatic void 18889051Sjakeat91_twi_deactivate(device_t dev) 18989051Sjake{ 19089051Sjake struct at91_twi_softc *sc; 19189051Sjake 19291617Sjake sc = device_get_softc(dev); 19389051Sjake if (sc->intrhand) 19489051Sjake bus_teardown_intr(dev, sc->irq_res, sc->intrhand); 19591617Sjake sc->intrhand = 0; 196 bus_generic_detach(sc->dev); 197 if (sc->mem_res) 198 bus_release_resource(dev, SYS_RES_MEMORY, 199 rman_get_rid(sc->mem_res), sc->mem_res); 200 sc->mem_res = 0; 201 if (sc->irq_res) 202 bus_release_resource(dev, SYS_RES_IRQ, 203 rman_get_rid(sc->irq_res), sc->irq_res); 204 sc->irq_res = 0; 205 return; 206} 207 208static void 209at91_twi_intr(void *xsc) 210{ 211 struct at91_twi_softc *sc = xsc; 212 uint32_t status; 213 214 status = RD4(sc, TWI_SR); 215 if (status == 0) 216 return; 217 AT91_TWI_LOCK(sc); 218 sc->flags |= status & (TWI_SR_OVRE | TWI_SR_UNRE | TWI_SR_NACK); 219 if (status & TWI_SR_RXRDY) 220 sc->flags |= TWI_SR_RXRDY; 221 if (status & TWI_SR_TXRDY) 222 sc->flags |= TWI_SR_TXRDY; 223 if (status & TWI_SR_TXCOMP) 224 sc->flags |= TWI_SR_TXCOMP; 225 WR4(sc, TWI_IDR, status); 226 wakeup(sc); 227 AT91_TWI_UNLOCK(sc); 228 return; 229} 230 231static int 232at91_twi_wait(struct at91_twi_softc *sc, uint32_t bit) 233{ 234 int err = 0; 235 int counter = 100000; 236 uint32_t sr; 237 238 AT91_TWI_ASSERT_LOCKED(sc); 239 while (!((sr = RD4(sc, TWI_SR)) & bit) && counter-- > 0 && 240 !(sr & TWI_SR_NACK)) 241 continue; 242 if (counter <= 0) 243 err = EBUSY; 244 else if (sr & TWI_SR_NACK) 245 err = ENXIO; // iic nack convention 246 return (err); 247} 248 249static int 250at91_twi_rst_card(device_t dev, u_char speed, u_char addr, u_char *oldaddr) 251{ 252 struct at91_twi_softc *sc; 253 int clk; 254 255 sc = device_get_softc(dev); 256 AT91_TWI_LOCK(sc); 257 if (oldaddr) 258 *oldaddr = sc->twi_addr; 259 sc->twi_addr = addr; 260 261 /* 262 * speeds are for 1.5kb/s, 45kb/s and 90kb/s. 263 */ 264 switch (speed) { 265 case IIC_SLOW: 266 clk = TWI_SLOW_CLOCK; 267 break; 268 269 case IIC_FAST: 270 clk = TWI_FAST_CLOCK; 271 break; 272 273 case IIC_UNKNOWN: 274 case IIC_FASTEST: 275 default: 276 clk = TWI_FASTEST_CLOCK; 277 break; 278 } 279 sc->cwgr = TWI_CWGR_CKDIV(1) | TWI_CWGR_CHDIV(TWI_CWGR_DIV(clk)) | 280 TWI_CWGR_CLDIV(TWI_CWGR_DIV(clk)); 281 WR4(sc, TWI_CR, TWI_CR_SWRST); 282 WR4(sc, TWI_CR, TWI_CR_MSEN | TWI_CR_SVDIS); 283 WR4(sc, TWI_CWGR, sc->cwgr); 284 printf("setting cwgr to %#x\n", sc->cwgr); 285 AT91_TWI_UNLOCK(sc); 286 287 return 0; 288} 289 290static int 291at91_twi_callback(device_t dev, int index, caddr_t data) 292{ 293 int error = 0; 294 295 switch (index) { 296 case IIC_REQUEST_BUS: 297 break; 298 299 case IIC_RELEASE_BUS: 300 break; 301 302 default: 303 error = EINVAL; 304 } 305 306 return (error); 307} 308 309static int 310at91_twi_transfer(device_t dev, struct iic_msg *msgs, uint32_t nmsgs) 311{ 312 struct at91_twi_softc *sc; 313 int i, len, err; 314 uint32_t rdwr; 315 uint8_t *buf; 316 uint32_t sr; 317 318 sc = device_get_softc(dev); 319 err = 0; 320 AT91_TWI_LOCK(sc); 321 for (i = 0; i < nmsgs; i++) { 322 /* 323 * The linux atmel driver doesn't use the internal device 324 * address feature of twi. A separate i2c message needs to 325 * be written to use this. 326 * See http://lists.arm.linux.org.uk/pipermail/linux-arm-kernel/2004-September/024411.html 327 * for details. Upon reflection, we could use this as an 328 * optimization, but it is unclear the code bloat will 329 * result in faster/better operations. 330 */ 331 rdwr = (msgs[i].flags & IIC_M_RD) ? TWI_MMR_MREAD : 0; 332 WR4(sc, TWI_MMR, TWI_MMR_DADR(msgs[i].slave) | rdwr); 333 len = msgs[i].len; 334 buf = msgs[i].buf; 335 /* zero byte transfers aren't allowed */ 336 if (len == 0 || buf == NULL) { 337 err = EINVAL; 338 goto out; 339 } 340 if (len == 1 && msgs[i].flags & IIC_M_RD) 341 WR4(sc, TWI_CR, TWI_CR_START | TWI_CR_STOP); 342 else 343 WR4(sc, TWI_CR, TWI_CR_START); 344 if (msgs[i].flags & IIC_M_RD) { 345 sr = RD4(sc, TWI_SR); 346 while (!(sr & TWI_SR_TXCOMP)) { 347 if ((sr = RD4(sc, TWI_SR)) & TWI_SR_RXRDY) { 348 len--; 349 *buf++ = RD4(sc, TWI_RHR) & 0xff; 350 if (len == 1) 351 WR4(sc, TWI_CR, TWI_CR_STOP); 352 } 353 } 354 if (len > 0 || (sr & TWI_SR_NACK)) { 355 err = ENXIO; // iic nack convention 356 goto out; 357 } 358 } else { 359 while (len--) { 360 if ((err = at91_twi_wait(sc, TWI_SR_TXRDY))) 361 goto out; 362 WR4(sc, TWI_THR, *buf++); 363 } 364 } 365 if ((err = at91_twi_wait(sc, TWI_SR_TXCOMP))) 366 break; 367 } 368out: 369 if (err) { 370 WR4(sc, TWI_CR, TWI_CR_SWRST); 371 WR4(sc, TWI_CR, TWI_CR_MSEN | TWI_CR_SVDIS); 372 WR4(sc, TWI_CWGR, sc->cwgr); 373 } 374 AT91_TWI_UNLOCK(sc); 375 return (err); 376} 377 378static device_method_t at91_twi_methods[] = { 379 /* Device interface */ 380 DEVMETHOD(device_probe, at91_twi_probe), 381 DEVMETHOD(device_attach, at91_twi_attach), 382 DEVMETHOD(device_detach, at91_twi_detach), 383 384 /* iicbus interface */ 385 DEVMETHOD(iicbus_callback, at91_twi_callback), 386 DEVMETHOD(iicbus_reset, at91_twi_rst_card), 387 DEVMETHOD(iicbus_transfer, at91_twi_transfer), 388 { 0, 0 } 389}; 390 391static driver_t at91_twi_driver = { 392 "at91_twi", 393 at91_twi_methods, 394 sizeof(struct at91_twi_softc), 395}; 396 397DRIVER_MODULE(at91_twi, atmelarm, at91_twi_driver, at91_twi_devclass, 0, 0); 398DRIVER_MODULE(iicbus, at91_twi, iicbus_driver, iicbus_devclass, 0, 0); 399MODULE_DEPEND(at91_twi, iicbus, 1, 1, 1); 400