at91_streg.h revision 155324 
1155324Simp/*-
2155324Simp * Copyright (c) 2005 M. Warner Losh.  All rights reserved.
3155324Simp *
4155324Simp * Redistribution and use in source and binary forms, with or without
5155324Simp * modification, are permitted provided that the following conditions
6155324Simp * are met:
7155324Simp * 1. Redistributions of source code must retain the above copyright
8155324Simp *    notice, this list of conditions and the following disclaimer.
9155324Simp * 2. Redistributions in binary form must reproduce the above copyright
10155324Simp *    notice, this list of conditions and the following disclaimer in the
11155324Simp *    documentation and/or other materials provided with the distribution.
12155324Simp *
13155324Simp * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
14155324Simp * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
15155324Simp * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
16155324Simp * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
17155324Simp * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
18155324Simp * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
19155324Simp * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
20155324Simp * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21155324Simp * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22155324Simp * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23155324Simp */
24155324Simp
25155324Simp/* $FreeBSD: head/sys/arm/at91/at91_streg.h 155324 2006-02-04 23:32:13Z imp $ */
26155324Simp
27155324Simp#ifndef ARM_AT91_AT91STREG_H
28155324Simp#define ARM_AT91_AT91STREG_H
29155324Simp
30155324Simp#define ST_CR		0x00 /* Control register */
31155324Simp#define ST_PIMR		0x04 /* Period interval mode register */
32155324Simp#define ST_WDMR		0x08 /* Watchdog mode register */
33155324Simp#define ST_RTMR		0x0c /* Real-time mode register */
34155324Simp#define ST_SR		0x10 /* Status register */
35155324Simp#define ST_IER		0x14 /* Interrupt enable register */
36155324Simp#define ST_IDR		0x18 /* Interrupt disable register */
37155324Simp#define ST_IMR		0x1c /* Interrupt mask register */
38155324Simp#define ST_RTAR		0x20 /* Real-time alarm register */
39155324Simp#define	ST_CRTR		0x24 /* Current real-time register */
40155324Simp
41155324Simp/* ST_CR */
42155324Simp#define ST_CR_WDRST	(1U << 0) /* WDRST: Watchdog Timer Restart */
43155324Simp
44155324Simp/* ST_WDMR */
45155324Simp#define ST_WDMR_EXTEN	(1U << 17) /* EXTEN: External Signal Assert Enable */
46155324Simp#define ST_WDMR_RSTEN	(1U << 16) /* RSTEN: Reset Enable */
47155324Simp
48155324Simp/* ST_SR, ST_IER, ST_IDR, ST_IMR */
49155324Simp#define ST_SR_PITS	(1U << 0) /* PITS: Period Interval Timer Status */
50155324Simp#define ST_SR_WDOVF	(1U << 1) /* WDOVF: Watchdog Overflow */
51155324Simp#define ST_SR_RTTINC	(1U << 2) /* RTTINC: Real-time Timer Increment */
52155324Simp#define ST_SR_ALMS	(1U << 3) /* ALMS: Alarm Status */
53155324Simp
54155324Simp/* ST_CRTR */
55155324Simp#define ST_CRTR_MASK	0xfffff /* 20-bit counter */
56155324Simp
57155324Simp#endif /* ARM_AT91_AT91STREG_H */
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